Renesas

OpenAccess: Examples of User Adoption
Renesas' Latest Deployment Status
Renesas Technology America, Inc.

Francis Cheung
10/13/2008 13th Si2/OpenAccess Conference
2008. Renesas Technology America, Inc., All rights reserved.
Rev. 1.00
00000-A
History & Roadmap with OpenAccess

2002
2003
2004
2005
2006
2007
2008
Joined to OA coalition
OA evaluation
Test system development on OA2.1 (Verilog/VHDL-in, incremental RC
extraction, incremental delay calc.)
Beta Test OA 2.2
Deployment Project
Open Design System (DRC)
Integrated into REAP v2.1
Renesas power format
Tr. Level Design Environment
9 Renesas wanted to use EMH features, then we waited for system

development with OA 2.2 release.
9 Almost all designs are using REAP environment at Renesas
Page 1
REAP: Renesas Advanced Design Platform

Renesas has design platform including many internal tools and qualified
commercial tools.
Renesas strongly supports OpenAccess database as a unified data model
of our design system.
System
SystemLevel
LevelDesign
DesignEnvironment
Environment
Std. file I/F

Verilog
VHDL
VCS, (NC-Verilog), SpyGlass

Design Compiler, (RTL-C)
TetraMax, FastScan, TestKompress

In-house LBIST/MBIST tool
Pre-layout Verification VCS, (NC-Verilog), PrimeTime
In-house netlist checkers
DFT
Floor/Power planning IC Compiler, (SoC-E w/ MasterPlan)

P&R
SI Analysis & Fixing
IC Compiler, (SoC-E, Blast Fusion)

PrimTime-SI, PrimeRail, (CeltIC)
(VoltageStorm), CoolTime
Post-layout verification Star-RCXT, PrimeTime
DEF
Layout Verification
REAP
Calibre
Mask Generation
Page 2
Ares
Ares
Extended API
Tcl API
Formal Verification
Logic Synthesis
C++ API
Utilities
Open Access
Extended-Tcl
C++ API
RTL Design
Block / Analog IP model
REAP
REAPv3.x
v3.x
encapsulation
encapsulationlevel
level
(Tcl/Tk,
awk,
perl)
(Tcl/Tk, awk, perl)
Renesas EDA Platform REAP

REAP consists of Standard Design Platform and various additional
Plug-ins.
Standard Design Platform

Additional Functions for Plug-in
Formal Verification
System Level Design
Logic Synthesis
Library
Low Leakage Design

Voltage/Power Domain Interaction Checker
Design Check
Level Shifters/Power Down Isolator Insertion
DFT
Delay Calculation (pre-layout)
Power Design
Floor Planning
STA
Low Power Design

Power Analysis
Power Optimization
P&R
Large Scale Design
LPE
RTL Prototyping
Delay Calculation (post-layout)
SI(IRDrop, Xtalk)
STA
LVS/DRC
Sim.->ATE
OPC
Optical proximity
correction
Memory BIST
High Speed Design

Clock Mesh Generation
Clock Skew Analysis
Logic BIST
RTL Prototyping
Utilities
Verilog/VHDLconv.

Logic BIST
Page 3
Netlist editing
Clock net analysis
REAP Environment with OpenAccess

:Targets of Deployment Proj.
Verilog in
User script
(Python)
DRC check
rules
Power
Spec.
C++ APIs
VHDL out
DEF
Utility
Extended-user APIs
Verilog out
User script
(Tcl)
Extended-Python
VHDL in
Extended-Tcl
REAP2.x Encapsulation Level

(Tcl/Tk, awk, perl)
Verilog/VHDL
netlist
DEF2OA
Utilities
OpenAccess v2.2 or later
EDA
tools
EDAvendor
vendor tools
(OA
supported)
(OA supported)
Verilog/VHDL
netlist
I/Futilities
utilities
I/F
Prototyping
EDA
tools
EDA vendor
vendor tools
(OA not
not supported)
(OA
supported)
OA2DEF
DEF

User
Extensions
Page 4
Data Interface using OA

Renesas
power format
Frontend planner
IOPA
Power implementation
Pwr. spec
IZANAGI
Circuit Analysis
oafunc
NWlib
vhdl2oa
oa2vhdl
VHDL
verilog2oa
oa2verilog
Verilog
pwrspc2oa
OpenAccess
Database
(OADB)
oa2pwrasgn
nwlib2oa
Library for DRC
PrimeTime
Netlister
def2oa
oa2verilog
Verilog
(w/oPG)
VCS/NCsim
GDS
DEF
Verilog
(w/PG)
LVS
LVS

Place & Route

Pwr. Assignment
Verilog
(w/PG)
Verification
Bi-directional
conversion between
Verilog and VHDL
Page 5
Future: Encapsulation Method at REAP

OpenAccess
OADB
OADB
Release
Library
NetWalker
Cellnet
GDS
LEF
etc
C++ API
OA Tcl
Python OA
exe
REAP base-socket package

Tool package
Tool package
Tool package
Tool package
Tool package accesses OA DB

by way of base-socket.

Page 6
Future: IZANAGI
Automatic
Operation
Dataflow
Analysis
IP/design
constraints
input
Paper base study
Automatic FP
generation
Hardmacro size is estimated

Logic area size is estimated
IO area size is estimated
Generated by IZANAGI
IP/design constraints input
Automatic dataflow analysis
Automatic FP generation
->approx 10 minutes.
Layout result
Floorplan
Automatic initial FP generation and constraints validity

can be feedback quickly.
Page 7
REAP Environment with OA

1. High speed netlist conversion
High speed Verilog in/out
High speed VHDL in/out
2. User definable Design Rule Checkers

Use Python as description language
Design specific rule development by designer
3. Tool Plug in/out

Support extended Python & Tcl
Keep encapsulation environment of REAP
Design data access in OpenAccess DB by Tcl is also
supported
4. Reduce design interface data

Disk size, number of interface files
Support Renesas power format which can cover both
CPF and UPF world
Page 8
Prototyping Environment
System Design
Prototyping
Physical Design
Netlist
Netlist
(background method)
System
System Spec.
Spec.
Black
Black Box
Box
RTL
RTL
Generate FP
Floorplan
Floorplan
Function Blocks
SDC
SDC
Logical-Physical
Logical-Physical
Collaboration
Collaboration
Path
Path Analysis
Analysis
Area
Area
Timing
Timing
Power
Power
Path Analysis
Design
Design Topology
Topology
C Level designs
Wire/hierarchy
Wire/hierarchy
Layer/Area:
OpenAccess v2.2 or later

Page 9
Renesas Prototyping Environment
(User Interface)
Tr. Level
Library
IZUMO2 : Cone Base Hierarchical Generation

Utilize the EMH feature in OpenAccess
In Module
Domain
F1
I1
I3
I2
I5
F3
F2 Good for logical
understanding by
logic designer
I4
Logical Hierarchy
F1-F2
In Block
Domain
F1
F1-F2-F3
I3
Level 0:same FFIDs
Level 1:include FFIDs
Level 2:connect FFIDs
Level 3: merge FF
F1-F3-F2
F1-F2
I1
I2
F3
IZUMO2
F3-F2
I5
F2
I4
Good for timing

optimization by
physical designer
Cone Base Physical Hierarchy

Have to maintain both hierarchies in one

single database -> OpenAccess EMH
Page 10
IZUMO2 - Example
Clock Gating Cells
Original
Logical
Hierarchy
Combinational & FF modules
IZUMO2
Cone Base
Physical
Hierarchy
Clock Gating
Cluster
Combinational clusters
FF clusters
Page 11
Summary
Almost all designs at Renesas are developed using
OpenAccess
OpenAccess can be unified for different design environments
especially power format (CPF/UPF)
Performance needs further improvement.
We are moving to the OpenAccess environment with transistor
level for mixed signal designs.

Page 12
Renesas Technology America, Inc.


Renesas

Uploaded by

Copyright:

Available Formats

Renesas

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Renesas

Uploaded by

Copyright:

Available Formats

OpenAccess: Examples of User Adoption

Renesas' Latest Deployment Status

Renesas Technology America, Inc.

10/13/2008 13th Si2/OpenAccess Conference

2008. Renesas Technology America, Inc., All rights reserved.

History & Roadmap with OpenAccess

9 Renesas wanted to use EMH features, then we waited for system

REAP: Renesas Advanced Design Platform

Std. file I/F

VCS, (NC-Verilog), SpyGlass

TetraMax, FastScan, TestKompress

Floor/Power planning IC Compiler, (SoC-E w/ MasterPlan)

IC Compiler, (SoC-E, Blast Fusion)

Post-layout verification Star-RCXT, PrimeTime

10/13/2008 13th Si2/OpenAccess Conference

2008. Renesas Technology America, Inc., All rights reserved.

Block / Analog IP model

Renesas EDA Platform REAP

Standard Design Platform

System Level Design

Low Leakage Design

Level Shifters/Power Down Isolator Insertion

Low Power Design

Large Scale Design

Delay Calculation (post-layout)

High Speed Design

10/13/2008 13th Si2/OpenAccess Conference

Clock net analysis

REAP Environment with OpenAccess

REAP2.x Encapsulation Level

OpenAccess v2.2 or later

10/13/2008 13th Si2/OpenAccess Conference

Data Interface using OA

Library for DRC

10/13/2008 13th Si2/OpenAccess Conference

Place & Route

Future: Encapsulation Method at REAP

REAP base-socket package

Tool package accesses OA DB

10/13/2008 13th Si2/OpenAccess Conference

Paper base study

Hardmacro size is estimated

Automatic initial FP generation and constraints validity

REAP Environment with OA

2. User definable Design Rule Checkers

3. Tool Plug in/out

4. Reduce design interface data

OpenAccess v2.2 or later

Renesas Prototyping Environment

IZUMO2 : Cone Base Hierarchical Generation

F2 Good for logical

Good for timing

Cone Base Physical Hierarchy

10/13/2008 13th Si2/OpenAccess Conference

Have to maintain both hierarchies in one

10/13/2008 13th Si2/OpenAccess Conference

Renesas Technology America, Inc.

You might also like