11 Robust Verification

数字集成电路静态时序分析基础
邸志雄博士, zxdi@home.swjtu.edu.cn
西南交通大学信息科学与技术学院
Copyright © 2018 芃苇_PengV. All Rights Reserved.

Part 6: Robust Verification
On-Chip Variations
1. Setup time check

2. Hold time check

On-Chip Variations
In general, the process and environmental parameters may not be uniform

across different portions of the die.
Due to process variations, identical MOS transistors in different portions of the
die may not have similar characteristics. These differences are due to process
variations within the die.

On-Chip Variations
These differences can arise due to many factors, including:
 i. IR drop variation along the die area affecting the local power supply.
 ii.Voltage threshold variation of the PMOS or the NMOS device.
 iii. Channel length variation of the PMOS or the NMOS device.
 iv. Temperature variations due to local hot spots.
 v. Interconnect metal etch or thickness variations impacting the interconnect resistance or
capacitance.
The PVT variations described above are referred to as On-Chip Variations (OCV) and these
variations can affect the wire delays and cell delays in different portions of the chip.
On-Chip Variations
Since the clock and data paths can be affected differently by the OCV, the
timing verification can model the OCV effect by making the PVT conditions for
the launch and capture paths to be slightly different.
The STA can include the OCV effect by derating the delays of specific paths, that
is, by making those paths faster or slower and then validating the behavior of
the design with these variations.
The cell delays or wire delays or both can be derated to model the effect of
OCV. Copyright © 2018 芃苇_PengV. All Rights Reserved.
On-Chip Variations
We now examine how the OCV derating is done for a setup check.
The worst condition for setup check occurs when the launch clock path and the data path have the OCV
conditions which result in the largest delays, while the capture clock path has the OCV conditions which
result in the smallest delays.
On-Chip Variations
For this example, here is the setup timing check condition; this does not include
any OCV setting for derating delays.
LaunchClockPath + MaxDataPath <= ClockPeriod +

CaptureClockPath - Tsetup_UFF1
This implies that the minimum clock period = LaunchClockPath

+ MaxDataPath - CaptureClockPath + Tsetup_UFF1

On-Chip Variations
From the figure,

LaunchClockPath = 1.2 + 0.8 = 2.0
MaxDataPath = 5.2
CaptureClockPath = 1.2 + 0.86 = 2.06
Tsetup_UFF1 = 0.35
This results in a minimum clock period of:

2.0 + 5.2 – 2.06 + 0.35 = 5.49ns

On-Chip Variations
The above path delays correspond to the delay values without any OCV
derating. Cell and net delays can be derated using the set_timing_derate
specification.
For example, the commands:
set_timing_derate -early 0.8
set_timing_derate -late 1.1

On-Chip Variations
Derate the minimum/shortest/early paths by -20% and derate the

maximum/longest/latest paths by +10%.
 Long path delays (for example, data paths and launch clock path for setup
checks or capture clock paths for hold checks) are multiplied by the derate
value specified using the -late option.
 Short path delays (for example, capture clock paths for setup checks or data
paths and launch clock paths for hold checks) are multiplied by the derate
values specified using the -early option.
If no derating factors are specified, a value of 1.0 is assumed
On-Chip Variations
The derating factors apply uniformly to all net delays and cell delays.
If an application scenario warrants different derating factors for cells and nets,
the -cell_delay and the -net_delay options can be used in the
set_timing_derate specification.

On-Chip Variations
We now apply the following derating to the example.

set_timing_derate -late 1.1 -cell_check

On-Chip Variations
With these derating values, we get the following for setup check:
LaunchClockPath = 2.0 * 1.2 = 2.4
MaxDataPath = 5.2 * 1.2 = 6.24
CaptureClockPath = 2.06 * 0.9 = 1.854
Tsetup_UFF1 = 0.35 * 1.1 = 0.385
This results in a minimum clock period of:
2.4 + 6.24 – 1.854 + 0.385 = 7.171ns

On-Chip Variations
In the setup check above, there is a discrepancy since the common clock
path of the clock tree, with a delay of 1.2ns, is being derated differently for
the launch clock and for the capture clock.
This part of the clock tree is common to both the launch clock and the
capture clock and should not be derated differently.

On-Chip Variations
Applying different derating for the launch and capture clock is overly
pessimistic as in reality this part of the clock tree will really be at only one PVT
condition, either as a maximum path or as a minimum path (or anything in
between) but never both at the same time.

On-Chip Variations
The pessimism caused by different derating factors applied on the common

part of the clock tree is called Common Path Pessimism (CPP) which should
be removed during the analysis.
CPPR, which stands for Common Path Pessimism Removal, is often listed
as a separate item in a path report. It is also labeled as Clock Reconvergence
Pessimism Removal (CRPR).

On-Chip Variations
CPPR is the removal of artificially induced pessimism between the launch

clock path and the capture clock path in timing analysis.
If the same clock drives both the capture and the launch flip-flops, then the
clock tree will likely share a common portion before branching.

On-Chip Variations
The common point is defined as the output pin of the last cell in the common
portion of the clock tree.
CPP = LatestArrivalTime@CommonPoint – EarliestArrivalTime@CommonPoint

On-Chip Variations
The Latest and Earliest times in the above analysis are in reference to the OCV derating at a
specific timing corner - for example worst-case slow or best-case fast.
LatestArrivalTime@CommonPoint = 1.2 * 1.2 = 1.44

EarliestArrivalTime@CommonPoint = 1.2 * 0.9 = 1.08
This implies a CPP of: 1.44 - 1.08 = 0.36ns
With the CPP correction, this results in a

minimum clock period of: 7.171 - 0.36 = 6.811ns

On-Chip Variations
Applying the OCV derating has increased the minimum clock period from
5.49ns to 6.811ns for this example design.
This illustrates that the OCV variations modeled by these derating factors can
reduce the maximum frequency of operation of the design.

On-Chip Variations
Analysis with OCV at Worst PVT Condition
If the setup timing check is being performed at the worst-case PVT condition,
no derating is necessary on the late paths as they are already the worst possible.
However, derating can be applied to the early paths by making those paths
faster by using a specific derating, for example, speeding up the early paths by
10%.

On-Chip Variations
A derate specification at the worst-case slow corner may be something like:

# Don’t derate the late paths as they are already the slowest,
# but derate the early paths to make these faster by 10%.

On-Chip Variations

The above derate settings are for max path (or setup) checks at the worstcase
slow corner; thus the late path OCV derate setting is kept at 1.0 so as not to slow
it beyond the worst-case slow corner.

On-Chip Variations
Here is the setup timing check path report performed at the worst-case slow
corner. The derating used by the late paths are reported as Max Data Paths
Derating Factor and as Max Clock Paths Derating Factor.
The derating used for the early paths is reported as Min Clock Paths Derating
Factor.

On-Chip Variations

On-Chip Variations

On-Chip Variations
The cell UCKBUF0 is on the common clock path, that is, on both the capture
clock path and the launch clock path.
Since the common clock path cannot have a different derating, the difference
in timing for this common path, 56ps - 45ps = 11ps, is corrected separately.

Part 6: Robust Verification
On-Chip Variations
1. Setup time check

2. Hold time check

On-Chip Variations
OCV for Hold Checks
If the PVT conditions are different along the chip, the worst condition for hold
check occurs：
when the launch clock path and the data path have OCV conditions which
result in the smallest delays, that is, when we have the earliest launch clock, and
the capture clock path has the OCV conditions which result in the largest
delays, that is, has the latest capture clock

On-Chip Variations
OCV for Hold Checks
The hold timing check is specified in the following expression for this example.
LaunchClockPath + MinDataPath - CaptureClockPath - Thold_UFF1 >= 0

On-Chip Variations
OCV for Hold Checks
Applying the delay values in the Figure 10-2 to the expression, we get (without applying any derating):
LaunchClockPath = 0.25 + 0.6 = 0.85
MinDataPath = 1.7
CaptureClockPath = 0.25 + 0.75 = 1.00
Thold_UFF1 = 1.25
This implies that the condition is:

0.85 + 1.7 – 1.00 - 1.25 = 0.3n >=0
which is true, and thus no hold violation
exists.
On-Chip Variations
OCV for Hold Checks
Applying the following derate specification:

set_timing_derate -early 0.95 -cell_check

On-Chip Variations
OCV for Hold Checks
LaunchClockPath = 0.85 * 0.9 = 0.765

MinDataPath = 1.7 * 0.9 = 1.53
CaptureClockPath = 1.00 * 1.2 = 1.2
Thold_UFF1 = 1.25 * 0.95 = 1.1875
Common clock path pessimism:

0.25 * (1.2 - 0.9) = 0.075
The hold check condition then becomes:

0.765 + 1.53 – 1.2 - 1.1875 + 0.075 =C-0.0175ns <苇0_ P e n g V . A l l R i g h t s R e s e r v e d .
opyright © 2018 芃
On-Chip Variations
OCV for Hold Checks
In general, the hold timing check is performed at the best-case fast PVT corner.
In such a scenario, no derating is necessary on the early paths, as those paths
are already the earliest possible.
However, derating can be applied on the late paths by making these slower by a
specific derating factor, for example, slowing the late paths by 20.

On-Chip Variations
OCV for Hold Checks
A derate specification at this corner would be something like:

# Don’t derate the early paths as they are already the
# fastest, but derate the late paths slower by 20%.

On-Chip Variations
OCV for Hold Checks
In the example of Figure 10-2,

LatestArrivalTime@CommonPoint
= 0.25 * 1.2 = 0.30
EarliestArrivalTime@CommonPoint
= 0.25 * 1.0 = 0.25
This implies a common path pessimism of:
0.30 - 0.25 = 0.05ns

On-Chip Variations
OCV for Hold Checks

On-Chip Variations
OCV for Hold Checks

On-Chip Variations
OCV for Hold Checks
Notice that the late paths are derated by +20% while the early paths are not derated. See cell
UCKBUF0.
Its delay on the launch path is 56ps while the delay on the capture path is 67ps - derated by
+20%.
UCKBUF0 is the cell on the common clock tree and thus the pessimism introduced due to
different derating on this common clock tree is, 67ps - 56ps = 11ps, which is accounted for
separately on the line clock reconvergence pessimism.

参考书目
 Static Timing Analysis for Nanometer Designs: A Practical Approach. J.

Bhasker, Rakesh Chadha. Springer Science Business Media, LLC 2009.
 集成电路静态时序分析与建模. 刘峰, 机械工业出版社.出版时间：2016-07-01.

谢谢聆听！
https://customizablecomputinglab.github.io/
个人教学工作主页https://customizablecomputinglab.github.io/

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数字集成电路静态时序分析基础

邸志雄 博士, zxdi@home.swjtu.edu.cn

Copyright © 2018 芃苇_PengV. All Rights Reserved.

1. Setup time check

Copyright © 2018 芃苇_PengV. All Rights Reserved.

In general, the process and environmental parameters may not be uniform

Copyright © 2018 芃苇_PengV. All Rights Reserved.

These differences can arise due to many factors, including:

LaunchClockPath + MaxDataPath <= ClockPeriod +

This implies that the minimum clock period = LaunchClockPath

Copyright © 2018 芃苇_PengV. All Rights Reserved.

From the figure,

This results in a minimum clock period of:

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Derate the minimum/shortest/early paths by -20% and derate the

Copyright © 2018 芃苇_PengV. All Rights Reserved.

We now apply the following derating to the example.

set_timing_derate -early 0.9

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Copyright © 2018 芃苇_PengV. All Rights Reserved.

The pessimism caused by different derating factors applied on the common

Copyright © 2018 芃苇_PengV. All Rights Reserved.

CPPR is the removal of artificially induced pessimism between the launch

Copyright © 2018 芃苇_PengV. All Rights Reserved.

CPP = LatestArrivalTime@CommonPoint – EarliestArrivalTime@CommonPoint

Copyright © 2018 芃苇_PengV. All Rights Reserved.

LatestArrivalTime@CommonPoint = 1.2 * 1.2 = 1.44

With the CPP correction, this results in a

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Analysis with OCV at Worst PVT Condition

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Analysis with OCV at Worst PVT Condition

A derate specification at the worst-case slow corner may be something like:

set_timing_derate -early 0.9

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Analysis with OCV at Worst PVT Condition

set_timing_derate -early 0.9

Copyright © 2018 芃苇_PengV. All Rights Reserved.

Analysis with OCV at Worst PVT Condition

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Analysis with OCV at Worst PVT Condition

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Analysis with OCV at Worst PVT Condition

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Analysis with OCV at Worst PVT Condition

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1. Setup time check

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OCV for Hold Checks

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OCV for Hold Checks

LaunchClockPath + MinDataPath - CaptureClockPath - Thold_UFF1 >= 0

Copyright © 2018 芃苇_PengV. All Rights Reserved.

OCV for Hold Checks

This implies that the condition is:

OCV for Hold Checks

邸志雄博士, zxdi@home.swjtu.edu.cn