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    8 建立时间与保持时间检查

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    MULLAIVANESH A V
    The document discusses static timing analysis fundamentals, including setup timing checks and hold timing checks. It explains the different timing paths that must be verified such as flip-flop to flip-flop, input to flip-flop, flip-flop to output, and input to output. It also describes how to model these timing paths, add constraints, and calculate slack for setup and hold checks in static timing analysis.

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    8 建立时间与保持时间检查

    Uploaded by

    MULLAIVANESH A V
    38 views44 pages
    The document discusses static timing analysis fundamentals, including setup timing checks and hold timing checks. It explains the different timing paths that must be verified such as flip-flop to flip-flop, input to flip-flop, flip-flop to output, and input to output. It also describes how to model these timing paths, add constraints, and calculate slack for setup and hold checks in static timing analysis.

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    8-建立时间与保持时间检查

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    The document discusses static timing analysis fundamentals, including setup timing checks and hold timing checks. It explains the different timing paths that must be verified such as flip-flop to flip-flop, input to flip-flop, flip-flop to output, and input to output. It also describes how to model these timing paths, add constraints, and calculate slack for setup and hold checks in static timing analysis.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    38 views44 pages

    8 建立时间与保持时间检查

    Uploaded by

    MULLAIVANESH A V
    The document discusses static timing analysis fundamentals, including setup timing checks and hold timing checks. It explains the different timing paths that must be verified such as flip-flop to flip-flop, input to flip-flop, flip-flop to output, and input to output. It also describes how to model these timing paths, add constraints, and calculate slack for setup and hold checks in static timing analysis.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 44

    数字集成电路静态时序分析基础

    邸志雄 博士, zxdi@home.swjtu.edu.cn

    西南交通大学信息科学与技术学院

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Part 5: Timing Verification

    1. Setup timing check


    2. Hold timing check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    1、Flip-flop to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    1、Flip-flop to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    2、Input to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Timing Analysis——Setup Timing Check

    Constrain：

    creat_clock –name VIRTUAL_CLKM –period 10 –waveform {0 5}

    set_input_delay –clock VIRTUAL_CLKM –max 2.55 [get_ports INA]

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    2、Input to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    2、Input to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    3、Flip-flop to Output Path

    Similar to the input port constraint described above, an output port can be constrained
    either with respect to a virtual clock, or an internal clock of the design, or an input clock
    port, or an output clock port.

    To determine the delay of the last cell connected to the output port correctly, one needs
    to specify the load on this port. The output load is specified above using the set_load
    command.

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    3、Flip-flop to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    3、Flip-flop to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    3、Flip-flop to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    3、Flip-flop to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    4、Input to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    4、Input to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    4、Input to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Setup Timing Check

    4、Input to Output Path

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    Setup Timing Check

    4、Input to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Part 5: Timing Verification

    1. Setup timing check


    2. Hold timing check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Just like the setup check, a hold timing check is between the launch flipflop -
    the flip-flop that launches the data, and the capture flip-flop - the flip-flop that
    captures the data and whose hold time must be satisfied.
    The clocks to these two flip-flops can be the same or can be different.

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

     The hold check is from one active edge of the clock in the launch flip-flop

    to the same clock edge at the capture flip-flop.

     Thus, a hold check is independent of the clock period.

     The hold check is carried out on each active edge of the clock of the

    capture flip-flop.

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    Hold Slack Calculation：


     An interesting point to note is the difference in the way the slack is
    computed for setup and hold timing reports.
     In the setup timing reports, the arrival time and the required time are
    computed and the slack is computed to be the required time minus arrival
    time.

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    1、Input to Flip-flop Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.

    set_input_delay -clock VIRTUAL_CLKM \ -min 1.1 [get_ports INA]


    Hold Timing Check

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

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    Hold Timing Check

    2、Flip-flop to Output Path

    set_output_delay -clock VIRTUAL_CLKP


    Copyrig \l l-min
    ht © 2018 芃苇_PengV. A 2.5
    Rights R e s e r[get_ports
    ved. ROUT]
    Hold Timing Check

    2、Flip-flop to Output Path

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    Hold Timing Check

    2、Flip-flop to Output Path

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    Hold Timing Check

    3、Input to Output Path

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    Hold Timing Check

    3、Input to Output Path

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    Hold Timing Check

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    Hold Timing Check

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    Conclusion-Setup Timing Check

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    Conclusion-Hold Timing Check

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    参考书目

     Static Timing Analysis for Nanometer Designs: A Practical Approach. J.


    Bhasker, Rakesh Chadha. Springer Science Business Media, LLC 2009.
    Chaper 7.
     集成电路静态时序分析与建模. 刘峰, 机械工业出版社.出版时间：2016-07-01.
    第六章.

    Copyright © 2018 芃苇_PengV. All Rights Reserved.


    谢谢聆听！
    https://customizablecomputinglab.github.io/
    个人教学工作主页https://customizablecomputinglab.github.io/

    Copyright © 2018 芃苇_PengV. All Rights Reserved.

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