Ee 382M Vlsi-Ii Class Overview Fall 2008: Mark Mcdermott
Ee 382M Vlsi-Ii Class Overview Fall 2008: Mark Mcdermott
Mark McDermott
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EE 382M VLSI - II
Instructor(s): Peter Hofstee, Kevin Nowka, Byron Krauter, Gian Gerosa, Steve Sullivan, Matt Amatangelo, Hector Sanchez, Jerry Moench, Romi Datta Mark McDermott
Office: ENS 425 Office hours: By appointment
TAs: Eun Jung Jang Prerequisite: Graduate VLSI-I, logic design, basic computer architecture. Web URL: http://www.ece.utexas.edu/~mcdermot/ Lecture notes, homework, exercises will be posted on the web.
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This class will introduce you to the tools that are needed to solve VLSI design planning, circuit design and integration problems. There will be 4 homework problems and a team class project which will help you to practice using these tools and techniques. The class provides examples of current design techniques, so that you can evaluate them and come to your own conclusions about their application to the real world. This experimentation will help you with building the foundation you need, to choose the appropriate circuits and simulation methods to solve your problems.
EE 382M Class Notes
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MS System Design
Bottom-Up
Feedback
Analog-2
VLSI-II
Analog-1
Cells
VLSI-I
Cell Level
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Design Phases
Design Specs & Netlist Cell Libraries
Design Analysis
Early Phase: Design Planning Mid Phase: Design Construction Late Phase: Design Tuning
Data Management
Design Validation
Estimated
Structured Netlist
Consistency
Mixed
Mapped Netlist
Partial
Extracted
Schematic Netlist
Design Database
Full
Suggested Reading
Chandrakasan, Bowhill, Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2000. Bernstein, et al., High Speed CMOS Design Styles, Kluwer Academic Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publishers Weste and Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective (second edition), Addison Wesley Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison Wesley
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Homework
Homework is designed for you to get experience with DSM technology and simulation and to experiment with new design techniques. HW Problems are posted on the web and are due in about 4 weeks. Problems MUST be worked out on your own. DO NOT share your work. No late assignments - Late submission of homework and lab exercises will result in a 25% penalty per day. (Max penalty: 100% - Yes it is tough, but so is the real world). HW must be submitted at the beginning of class. Other homework you must do: Read the course notes. Be prepared before coming to class.
EE 382M Class Notes
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Class Project
Project assignment: Project is focused on the early design planning, timing and optimization of an Open Cores processor core. Project will be reviewed during the last 2 days of the class.
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Collaboration is good!
Collaboration is good!
Discussing issues with your classmates is a good way to learn and a study group is a very effective learning tool Helping each other learn is particularly satisfying But....Individual assignments and exams must be done by individuals
Take some free advice from me: Dont cheat, its not worth it
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