Course Work - Exams Only
Course Work - Exams Only
Course Work - Exams Only
Course Title
No. Code CODE
Long Term
8 Advances in Low Power VLSI
20EVE12 ASIC Design 20EVE241 20EVE251 20EVE14 VLSI Testing 20EVE23 System Verilog 20EVE334 Reliability of
(VLSI related) VLSI Design Design
VLSI Systems
Approved Ph. D Coursework Examination Courses
GROUP 1
Sl.
Course Code Course Name
No.
7 20EVE242 Nanoelectronics
Module-1
Introduction to ASICs: Full custom, Semi-custom and Programmable ASICs, ASIC Design flow, ASIC
cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry
save, Carry select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell
Compilers.
Module-2
ASIC Library Design: Logical effort: Predicting Delay, Logical area and logical efficiency, Logical
paths, Multi stage cells, Optimum delay and number of stages, library cell design.
Programmable ASIC Logic Cells:
MUX as Boolean function generators, Acted ACT: ACT 1, ACT 2 and ACT 3 Logic Modules, Xilinx LCA:
XC3000 CLB, Altera FLEX and MAX, Programmable ASIC I/O Cells: Xilinx and Altera I/O Block.
Module-3
Low-level design entry: Schematic entry: Hierarchical design, The cell library, Names, Schematic
Icons & Symbols, Nets, Schematic Entry for ASICs, Connections, vectored instances & buses, Edit in
place, attributes, Netlist screener.
ASIC Construction: Physical Design, CAD Tools System partitioning, Estimating ASIC size.
Partitioning: Goals and objectives, Constructive Partitioning, Iterative Partitioning Improvement,
KL, FM and Look Ahead algorithms.
Module-4
Floor planning and placement: Goals and objectives, Measurement of delay in Floor planning,
Floor planning tools, Channel definition, I/O and Power planning and Clock planning.
Placement: Goals and Objectives, Min-cut Placement algorithm, Iterative Placement Improvement,
Time driven placement methods, Physical Design Flow.
Module-5
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between
blocks, Back-annotation. Detailed Routing: Goals and objectives, Measurement of Channel Density,
Left-Edge Algorithm, Area-Routing Algorithms, Multilevel routing, Timing –Driven detailed routing,
Final routing steps, Special Routing, Circuit extraction and DRC.
Textbook
‘Application - Specific Integrated Circuits’, Michael John Sebastian Smith, Addison- Wesley
Professional, 2005
03.09.2020
Reference Books
1. ‘CMOS VLSI Design: A Circuits and Systems Perspective’, Neil H.E. Weste, David Harris and
Ayan Banerjee, Addison Wesley/ Pearson education, 3rd edition, 2011
2. ‘VLSI Design: A Practical Guide for FPGA and ASIC Implementations’, Vikram Arkalgud
Chandrasetty, Springer, ISBN: 978-1-4614-1119-2 , 2011
3. ‘An ASIC Low Power Primer’, Rakesh Chadha, Bhasker J , Springer, ISBN: 978-14614-4270-7
Approved Ph. D Coursework Examination Courses
GROUP 4
Sl.
Course Code Course Name
No.
Module-1
Faults in digital circuits: Failures and Faults, Modeling of faults, Temporary Faults. (Text 1)
Logic Simulation: Applications, Problems in simulation based design verification, types of
simulation, The unknown logic values, compiled simulation, event-driven simulation, Delay models,
Element evaluation, Hazard detection, Gate-level event-driven Simulation. (Text 2)
Module-2
Test generation for Combinational Logic circuits: Fault Diagnosis of digital circuits, Test
generation techniques for combinational circuits, Detection of multiple faults in Combinational logic
circuits. (Text 1)
Testable Combinational logic circuit design: The Read-Muller expansion technique, Three level
OR-AND-OR design, Automatic synthesis of testable logic. (Text 1)
Module-3
Testable Combinational logic circuit design: Testable design of multilevel combinational circuits,
Synthesis of random pattern testable combinational circuits, Path delay fault testable combinational
logic design, Testable PLA design. (Text 1)
Test generation for Sequential circuits: Testing of sequential circuits as Iterative combinational
circuits, state table verification, Test generation based on Circuit Structure, Functional Fault
models, test Generation based on Functional Fault models. (Text 1)
Module-4
Design of testable sequential circuits: Controllability and observability, Ad-Hoc design rules for
improving testability, design of diagnosable sequential circuits, the scan-path technique for testable
sequential circuit design, Level Sensitive Scan Design (LSSD), Random Access Scan Technique,
Partial scan, testable sequential circuit design using Nonscan Techniques, Cross check, Boundary
Scan. (Text 1)
Module-5
Built-In Self Test: Test pattern generation for BIST, Output response analysis, Circular BIST, BIST
Architectures. (Text 1)
Testable Memory Design: RAM Fault Models, Test algorithms for RAMs, Detection of pattern-
sensitive faults, BIST techniques for RAM chips, Test generation and BIST for embedded RAMs.
(Text1)
Textbooks
1. ‘Digital Circuit Testing and Testability’, Lala Parag K, New York, Academic Press, 1997
2. ‘Digital Systems Testing and Testable Design’, Abramovici M, Breuer M A and Friedman A D,
Wiley, 1994
Reference Books
1. ‘Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits’, Vishwani D
Agarwal, Springer, 2002
2. ‘VLSI Test Principles and Architectures’, Wang, Wu and Wen, Morgan Kaufmann, 2006
Approved Ph. D Coursework Examination Courses
GROUP 6
Sl.
Course Code Course Name
No.
Module-1
Electromigration Reliability
Why Electromigration Reliability?, Why system-level EM Reliability Management? Physics- based
EM Modeling, Electromigration Fundamentals, Stress based EM Modeling and stress diffusion
equations, Modeling for transient EM effects and Initial stress conditions, post voiding stress and
void volume evolution, compact physics based EM model for a single wire, other relevant EM
models and analysis methods. (Text Book:1 – 1.1, 1.2, 2.1 up to 2.6, 2.9).
Module-2
Fast EM Stress Evolution Analysis
Introduction, The LTI ordinary differential equations for EM stress evolution, The presented Krylov
fast EM stress analysis, Numerical results and discussions (Text. Book:1 – 3.1 up to 3.4).
Module-3
EM Assessment for Power Grid Networks
New power grid reliability analysis method, cross-layout temperature and thermal stress
characterization, impact of across-layout temperature and thermal stress on EM. (Text.Book:1 – 7.1,
7.2, 7.4, 7.5).
Module-4
Transistor Aging Effects and Reliability:
Introduction, Transistor reliability in advanced technology nodes, Transistor Aging, BTI- Bias
Temperature Instability, HCI – Hot Carrier Injection, Coupling models for BTI and HCI degradations,
RTN – Random Telegraph Noise, TDDB – Time Dependent Dielectric Breakdown. (Text Book: 1 –
13.1, 13.2).
Module-5
Aging Effects in Sequential Elements:
Introduction, Background: flip flop timing analysis, process variation model, voltage droop model,
Robustness analysis, reliability-aware flip-flop design (Text Book: 1 – 16.1 up to 16.4).
Textbook
‘Long-Term Reliability of Nanometer VLSI Systems’, Sheldon X. D. Tan, Mehdi Baradaran
Tahoori, Taeyoung Kim, Saman Kiamehr, Zeyu Sun, Shengcheng Wang, Springer International
Publishing, 1st Edition, 2019, ISBN: 978-3-030-26171-9
Reference Books