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Course Work - Exams Only

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Group Course UNIQUE

Course Title
No. Code CODE

1 20ECS14 Advanced Communication Systems - 1 201EC001


1 20ECS12 Advanced Digital Signal Processing 201EC002
1 20ELD14 Digital Circuits and Logic Design 201EC003
1 20ECS333 Internet of Things 201EC004
1 20ELD11 Advanced Engineering Mathematics 201EC005
1 20ELD21 Advanced Computer Architecture 201EC006
1 20EVE242 Nanoelectronics 201EC007
1 20EVE12 ASIC Design 201EC008

2 20ECS21 Advanced Communication Systems - 2 202EC001


2 20ESP15 Digital Compression 202EC002
2 20EVE21 Design of Analog and Mixed Mode VLSI Circuits 202EC003
2 20ESP21 Image Processing and Machine Vision 202EC004
2 20EIE15 Advanced Control System 202EC005
2 20ECS15 Advanced Computer Communication Networks 202EC006
2 20EVE254 High Frequency GaN Electronic Devices 202EC007
2 20EVE241 Advances in VLSI Design 202EC008

3 20ECS23 Error Control Coding 203EC001


3 20ESP321 Array Signal Processing 203EC002
3 20EIE251 Automotive Electronics 203EC003
3 20EVE321 Machine Learning in VLSI CAD 203EC004
3 20EIE21 Process Control Instrumentation 203EC005
3 20ECS243 Cryptography and Network Security 203EC006
3 20ELD253 Micro Electro Mechanical Systems 203EC007
3 20EVE251 Low Power VLSI Design 203EC008

4 20ECS22 Antenna Theory and Design 204EC001


4 20ESP324 Speech and Audio Processing 204EC002
4 20EVE252 SoC Design 204EC003
4 20ESP332 Pattern Recognition & Machine Learning 204EC004
4 20EIE252 Industrial Drives 204EC005
4 20ELD323 Business Intelligence and its Applications 204EC006
4 20EVE331 VLSI Design for Signal Processing 204EC007
4 20EVE14 VLSI Testing 204EC008

5 20ECS244 Optical Communication and Networking 205EC001


5 20ESP31 Adaptive Signal Processing 205EC002
5 20EVE322 CMOS RF Circuit Design 205EC003
5 20SCS322 Virtual Reality 205EC004
Advanced Power Electronic Converters and
5 20EIE331 205EC005
Applications
5 20ECS241 Wireless Sensor Networks 205EC006
5 20EVE244 Reconfigurable Computing 205EC007
5 20EVE23 System Verilog 205EC008

6 20ECS251 Multimedia Over Communication Links 206EC001


6 20ESP251 Biomedical Signal Processing 206EC002
6 20ECS331 RF and Microwave Circuit Design 206EC003
6 20SCS23 Blockchain Technology 206EC004
6 20ECS254 Simulation, Modelling and Analysis 206EC005
6 20ECS31 LTE 4G Broadband 206EC006
6 20EIE322 Medical Imaging 206EC007
6 20EVE334 Long Term Reliability of VLSI Systems 206EC008
Approved Ph. D Coursework Examination Courses under ECE Board with Course Codes as per 2020 M. Tech Scheme

Sl. No. GROUP 1 GROUP 2 GROUP 3 GROUP 4 GROUP 5 GROUP 6


Optical Multimedia
1 Advanced Advanced Antenna
Error Control Communication Over
(Communication 20ECS14 Communication 20ECS21 Communication 20ECS23 20ECS22 Theory and 20ECS244 20ECS251
Coding and Communication
related) Systems - 1 Systems - 2 Design
Networking Links
2
Advanced Speech and Biomedical
(Signal Digital Array Signal Adaptive Signal
20ECS12 Digital Signal 20ESP15 20ESP321 20ESP324 Audio 20ESP31 20ESP251 Signal
processing Compression Processing Processing
Processing Processing Processing
related)
Design of
3 Digital Circuits RF and
Analog and Automotive CMOS RF
(Devices and 20ELD14 and Logic 20EVE21 20EIE251 20EVE252 SoC Design 20EVE322 20ECS331 Microwave
Mixed Mode Electronics Circuit Design
circuits related) Design Circuit Design
VLSI Circuits
Pattern
4 Image Machine
Internet of Recognition Blockchain
(IoT and ML 20ECS333 20ESP21 Processing and 20EVE321 Learning in VLSI 20ESP332 20SCS322 Virtual Reality 20SCS23
Things & Machine Technology
related) Machine Vision CAD
Learning
Advanced
5 Advanced Power Simulation,
Advanced Process Control Industrial
(Process control 20ELD11 Engineering 20EIE15 20EIE21 20EIE252 20EIE331 Electronic 20ECS254 Modeling and
Control System Instrumentation Drives
& allied) Mathematics Converters and Analysis
Applications
Advanced Business
6 Advanced Cryptography
Computer Intelligence Wireless Sensor LTE 4G
(Networks & 20ELD21 Computer 20ECS15 20ECS243 and Network 20ELD323 20ECS241 20ECS31
Communication and its Networks Broadband
allied) Architecture Security
Networks Applications
7 High Frequency Micro Electro VLSI Design
Reconfigurable Medical
(Applied 20EVE242 Nanoelectronics 20EVE254 GaN Electronic 20ELD253 Mechanical 20EVE331 for Signal 20EVE244 20EIE322
Computing Imaging
Electronics) Devices Systems Processing

Long Term
8 Advances in Low Power VLSI
20EVE12 ASIC Design 20EVE241 20EVE251 20EVE14 VLSI Testing 20EVE23 System Verilog 20EVE334 Reliability of
(VLSI related) VLSI Design Design
VLSI Systems
Approved Ph. D Coursework Examination Courses

GROUP 1
Sl.
Course Code Course Name
No.

1 20ECS14 Advanced Communication Systems - 1

2 20ECS12 Advanced Digital Signal Processing

3 20ELD14 Digital Circuits and Logic Design

4 20ECS333 Internet of Things

5 20ELD11 Advanced Engineering Mathematics

6 20ELD21 Advanced Computer Architecture

7 20EVE242 Nanoelectronics

8 20EVE12 ASIC Design


VISVESVARAYA TECHNOLOGICAL UNIVERSITY BELAGAVI
PhD Coursework Courses-2020 (ELECTRONICS & COMMUNICATION)
As per the regulation 2020

Group no. 1 Subject Code 20EVE12 Exam Duration 03 Hours


Exam Marks 100
Subject Title ASIC Design

Module-1
Introduction to ASICs: Full custom, Semi-custom and Programmable ASICs, ASIC Design flow, ASIC
cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry
save, Carry select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell
Compilers.

Module-2
ASIC Library Design: Logical effort: Predicting Delay, Logical area and logical efficiency, Logical
paths, Multi stage cells, Optimum delay and number of stages, library cell design.
Programmable ASIC Logic Cells:
MUX as Boolean function generators, Acted ACT: ACT 1, ACT 2 and ACT 3 Logic Modules, Xilinx LCA:
XC3000 CLB, Altera FLEX and MAX, Programmable ASIC I/O Cells: Xilinx and Altera I/O Block.

Module-3
Low-level design entry: Schematic entry: Hierarchical design, The cell library, Names, Schematic
Icons & Symbols, Nets, Schematic Entry for ASICs, Connections, vectored instances & buses, Edit in
place, attributes, Netlist screener.
ASIC Construction: Physical Design, CAD Tools System partitioning, Estimating ASIC size.
Partitioning: Goals and objectives, Constructive Partitioning, Iterative Partitioning Improvement,
KL, FM and Look Ahead algorithms.

Module-4
Floor planning and placement: Goals and objectives, Measurement of delay in Floor planning,
Floor planning tools, Channel definition, I/O and Power planning and Clock planning.
Placement: Goals and Objectives, Min-cut Placement algorithm, Iterative Placement Improvement,
Time driven placement methods, Physical Design Flow.

Module-5
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between
blocks, Back-annotation. Detailed Routing: Goals and objectives, Measurement of Channel Density,
Left-Edge Algorithm, Area-Routing Algorithms, Multilevel routing, Timing –Driven detailed routing,
Final routing steps, Special Routing, Circuit extraction and DRC.

Textbook
‘Application - Specific Integrated Circuits’, Michael John Sebastian Smith, Addison- Wesley
Professional, 2005
03.09.2020

Reference Books

1. ‘CMOS VLSI Design: A Circuits and Systems Perspective’, Neil H.E. Weste, David Harris and
Ayan Banerjee, Addison Wesley/ Pearson education, 3rd edition, 2011
2. ‘VLSI Design: A Practical Guide for FPGA and ASIC Implementations’, Vikram Arkalgud
Chandrasetty, Springer, ISBN: 978-1-4614-1119-2 , 2011
3. ‘An ASIC Low Power Primer’, Rakesh Chadha, Bhasker J , Springer, ISBN: 978-14614-4270-7
Approved Ph. D Coursework Examination Courses

GROUP 4
Sl.
Course Code Course Name
No.

1 20ECS22 Antenna Theory and Design

2 20ESP324 Speech and Audio Processing

3 20EVE252 SoC Design

4 20ESP332 Pattern Recognition & Machine Learning

5 20EIE252 Industrial Drives

Business Intelligence and its


6 20ELD323
Applications

7 20EVE331 VLSI Design for Signal Processing

8 20EVE14 VLSI Testing


VISVESVARAYA TECHNOLOGICAL UNIVERSITY BELAGAVI
PhD Coursework Courses-2020 (ELECTRONICS & COMMUNICATION)
As per the regulation 2020

Group no. 4 Subject Code 20EVE14 Exam Duration 03 Hours


Exam Marks 100
Subject Title VLSI Testing

Module-1
Faults in digital circuits: Failures and Faults, Modeling of faults, Temporary Faults. (Text 1)
Logic Simulation: Applications, Problems in simulation based design verification, types of
simulation, The unknown logic values, compiled simulation, event-driven simulation, Delay models,
Element evaluation, Hazard detection, Gate-level event-driven Simulation. (Text 2)

Module-2
Test generation for Combinational Logic circuits: Fault Diagnosis of digital circuits, Test
generation techniques for combinational circuits, Detection of multiple faults in Combinational logic
circuits. (Text 1)
Testable Combinational logic circuit design: The Read-Muller expansion technique, Three level
OR-AND-OR design, Automatic synthesis of testable logic. (Text 1)

Module-3
Testable Combinational logic circuit design: Testable design of multilevel combinational circuits,
Synthesis of random pattern testable combinational circuits, Path delay fault testable combinational
logic design, Testable PLA design. (Text 1)
Test generation for Sequential circuits: Testing of sequential circuits as Iterative combinational
circuits, state table verification, Test generation based on Circuit Structure, Functional Fault
models, test Generation based on Functional Fault models. (Text 1)

Module-4
Design of testable sequential circuits: Controllability and observability, Ad-Hoc design rules for
improving testability, design of diagnosable sequential circuits, the scan-path technique for testable
sequential circuit design, Level Sensitive Scan Design (LSSD), Random Access Scan Technique,
Partial scan, testable sequential circuit design using Nonscan Techniques, Cross check, Boundary
Scan. (Text 1)

Module-5
Built-In Self Test: Test pattern generation for BIST, Output response analysis, Circular BIST, BIST
Architectures. (Text 1)
Testable Memory Design: RAM Fault Models, Test algorithms for RAMs, Detection of pattern-
sensitive faults, BIST techniques for RAM chips, Test generation and BIST for embedded RAMs.
(Text1)

Textbooks

1. ‘Digital Circuit Testing and Testability’, Lala Parag K, New York, Academic Press, 1997
2. ‘Digital Systems Testing and Testable Design’, Abramovici M, Breuer M A and Friedman A D,
Wiley, 1994
Reference Books

1. ‘Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits’, Vishwani D
Agarwal, Springer, 2002
2. ‘VLSI Test Principles and Architectures’, Wang, Wu and Wen, Morgan Kaufmann, 2006
Approved Ph. D Coursework Examination Courses

GROUP 6
Sl.
Course Code Course Name
No.

1 20ECS251 Multimedia Over Communication Links

2 20ESP251 Biomedical Signal Processing

3 20ECS331 RF and Microwave Circuit Design

4 20SCS23 Blockchain Technology

5 20ECS254 Simulation, Modelling and Analysis

6 20ECS31 LTE 4G Broadband

7 20EIE322 Medical Imaging

8 20EVE334 Long Term Reliability of VLSI Systems


VISVESVARAYA TECHNOLOGICAL UNIVERSITY BELAGAVI
PhD Coursework Courses-2020 (ELECTRONICS & COMMUNICATION)
As per the regulation 2020

Group no. 6 Subject Code 20EVE334 Exam Duration 03 Hours


Exam Marks 100
Subject Title Long Term Reliability of VLSI Systems

Module-1
Electromigration Reliability
Why Electromigration Reliability?, Why system-level EM Reliability Management? Physics- based
EM Modeling, Electromigration Fundamentals, Stress based EM Modeling and stress diffusion
equations, Modeling for transient EM effects and Initial stress conditions, post voiding stress and
void volume evolution, compact physics based EM model for a single wire, other relevant EM
models and analysis methods. (Text Book:1 – 1.1, 1.2, 2.1 up to 2.6, 2.9).

Module-2
Fast EM Stress Evolution Analysis
Introduction, The LTI ordinary differential equations for EM stress evolution, The presented Krylov
fast EM stress analysis, Numerical results and discussions (Text. Book:1 – 3.1 up to 3.4).

Module-3
EM Assessment for Power Grid Networks
New power grid reliability analysis method, cross-layout temperature and thermal stress
characterization, impact of across-layout temperature and thermal stress on EM. (Text.Book:1 – 7.1,
7.2, 7.4, 7.5).

Module-4
Transistor Aging Effects and Reliability:
Introduction, Transistor reliability in advanced technology nodes, Transistor Aging, BTI- Bias
Temperature Instability, HCI – Hot Carrier Injection, Coupling models for BTI and HCI degradations,
RTN – Random Telegraph Noise, TDDB – Time Dependent Dielectric Breakdown. (Text Book: 1 –
13.1, 13.2).

Module-5
Aging Effects in Sequential Elements:
Introduction, Background: flip flop timing analysis, process variation model, voltage droop model,
Robustness analysis, reliability-aware flip-flop design (Text Book: 1 – 16.1 up to 16.4).

Textbook
‘Long-Term Reliability of Nanometer VLSI Systems’, Sheldon X. D. Tan, Mehdi Baradaran
Tahoori, Taeyoung Kim, Saman Kiamehr, Zeyu Sun, Shengcheng Wang, Springer International
Publishing, 1st Edition, 2019, ISBN: 978-3-030-26171-9

Reference Books

1. ‘Reliability Wearout Mechanisms in Advanced CMOS Technologies’, Alvin Wayne Strong,


Rolf-Peter Vollertsen, Timothy D. Sullivan, Ernest Y. Wu, Giuseppe La Rosa, Jordi Sune,
Wiley, Copyright © the Institute of Electrical and Electronics Engineers, Inc., 2009 Print
ISBN: 9780471731726
2. ‘Hot-carrier Reliability of MOS VLSI Circuits’, Yusuf Leblebici, S M Kang, Springer Science &
Business Media, 1st Edition, 1993
3. ‘Fundamentals of Electromigration-Aware Integrated Circuit Design’, Matthias Thiele, Jens
Lienig, Springer International Publishing, 2018

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