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VHDL Codes

The document contains VHDL code for several common digital logic components and circuits including: 1. A 4-bit adder/subtractor using a full adder component 2. A BCD adder using two 4-bit adder components 3. D latches with different enable types 4. 8-bit counters with various load and clear functions 5. Gray code and binary counters 6. A signal pulse generator The code provides implementations for basic logic functions like addition and storage (latches), as well as more complex sequential circuits like counters using VHDL components, processes, and state machines.

Uploaded by

Saneesh Karayil
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© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
210 views

VHDL Codes

The document contains VHDL code for several common digital logic components and circuits including: 1. A 4-bit adder/subtractor using a full adder component 2. A BCD adder using two 4-bit adder components 3. D latches with different enable types 4. 8-bit counters with various load and clear functions 5. Gray code and binary counters 6. A signal pulse generator The code provides implementations for basic logic functions like addition and storage (latches), as well as more complex sequential circuits like counters using VHDL components, processes, and state machines.

Uploaded by

Saneesh Karayil
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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4-bit adder / subtractor

addsub4g.vhd ENTITY addsub4g IS PORT ( sub : IN BIT; a, b : IN BIT_VECTOR (3 downto 0); c4 : OUT BIT; sum : OUT BIT_VECTOR (3 downto 0)); END addsub4g; ARCHITECTURE adder OF addsub4g IS Component declaration COMPONENT full_add PORT ( a, b, c_in : IN BIT; c_out, sum : OUT BIT); END COMPONENT; Define a signal for internal carry bits SIGNAL c: BIT_VECTOR (4 downto 0); SIGNAL b_comp: BIT_VECTOR (3 downto 0); BEGIN add/subtract select to carry input (sub_1 for subtract) c(0) <= sub; adders: FOR i IN 1 to 4 GENERATE invert b for subtract (b(i) xor 1), do not invert for add (b(i) xor 0) b_comp(i) <= b(i) xor sub; adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i),sum(i)); END GENERATE; c4 <= c(4); END adder;

BCD adder, using two parallel adder components


bcd_add.vhd BCD adder, using 2 instances of the component add4par ENTITY bcd_add IS PORT ( c0 : IN BIT; a, b : IN BIT_VECTOR (4 downto 1); c4 : OUT BIT; sum : OUT BIT_VECTOR (4 downto 1)); END bcd_add; ARCHITECTURE adder OF bcd add IS Component declaration COMPONENT add4par PORT ( c0 : IN BIT; a, b : IN BIT_VECTOR (4 downto 1); c4 : OUT BIT; sum : OUT BIT_VECTOR (4 downto 1)); END COMPONENT; SIGNAL c4_bin : BIT; SIGNAL sum_bin : BIT_VECTOR (4 downto 1); SIGNAL a_bcd : BIT_VECTOR (4 downto 1); SIGNAL b_bcd : BIT_VECTOR (4 downto 1); SIGNAL c0_bcd: BIT; BEGIN Instantiate 4-bit adder (binary sum) add_bin: add4par PORT MAP ( c0 => c0, a =>a, b => b, c4 => c4_bin, sum => sum_bin); Instantiate 4-bit adder (binary-BCD converter) converter: add4par PORT MAP ( c0 => c0_bcd, a => a_bcd, b => b_bcd, sum => sum); Connect components c0_bcd <= 0; b_bcd <= sum_bin; a_bcd(4) <= 0; a_bcd(3) <= c4 bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); a_bcd(2) <= c4 bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); a_bcd(1) <= 0; c4 <= c4_bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); END adder; 2

D_Latch
d_lch.vhd D latch with active-HIGH level-sensitive enable ENTITY d_lch IS PORT( d, ena : IN BIT; q : OUT BIT); END d_lch; ARCHITECTURE a OF d_lch IS BEGIN PROCESS (d, ena) BEGIN IF (ena = 1) THEN q <= d; END IF; END PROCESS; END a;

Lct_Prime
lch_prim.vhd D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY lch_prim IS PORT( d_in, enable : IN STD_LOGIC; q_out : OUT STD_LOGIC); END lch_prim; ARCHITECTURE a OF lch_prim IS BEGIN Instantiate a latch from a MAX_PLUS II primitive latch_primitive: latch PORT MAP (d => d_in, Ena => enable, q => q_out); END a;

Simple 8-bit counter


ct_simp.vhd ENTITY ct_simp IS PORT( clk : IN BIT; clear : IN BIT; q : OUT INTEGER RANGE 0 TO 255); END ct_simp; ARCHITECTURE a OF ct_simp IS BEGIN PROCESS (clk, clear) VARIABLE count : INTEGER RANGE 0 TO 255; BEGIN If (clear = 0) THEN count := 0; ELSE IF (clkEVENT AND clk = 1) THEN count := count + 1; END IF; END IF; q <= count; END PROCESS; END a;

Lpm_Simp
lpm_simp.vhd Eight-bit binary counter based on a component from the Library of Parameterized Modules (LPM) Counter has an active-LOW asynchronous clear. LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY lpm_simp IS PORT( clk, clear : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 downto 0)); END lpm_simp; ARCHITECTURE count OF lpm_simp IS SIGNAL clrn : STD_LOGIC; BEGIN count8: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP ( clock => clk, aclr => clrn, q => q(7 downto 0)); clrn <= not clear; END count; 4

The following lists the VHDL code for an 8-bit bidirectional counter with count enable, terminal count decoding, and asynchronous load and clear:
pre_ct8a.vhd ENTITY pre_ct8a IS PORT ( clk, count_ena : IN BIT; clear, load, direction : IN BIT; p : IN INTEGER RANGE 0 TO 255; max_min : OUT BIT; qd : OUT INTEGER RANGE 0 TO 255); END pre_ct8a; ARCHITECTURE a OF pre_ct8a IS BEGIN PROCESS (clk, clear, load) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clear = 0) THEN Asynchronous clear cnt := 0; ELSIF (load = 1 and clear = 1) THEN Asynchronous load cnt := p; ELSE IF (clkEVENT AND clk = 1) THEN IF (count_ena = 1 and direction = 0) THEN cnt := cnt - 1; ELSIF (count_ena = 1 and direction = 1) THEN cnt := cnt + 1; END IF; END IF; END IF; qd <= cnt; Terminal count decoder IF (cnt = 0 and direction = 0) THEN max_min <= 1; ELSIF (cnt = 255 and direction = 1) THEN max_min <= 1; ELSE max_min <= 0; END IF; END PROCESS; END a;

The code for the same 8-bit counter, but with synchronous clear and load, is shown next.
pre_ct8s.vhd ENTITY pre_ct8s IS PORT ( clk, count_ena : IN BIT; clear, load, direction : IN BIT; p : IN INTEGER RANGE 0 TO 255; max_min : OUT BIT; qd : OUT INTEGER RANGE 0 TO 255); END pre_ct8s; ARCHITECTURE a OF pre_ct8s IS BEGIN PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF (clear = 0) THEN Synchronous clear cnt := 0; ELSIF (load = 1) THEN Synchronous load cnt := p; ELSIF (count_ena = 1 and direction = 0) THEN cnt := cnt - 1; ELSIF (count_ena _ 1 and direction = 1) THEN cnt := cnt + 1; END IF; END IF; qd <= cnt; Terminal count decoder IF (cnt = 0 and direction = 0) THEN max_min <= 1; ELSIF (cnt = 255 and direction = 1) THEN max_min <= 1; ELSE max_min <= 0; END IF; END PROCESS; END a;

3-bit Gray code counter


gray_ct1.vhd 3-bit Gray code counter (state machine with decoded outputs) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY gray_ct1 IS PORT( clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 downto 0)); END gray_ct1; ARCHITECTURE a OF gray_ct1 IS TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6, s7); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN CASE state IS WHEN s0 => state <= s1; WHEN s1 => state <= s2; WHEN s2 => state <= s3; WHEN s3 => state <= s4; WHEN s4 => state <= s5; WHEN s5 => state <= s6; WHEN s6=> state <= s7; WHEN s7 => state <= s0; END CASE; END IF; END PROCESS; WITH state SELECT q <= 000 WHEN s0, 001 WHEN s1, 011 WHEN s2, 010 WHEN s3, 110 WHEN s4, 111 WHEN s5, 101 WHEN s6, 100 WHEN s7; END a; 7

(Outputs defined within states)


-- gray_ct2.vhd -- 3-bit Gray code counter -- (outputs defined within states) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY gray_ct2 IS PORT( clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 downto 0)); END gray_ct2; ARCHITECTURE a OF gray_ct2 IS TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6, s7); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN CASE state IS WHEN s0 => state <= s1; q <= 001; WHEN s1 => state <= s2; q <= 011; WHEN s2 => state <= s3; q <= 010; WHEN s3 => state <= s4; q <= 110; WHEN s4 => state <= s5; q <= 111; WHEN s5 => state <= s6; q <= 101; WHEN s6 => state <= s7; q <= 100; WHEN s7 => state <= s0; q <= 000; END CASE; END IF; END PROCESS; END a;

Signal Pulse
-- sngl_pls.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sngl_pls IS PORT( clk, sync : IN STD_LOGIC; pulse : OUT STD_LOGIC); END sngl_pls; ARCHITECTURE pulser OF sngl_pls IS TYPE PULSE_STATE IS (seek, find); SIGNAL status: PULSE_STATE; BEGIN PROCESS (clk, sync) BEGIN IF (clkEVENT and clk = 1) THEN CASE status IS WHEN seek => IF (sync = 1) THEN status <= seek; pulse <= 0; ELSE status <= find; pulse <= 1; END IF; WHEN find => IF (sync = 1) THEN status <= seek; pulse <= 0; ELSE status <= find; pulse <= 0; END IF; END CASE; END IF; END PROCESS; END pulser;

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