Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
81 views

ECE111 Advanced Digital Design Project Winter 2009: Introduction To Verilog Hardware Description Language

This document provides an introduction to the Verilog hardware description language. It describes what Verilog is, the digital design flow using HDLs, writing synthesizable Verilog code, basic Verilog constructs, data types, sequential logic, testbenches, simulation, and some tips for writing Verilog. Key topics covered include hardware modeling using Verilog, logic synthesis to translate RTL to gate-level netlists, and simulation for functional verification.

Uploaded by

henisgood
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
81 views

ECE111 Advanced Digital Design Project Winter 2009: Introduction To Verilog Hardware Description Language

This document provides an introduction to the Verilog hardware description language. It describes what Verilog is, the digital design flow using HDLs, writing synthesizable Verilog code, basic Verilog constructs, data types, sequential logic, testbenches, simulation, and some tips for writing Verilog. Key topics covered include hardware modeling using Verilog, logic synthesis to translate RTL to gate-level netlists, and simulation for functional verification.

Uploaded by

henisgood
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 16

ECE111 Advanced Digital Design Project Winter 2009

Introduction to Verilog Hardware Description Language

What Is It?
Hardware description language
a (sort of programming) language allows designer to describe behavior of a design in text rather than schematic

First created by Phil Moore in 1983 at Gateway Design Automation (acquired by Cadence in 1989) Advantages of Verilog (over VHDL):
Syntax based on C (VHDL based on ADA) Easier to learn & use, less stringent, loosely typed More compact code Switch-level modeling All signals are initialized to unknow that mimics the real hardware well.

Digital Design Flow


HDL
RTL coding Verification

Logic synthesis
Translate synthesizable RTL code to a netlist of predefined circuit elements that is
functionally equivalent to RTL Meeting design constraints (timing, area, power)

Synthesizable code: a subset of verilog language that can be understood by synthesis tools Standard cell library: collection of pre-defined circuit elements (mostly logic gates), technology& process-specific

Writing Synthesizable Code


Can be mapped to a piece of hardware (logic gates, wires, etc.) by synthesis tools Only a subset of the standard verilog code is synthesizable
Example of non-synthesizable statements: initial, wait, forever, #, casex

Example 1: 1-bit Full Adder


// Verilog one-bit adder slice module full_adder (a_one, a_two, c_in, s, c_out); // module name // module ports

input a_one, a_two; // by default a signal's number of bits is 1 input c_in; // declaration of module ports output s; output c_out; wire s; // declare wires

assign s = a_one ^ a_two ^ c_in; // continuous signal assignment wire c_out = (a_one & a_two) | (a_one & c_in) | (a_two & c_in); endmodule

Structural description

Example 2: 4-bit Adder


// 4-bit adder using hierarchical logic. A 1-bit full adder is instantiated four times. module h4ba (addend_one,addend_two,carry_in,sum,carry_out); input [3:0] addend_one; // four bit signal with msb addend_one(3) input [3:0] addend_two; input carry_in; output [3:0] sum, carry_out; // Declare wires to connect the four instantiations of the full adder together to obtain the four-bit adder. wire carry_out_0, carry_out_1, carry_out_2; // 1-bit wires // 4 instantiations of the full_adder module. Each instantiation is given a unique name (instance name) full_adder fa0 ( .a_one(addend_one[0]), .a_two(addend_two[0]), .c_in(carry_in), .s(sum[0]), .c_out(carry_out_0) ); full_adder fa1 ( .a_one(addend_one[1]), .a_two(addend_two[1]), .c_in(carry_out_0), .s(sum[1]), .c_out(carry_out_1)); full_adder fa2 ( .a_one(addend_one[2]), .a_two(addend_two[2]), .c_in(carry_out_1), .s(sum[2]), .c_out(carry_out_2)); full_adder fa3 ( .a_one(addend_one[3]), .a_two(addend_two[3]), .c_in(carry_out_2), .s(sum[3]), .c_out(carry_out) ); endmodule

Structural description

Example 3: More Adder


1: module adder_variation1 (A, B, C, D, Sum1, Sum2); 2: 3: input [31:0] A, B; 4: input [31:0] C, D; 5: 6: output [31:0] Sum1; Behavioral description 7: output [31:0] Sum2; Actual implementation will be 8: 9: reg [31:0] Sum2; decided by the synthesis tool 10: 11: assign Sum1 = A + B; 12: 13: always @ (C or D) 14: begin 15: Sum2 = C + D; 16: end 17: 18: endmodule

Basic Stuff
Comments:
single-line: // multi-line: /**/

Logic values: 0, 1, x, z Integer numbers


1b1, 1bx, d4, 32hDEADBEEF, 8hzz, 3O3

Reserved words Identifiers


Case sensitive! Must begin with alphabetic or underscore characters a-z A-Z _ May contain the characters a-z A-Z 0-9 _ and $ May use any character by escaping with a backslash ( \ ) at the beginning of the identifier, and terminating with a white space.

Flow controls
if/else, case, wait, repeat, for, while

Assignments
Continuous:
assign a = b + c;

Procedural: must appear in always or initial blocks


blocking (=): a = b;
Expression is evaluated and assigned when the statement is encountered. In a begin--end statement group, execution of the next statement is blocked until the assignment is complete.

non-blocking (<=): a <= b;


Expression is evaluated when the statement is encountered, and assignment is postponed until the end of the time-step. In a begin--end statement group, execution of the next statement is not blocked; and may be evaluated before the assignment is complete.

Can not use both on the same target Combinational vs. sequential Sensitivity list of an always block
an event timing control that controls when all statements in the procedural block will start to be evaluated.

Data Types
Register:
reg, integer, time, real, realtime. A register data type must be used when the signal is on the left-hand side of a procedural assignment does not necessarily mean a register

Net:

wire, tri, wor, wand, supply0, supply1,


A net data type must be used when:
A signal is driven by the output of some device. A signal is also declared as an input port or inout port. A signal is on the left-hand side of a continuous assignment

Sequential Logics
Described using an always block: wire clk, rst_n; reg [3:0] q; wire [3:0] d; // A DFF with negative edge triggered asynchronous reset always @ (posedge clk or negedge rst_n) begin if (~rst_n) q<= 3b000; // The first if will be translated to a reset pin. else d[3:0] q[3:0] begin q <= d; DFF // more code here clk end end rst_n Tip: Use blocking assignment (=) in non-sequential always block and non-blocking assignment (<=) in sequential always block

Think hardware!
Concurrency always @ (posedge clk or negedge rst_n) if (~rst_n) begin a <= 1b1; b <= 1b0; end else begin b <= a; c <= b; end

What will be the value in DFF b and c?

Testbench

Verification

Behavioral verilog code written to verify design Will not be part of your chip Does not to be synthesizable

Tasks to be performed in a testbench


Global clocks and resets Initialization File I/O Flow control Stimulus application Response collection Checking results Debugging capability

Simulation in ModelSim
Running ModelSim
Command lines Using do files

Debugging in ModelSim

A Few Tips
Think of hardware when writing RTL Understand concurrency Write proper combinational procedural assignments to avoid latches Sensitivity list: all signals (wires, regs) on the RHS of =; Fully describe the behaviors of all signals: if/else: always have an else; case: always use default clause; Properly use sequential process always reset a FF: async reset vs. sync reset signals can not appear in multiple sequential process Assignments Use blocking assignments (=) in combinational procedural assignments Use non-blocking assignments (<=) in sequential procedural assignments Only use wire/reg data type wire: signals assigned using continuous assignment; port connections; reg: signals assigned using procedural assignments (either comb. or seq.) Be careful when using for loops (actually, avoid using for loops) One module in one file, module name same as file name Use lower-case for signals, upper-case ONLY for parameters

Resources
Books
The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby
Kluwer Academic, June 1996, ISBN: 0792397231

Verilog HDL : A Guide to Digital Design and Synthesis by Samir Palnitkar


Prentice Hall, March 1996, ISBN: 0134516753

Links
On-line manual: http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/index.html Quick reference guide: http://www.sutherland-hdl.com/online_ref_guide/vlog_ref_top.html An introductory article: http://www.see.ed.ac.uk/~gerard/VLSI/verilog.ps Google it!

You might also like