97 () Chapter-7 Differential Amplifier and Multistage Amplifier

Section Title 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Exercises(E7. ) 5,6 9 12 15 2 3 Examples Problems (P7.) 1 2, 8 11 , 14 , 15 , 17 37 , 38 , 39 , 41 50 , 57 64 , 74 88 , 89 98

MOS Differential Pair 3 Small-Signal of MOS-D.A. BJT Differential Pair NonIdeal Characteristics DA with Active Load Frequency Response Multistage Amplifier

Example.1 The differential amplifier in Fig. 7.24 uses transistors with =100 .Evaluate the following: (a)The input differential resistance R id . (b)The over differential voltage gain V0 / Vsig (neglect the effect of r0 ) (c)The worst-case common-mode gain if the two collector resistances are accurate to within 1% . (d)The CMRR,in dB. (e)The input common-mode resistance (assuming that the Early voltage V A =100V).

Example.2 Consider an active-loaded MOS differential amplifier of the type shown in Fig.7.28(a) m / 0.36 m , C gs = 20 fF , C gd = 5 fF , and Assume that for all transistors, W/L=7.2 2 ' C db = 5 fF . Also, let n C ox = 387 A / V , p C ox = 86 A / V 2 , V An = 5V / m , ' V Ap = 6V / m .The bias current I=0.2mA , and the bias current source has an output Resistance R ss = 25k and an output capacitance C ss = 0.2 pF . In addition to the capacitances introduced by the transistors at the output node. There is a capacitance C x of 25fF. It is required to determine the low-frequency values of Ad , Acm and CMRR. It is also required to find the poles and zero of Ad and the dominant pole of CMRR.

Example.3 Consider the circuit in Fig. 7.40 with the follow device geometries(in m )

2 2 Let I REF = 90 A, Vtn = 0.7V , Vtp = 0.8V , n C ox = 160 A / V , p C ox = 40 A / V , V A (for all devices)=10V, V DD = V ss = 2.5V . For all devices evaluate I D , Vov , VGS , g m ,and ro . Also find A1 , A2 ,the dc open-loop voltage gain , the input common-mode range, and the output voltage range. Neglect the effect of V A on bias current.

Exercise.3 A MOS differential pair is operated at a bias current I of 0.4mA. If n C ox = 0.2mA / V 2 ,fine the required values of W/L and the resulting g m if the MOSFET are operated at VOV =0.2,0.3,and0.4V. For each value , give the maximum 2 Vid for which the term involving Vid in Eqs.(7.23)and (7.24), namely 2 ((Vid / 2) / VOV ) , is limited to 0.1 .

Exercise.5 A MOS differential pair is operated at a bias current of 0.8mA employs transistors with W/L=100 and n C ox = 0.2mA / V 2 ,using R D =5k , Rss =25k (a) Find the differential gain , the common-mode gain, and common-mode rejection ratio(in dB)if the output os taken single-endedly and the circuit is perfectly matched. (b) Repeat(a) when the output is taken differentially. (c) Repeat(a) when the output is taken differentially but the drain resistances have a 1% mismatch.

Exercises.6 For the MOS amplifier specified in Exercise7.5 with the output taken differentially Compute CMRR that results from a 1% mismatch in g m .

Exercises.9 For the circuit in Fig. 7.16 , let I=1mA, VCC =15V, RC =10k ,with =1,and let the Input voltages be: V B1 =5+0.005sin2 1000t,and V B 2 =5-0.005sin2 1000t,volts. (a) If the BJTs are specified to have V BE of 0.7V at a collector current of 1 mA,find the voltage at the emitters(Hint:Observe the symmetry of the circuit) (b) Find g m for each of the two transistors. (c) Find ic for each of the two transistors. (d) Find Vc for rach of the two transistors . (e) Find the voltage between the two collectors. (f) Fine the gain experienced by the 1000-Hz signal.

Exercises.12 An active-loaded MOS differential amplifier of the type shown in Fig.7.28(a)is specified as follows: 2 (W/L) n =100,(W/L) p =200, n C ox = 2 p C ox = 0.2mA / V , V An = V Ap =20V, I=0.8mA, RSS =25k .Calculate G m , Ro , Ad , Acm , and CMRR.

Exercises.15 A MOSFET differential amplifier such as that in Fig. 7.36(a)is biased with a current

' = 0.2mA / V 2 , V A = 20V , C gs = 50 fF , I=0.8mA. The transistors have W/L =100, k n C gd =10 fF ,and C db = 10 fF .The drain resistors are 5k each. Also , there is a 100-fF capacitive load between each drain and ground. (a)Find VOV and g m for each transistor. (b)Find the differential gain A d . (c)If the input signal source has a small resistance R sig and thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency fH . (d) If,in a differential situation ,the amplifier is fed symmetrically with a signal source of 20k resistance(i.e. 10k in series with each gate terminal ), use the opencircuit time-constants method to estimate f H .

Problems.2 For the PMOS differential amplifier shown in Fig.P7.2 let Vtp = -0.8V and ' kp W / L = 3.5mA / V 2 .Neglect channel-length modulation. (a) For VG1 =VG 2 = 0V ,find VOV and VGS for each of Q1 and Q2 .Also find V S , V D1 ,

and V D 2 . (b) If the current source requires a minimum voltage of 0.5V, find the input commonmode range.

Problems.8 A . The devices have An NMOS differential amplifier utilizes a bias current of 200 Vt =0.8V , W=100 m , and L=1.6 m , in a technology ofr which n C ox = 90A / V 2 . Find VGS , g m , and the value of Vid for full-current switching. To what value should the bias current be changed in order to double the value of Vid for fullcurrent switching? Problems.11 An NMOS differential amplifier is operated at a bias current I of 0.5mA and has a W/L ratio of 50, n C ox = 250A / V 2 , V A =10V , and R D =4k . Find VOV , g m , ro , Ad .

Problems.14 A design error has resulted in a gross mismatch in the circuit of Fig.P7.14. Specifically, Q2 has twice the W/L ratio of Q1 . If Vid is a small sine-wave signal , find: (a) I D1 and I D 2 (b) VOV for each of Q1 and Q 2 . (c)The differential gain Ad in terms of R D , I , and VOV .

Problems.15 An NMOS differential pair is biased by a current source I=0.2mA having an output resistance R ss =100k . The amplifier has drain resistances R D =10k ,using ' W / L = 3mA / V 2 , and ro that is large. transistors with k n (a) If the output is taken single-endedly, find Ad , Acm , and CMRR. (b) If the output is taken differentially and there is a 1% mismatch between the drain resistances, find Ad , Acm , and CMRR..

Problems.17 The differential amplifier in Fig.P7.17 utilizes a resistor R ss to establish a 1-mA dc bias current . Note that this amplifier uses a single 5-V supply and thus needs a dc ' W / L = 2.5mA / V 2 common-mode voltage VCM . Transistors Q1 and Q 2 .have k n , Vt = 0.7V and = 0 . (a) Find the required value of VCM . (b) Find the value of R D that results in a differential gain Ad of 8V/V. (c) Determine the dc voltage at the drains. (d) Determine the common-mode gain V D1 / VCM . (e) Use the common-mode gain found in (d) to determine the change in VCM that

result in Q1 and Q 2 entering the triode region.

Problems.37 Find the voltage gain and the input resistance of the amplifier shown Fig. P7.37 Assuming =100

Problems.38 Find the voltage gain and the input resistance of the amplifier shown Fig. P7.38 Assuming that =100

Problems.39 Derive an expression for the small-signal voltage gain Vo / Vi of the circuit shown in Fig. P7.39 in two different ways: (a) as a differertial amplifier (b) as a cascade of a common-collector stage Q1 and a common-base stage Q 2 Assume that the BJT are matched and have a current gain .Verify that both approaches lead to the same result.

Problem.41 For the differerntial amplifier shown in Fig. P7.41 , identify and sketch the differential half-circuit.Find the differential gain , the differential input resistance, the commonmode , and the common-mode input resistance . For these transistors, =100 and V A =100V

Problem.50 A uses transistors for An Nmos differential pair operating at a bias current I of 100 ' 2 whitch k n = 100 A / V and W/L=20, with Vt =0.8V. Find the three components of input offset voltage under the conditions that R D / R D = 5% , (W / L) /(W / L) = 5% Vt =5mV. In the worst case, what might the total offset be? For the usual case ,and of the three effects being independent , what is the offset likely to be ? Problem.57 One approach to offset correction involves the adjustment of the values of RC1 and RC 2 so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accomplished by utilizing a potentionmeter in the collector circuit, as shown in Fig. P7.57. We wish to find the potentionmeter setting, represented by the fraction x of its value connected in series with RC1 , that is required for nulling the output offset voltage that results from: (a) RC1 being 5% higher than nominal and RC 2 5% lower than nominal (b) Q1 having an area 10% larger than that of Q2

Problem.64 Consider the active-loaded MOS differential amplifier of Fig. 7.28(a) in two cases: (a) Current-source I is implemented with a simple current mirror. (b) Current-source I is implemente with the modified Wilson current mirror shown in Fig. P7.64 Recalling that for the simple mirror R SS = ro | Q and for the Wilson mirror
S

R SS g m 7 ro 7 ro 5 ,and assuming that all transistors have the same V A and k 'W / L ,

VA Show that for case (a) CMRR=2 V OV VA CMRR= 2 V OV

And for case(b)

Where VOV is the overdrive voltage that corresponds to a drain current of I/2 . For k 'W / L =10 mA / V 2 , I = 1 mA , and V A =10V, find CMRR for both cases.

Problem.74 Figure P7.74 shows a differential cascode amplifier with an active load formed by a Wilson current mirror , Utlizing the expressions derived in Chapter 6 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror , and assuming all transistors to be identical, show that the differential voltage gain Ad is given by
Ad =

1 g m rO 3

Evaluate Ad for the case I=0.4mA , =100, and V A =120V.

Problem.88 A and VOV =0.25V , Consider the circuit of Fig. P7.88 for the case: I = 200 R sig = 200k, R D = 50k , C gs = C gd =1 pF . Find the dc gain, the hige-frequency poles, and an estimate of f H .

Problem.89 For the circuit in Fig. P7.89 , let the bias be such that each transistor is operating at A collector current. Let the BJTs have = 200 , f T =600MHz , and C 100- =0.2pF , and neglect rO and rx . Also , Rsig = RC = 50k. Find the low-frequency gain, the input defferential resistance , the high-frequency poles,and an estimate of fH .

Problem.98

In the multistage amplifier of Fig. 7.43,emitter resistors are to be introduced 100 in the emitter lead of each of the first-stage reansistors and 25 for each of the second-stage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example7.4

Chapter-8 Feedback
Section Title 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Feedback Structure Properties of Feedback Basic Feedback Topologies SR-SH Feedback Amp SR-SR Feedback Amp SH-SH Feedback Amp Determine the loop Gain Stability Porblem Effect on Pole Location Effect on Bode Plot Frequnecy compensation 8.14 8.6 8.7 8.8 8.5 8.5 8.1 8.2 8.3 8.4 Exercises(E8. ) 8.1 Examples Problems (P8.) 4, 6 10 , 15 24 , 26 32 , 34 37 , 39 42 , 48 , 52 54 , 55 66 66 , 68 73 , 75 78 , 81

Example 8.1 Figure 8.12(a)shows an op amp connected in the noninverting configuration. The op amp has an open-loop gain ,a differential input resistance Rid ,and an output resistance ro .Recall that in our analysis of op-amp circuits in chapter 2 , we neglected the effects of Rid (assumed it to be infinite) and of ro (assumed it to be zero). Here we wish to use the feedback method to analyze the circuit taking both Rid and ro into account . Find expressions for A, ,the closed-loop gain Vo / V s ,the input resistance R in (see Fig 8.12a),and the output resistance Rout .Also find numerical values,given = 10 4 , Rid =100k , ro =1k , R L =2k , R1 =1k ,and R s =100k .

Example 8.2

Because negative feedback extends the amplifier bandwidth ,it is commonly used in the design of broadband amplifiers. One such amplifier is the MC1553. Part of the circuit of the MC1533 is shown in Fig.8.17(a). The circuit shown(called a feedback triple) is composed of three gain stages with series-series feedback provided by the network composed of R E1 , R F ,and R E 2 . Assume that the bias circuit ,which is not shown , causes I c1 =0.6mA, I c 2 =1mA,and I c 3 =4mA, Using these values and assuming that h fe =100 and ro = , find the open-loop gain A,the feedback factor ,the closed-loop gain A f I o / Vs , the voltage gain Vo / V s , the input resistance R in = Rif ,and the output resistance Rof (between nodes Y and Y ' ,as indicated ). Now, if ro of Q3 is 25k , estimate an approximate value of the output resistance Rout .

Example 8.3 We want to analysis the circuit of Fig.8.21(a) to determine the small-signal voltage gain Vo / Vs ,the input resistance R in ,and the output resistance Rout = Rof . The transistor has =100 . Example 8.4 Figure 8.25 shows a feedback circuit of the shunt-series type. Find I out / I in , R in and Rout . Assume the transistor ot have =100 and V A =75V.

Exercises8.1 The noninverting op-amp configuration shown in Fig. E8.1 provides a direct implementation of the feedback loop of Fig.8.1. (a)Assume that the op amp has infinite input resistance and zero output resistance. Find an expression for the feedback factor . (b)if the open-loop valtage gain A= 10 4 ,find R2 / R1 to obtain a closed-loop voltage gain A f of 10. (c)what is the amount of feedback in decibels? (d)if V s =1v, find Vo , V f and Vi . (e) If A decrease by 20% , what is the corresponding decrease in A f ?

Exercises8.5 The circuit shown in Fig. E8.5 consists of a differential stage followed by an emitter

follower,with series-shunt feedback supplied by the resistance R1 and R2 .Assume that the dc component of Vs is zero , and that of the BJTs is very high , find the dc operating current of each of the three transistors and show that the dc voltage at the output is approximately zero. Then find the values of A, , A f I o / Vs , R in and
Rout

Assume that the transistors have =100.

Problem 8.4 The noninveritng buffer op-amp configuration shown in Fig. P8.4 provieds a direct implinentation of the feedback loop of Fig. 8.1 . Assuming that the op amp has infinite input resistance and zero output resistance,what is ? If A=100, what is the closedloop voltage gain? What is the amount of feedback (in dB)? For Vs =1V, find Vo and Vi . If A decreases by 10%, what is the corresponding decrease in A f .

Problem 8.6 Find the open-loop gain,the loop gain, and the amount of feedback of a voltage amplifier for which A f and 1/ differ by (a)1% (b)5% (c) 10% (d) 50%.

Problem D8.10 It is required to design an amplifier with a gain of 100 that is accurate to within 1% . You have available amplifier stages with a gain of 1000 that is accurate to within 30% .Provide a design that uses a number of these gain in cascade , with each stage employing negative feedback of an appropriate amount . Obviously, your design should use the lowest possible number of stages while meeting specification.

Problem D8.15 It is required to design a dc amplifier with a low-frequency gain of 1000 and a 3-dB frequency of 0.5 MHz. You have available gain stages with a gain of 1000 but with a dominant high-frequnecy pole at 10 kHz. Provide a design that employs a number of such stages in cascade, each with negative feedback of an appropriate amount.Use identical stages. Problem 8.24

A series-series feedback circuit representable by Fig.8.4(c) and using an ideal transconductance amplifier operates with Vs =100mV, V f =95mV,and I o =10mA. What are the corresponding values of A and ? Include the correct units for each.

Problem 8.26 For each of the op-amp circuits shown in Fig.P8.26, identify the feedback topology and indicate the output variable being sampled and the feedback signal. In each case,assuming the op amp to be ideal,find am expression for ,and hence find A f . Problem 8.32 In the series-shunt amplifier shown in Fig. P8.32, the transistors operate at V BE 0.7V with hFE of 100 and an Early voltage that is very large. (a) Derive expressions for A, , Ri and Ro (b) For I B1 =0.1mA, I B 2 =1mA, R1 =1k , R2 =10k , Rs =100 ,and R L =1k ,find the dc bias voltages at the input and at the output ,and find A f = Vo / Vs , R in and Rout .

Problem 8.34 For the circuit in Fig. P8.34, Vt =1V, k 'W / L =1mA/ V 2 , h fe =100,and the Early voltage magnitude for all devices(including those that implement the current sources)is 100V. The signal source V s has a zero dc component . Find the dc voltage at the output and at the base Q3 . Find the values of A, , A f , R in , Rout .

Problem 8.37 A series-series feedback amplifier employs a transconductance amplifier having Gm =100mA/V,input resistance of 10k ,and output resistance of 100k .The feedback network has =0.1V/mA , an input resistance (with port 1 open-circuited) of 100k ,and an input resistance (with port 2 open-circuited) of 10k . The amplifier operates with a signal source having a resistance of 10k , Find A f , R in , Rout .

Problem 8.39 Figure P8.39 shows a circuit for a voltage-to-current converter employing seriesseries feedback via resistor R F . The MOSFETs have the dimensions shown and

n C ox =20 A/ V 2 , Vt =1V,and V A =100V. What is the value of I o / Vs .Also ,

if the output voltage is taken at the source of Q5 ,what closed-loop voltage gain is realized?

Problem 8.42 The shunt-shunt feedback amplifier in Fig. P8.42 has I=1mA and VGS =0.8V.The MOSFETs has Vt =0.6V and V A =30V . For Rs =10k , R1 =1M ,and R2 =4.7M ,find the voltage gain Vo / Vs ,the input resistance R in , and the output resistance
Rout

Problem 8.48 For the circuit of Fig. P8.48, use the feedback method to find the volage gain Vo / V s ,the input resistance R in ,and the output resistance Rout . The op amp has open-loop gain =10 4 V / V , Rid = 100k ,and ro =1k .

Problem 8.52 The feedback amplifier of Fig. P8.52 consists of a common-gate amplifier formed by Q1 and R D , and a feedback circuit formed by the capacitive divider (c1,c2) and the common-source transistor Q f . Note that the bias circuit for Q f is not shown . It is required to derive expressions for A f = Vo / I s , R in and Rout .Assume that C1 andC 2 are sufficiently small that their loading effect on the basic amplifier can be neglected . Also neglect ro and the body effect. Find the values of A f , R in , Rout for the case in which gm1 =5mA/V, R D =10k , C1 =0.9pF, C 2 =0.1pF,and gm f =1mA/V