FM Transceiver Project (144-148 MHZ)

QRP 2m FM Transceiver Project
IZ0ROO, Paolo Pinto
October 2011
QRP 2m FM Transceiver PP-002m
IZ0ROO@fastwebnet.it
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Table of contents
Introduction..........................................................................................................................................4 Technical Data .....................................................................................................................................5 Circuit description................................................................................................................................6 CPU (Central Processing Unit) ........................................................................................................6 Operations ....................................................................................................................................9 Receiver .........................................................................................................................................11 Transmitter .....................................................................................................................................12 PLL VCO .....................................................................................................................................12 PLL parameters ..........................................................................................................................13 How to calculate the N and A values ? ......................................................................................14 Registers N and A for each frequency .......................................................................................15 Schematics .........................................................................................................................................16 Parts List ............................................................................................................................................20 Semiconductors outline drawings ......................................................................................................22 PCB layout .........................................................................................................................................24 Firmware ............................................................................................................................................26 Calibration..........................................................................................................................................30 CPU programming .........................................................................................................................30 PLL calibration ..............................................................................................................................30 Receiver calibration .......................................................................................................................30 Transmitter calibration...................................................................................................................30 Components Suppliers .......................................................................................................................31 Software .............................................................................................................................................31 Note....................................................................................................................................................31 Limitation of incidental or consequential damages ...........................................................................31 Pictures...............................................................................................................................................32
Introduction
The complexity of amateur transceivers reached the point that their construction is generally left to commercial manufacturers. For many radio amateurs the number of components required to build such a project and their assembly often discourage from starting this adventure. Another question that many amateurs are asking is why should I build a homebrewed radio when I could buy it paying less and perhaps obtaining more functions ? and this is for sure a correct question ! Electronic difficulties are accompanied by mechanical problems. Replicating the mechanical aspect of a modern enclosure seems to require a machine shop and the talents of an artist. There are many difficulties not always easily and economically overcoming but the most important reason which encourages the amateur to start this adventure is the ability to transmit and to receive his voice with an object built with his own hands. Who builds a homebrewed radio lives on the spirit of Guglielmo Marconi1, who faced the airwaves with his radio equipments and experiments. This is my second transceiver, designed with the desire to constantly learn new concepts and experiment with new techniques. I wanted to design a easy to build radio with readily available components. This paper describes the main concepts and the construction of a QRP VHF transceiver on the 2m band (144-148 MHz) designed after many experiments and tests. I have used all discrete components avoiding the use of SMD components, difficult to solder and replace. This transceiver is based on a microcontroller that governs all the functions. The controller I used is the Parallax Basic Stamp BS2-IC. The transceiver is based on classic superheterodyne design. It adopts a double conversion narrowband superheterodyne FM receiver with excellent sensitivity achieved by a dual-gate MOSFET. The project of the receiver has been significantly simplified by using a Motorola MC3372 integrated circuit. The frequency stability of the VCO is then achieved using a PLL with reference frequency of 8 MHz, I used a Fujitsu PLL MB1502 working up to 1.1 Ghz. The transmitter provides about 1.5 W of power into a load of 52 ohms.
I hope you will find this lecture interesting and useful for your next radio creations.
Note: This transceiver may be operated only by radio amateurs as part of their approval.
http://www.nobelprize.org/nobel_prizes/physics/laureates/1909/marconi-bio.html
Technical Data
General
Frequency range: 144-148 MHz U.S.A. (144-146 Europe) Channel spacing: 25kHz Power supply: 13.8 V DC 20% (negative ground) Microprocessor PLL controlled
Receiver
Double-conversion super heterodyne system Sensitivity: 0.2vV typical (at 12dB SINAD) Intermediate frequencies: 1st 10.7Mhz, 2nd 455 Khz Audio output power 1W at 10% distortion at 8
Transmitter
RF power: 1.5W at 12V
User interface
Button: frequency UP Button: frequency DOWN Button: MID frequency Button: Microphone PTT (push to talk) AF gain Squelch LCD Display S-meter for signal reception and power transmission
Circuit description
In this picture you can see the block diagram of the transceiver.
Fig. 1: RTX block diagram
CPU (Central Processing Unit)
The transceiver is controlled by a Parallax Basic Stamp "BS2-IC" CPU. For any specific and detailed information about this great processor, visit the site: http://www.parallax.com A BASIC Stamp is a single-board computer that runs the Parallax PBASIC language interpreter. The developer's code is stored in an EEPROM, which can also be used for data storage. The PBASIC language has easy-to-use commands for basic I/O, like turning devices on or off, interfacing with sensors, etc. More advanced commands let the BASIC Stamp module interface with other integrated circuits, communicate with each other, and operate in networks. The BASIC Stamp microcontroller has prospered in hobby, lower-volume engineering projects and education due to ease of use and a wide support base of free application resources.
Fig. 2: Basic Stamp schematic diagram 7
The BS2 controls all functions of the radio: frequency change, muting status, PLL programming, power switching. The firmware is written in PBasic. The user interaction occurs through three input buttons and through a display for displaying messages. The processor performs these tasks: acquires the user's input: frequency change and pressure of the transmissin button (PTT); provides power to the various circuits of the radio (transmitter, receiver, PLL-VC); programs the registers of the PLL using a synchronous SPI bus (latch Enable, clock, data).
Fig. 3: Main blocks with data / power lines
CPU Pin 5 6 7 8 9 10 11 12 13 14 15 16
Pin name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11
Signal PLL lock (from MB1502)
Signal direction input input output output output output output output output input input input
0 Error ON OFF OFF OFF NA NA NA NA PRESSED PRESSED PRESSED
1 Lock OFF ON ON ON NA NA NA NA
Muting status (from MC3772) PLL power RECEIVER power TRANSMITTER power PLL LE PLL data PLL clock Serial display Button frequency DOWN Button MID frequency Button frequency UP
Fig. 4: CPU lines description
Operations
When you power the radio on this goes in receive mode and tunes itself to the low band limit frequency (144 MHz), then It enters in a loop that controls the PTT button and the buttons that change frequency. Reception (RX): 1) the CPU turns on the PLL circuit: P2 =1; 2) the CPU communicates to the PLL parameters N and A through P5, P6, P7 lines; 3) the CPU turns on the receiving circuit: P3=1. Frequency change UP (the radio is in reception mode): 1) communicates to the PLL the parameters N and A through P5, P6, P7 lines; 2) updates the frequency on LCD Display (P8 line). Frequency change DOWN (the radio is in reception mode): 1) communicates to the PLL the parameters N and A through P5, P6, P7 lines; 2) updates the frequency on LCD Display (P8 line). Transmission (TX): 1) The CPU detects PTT button activation P9=0; 2) turns off the RX circuit: P3=0; 3) communicates to the PLL the parameters N and A through P5, P6, P7 lines; 4) turns on the TX circuit: P4=1.
Fig. 5: finite automata representing the states: RX and TX
Fig. 6: software flowchart
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Receiver
The principle of operation of the superheterodyne receiver depends on the use of frequency mixing. The signal from the antenna is filtered to reject the image frequency and then is amplified. A local oscillator (VCO) produces a sine wave which mixes with signal from antenna, shifting it to a specific intermediate frequency (IF), usually a lower frequency. The IF signal is itself filtered and amplified and possibly processed in additional ways. The demodulator uses the IF signal rather than the original radio frequency to recreate a copy of the original modulation (audio). The radio signal coming from the antenna is very small, often only a few microvolts, this will be tuned with L1, C3 and amplified with a Mosfet MSFT1. One more tuned circuit L2, C4 at this stage blocks frequencies which are far from the intended reception frequency. The signal is then fed into a circuit build around the Mosfet MSFT2 where it is mixed with a sine wave from a variable controlled oscillator known as VCO (POS-200). The mixer produces both sum and difference beat frequencies signals, each one containing the modulation contained in the desired signal. The output of the mixer includes the original RF signal at fd, the local oscillator signal at fLO, and the two new frequencies fd+fLO and fd-fLO. The mixer may inadvertently produce additional frequencies such as 3rd and higher-order intermodulation products. The undesired signals are removed by the IF bandpass filter XF1, leaving only the desired offset IF signal at fIF (10.7 Mhz) which contains the original modulation (transmitted information) as the received radio signal had at fd. The next stage is the intermediate frequency amplifier TR1 that is tuned to the specific frequency of 10.7 Mhz not dependent on the receiving frequency. The 10.7 Mhz signal is entered in the discriminator stage IC2 (MC3372). The MC3372 performs single conversion FM reception and consists of an oscillator, mixer, limiting IF amplifier, quadrature discriminator, active filter, squelch switch, and meter drive circuitry. This device is designed for use in FM dual conversion communication equipment.
Fig. 7: MC3372 and TDA7052 pinout

The MC3372 is similar to the MC3361/MC3357 FM IFs, except that a signal strength indicator replaces the scan function controlling driver which is in the MC3361/MC3357. The muting function is implemented connecting the pin 14 (Mute) to the pin 4 of the TDA7052. A transistor TR3 communicates to the CPU the status of this line.
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Transmitter
The signal from the VCO is amplified by the MAV-11 before being sent to the final stage TR11. The audio modulation it performed using a transistor TR4 that amplifies the signal coming from the microphone.
PLL VCO
A voltage-controlled oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage input. The frequency of oscillation is varied by the applied DC voltage, while modulating signals may also be fed into the VCO to cause frequency modulation (FM). The VCO used in this RTX is the POS-200 from Mini-Circuits.
Fig. 8: POS-200 functional data

The VCO generates a signal within the 144-148 Mhz (144-146 Mhz in Europe) frequency range for the transmission and within the 133.3-137.3 Mhz frequency range for the reception. The VCO output is connected to the receiver mixer and to the MAV-11 amplifier for the transmitter. The VCO circuit is always active. In reception mode the receiver part is powered by the microprocessor and the VCO injects its signal in the mixer. In transmission mode the receiving part is switched off, the PLL is updated with the parameters required to produce frequencies from 144 to 148 MHz and the transmitter is switched on. The VCO is controlled by the PLL (Phase Locked Loop). The main blocks inside a PLL are: the comparator phase (Phase Detector), the low pass filter PB (loop filter), the VCO (Voltage Controlled Oscillator) and the reference oscillator.
Fig. 9: PLL description

In principle, a PLL is a device that locks the phase or the frequency of an output signal to a reference. At the operational level, therefore, the phase comparator makes a comparison between
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the phase reference signal and the signal output from the VCO and generates a voltage whose average value is proportional to the phase shift of the two signals. The output signal from the phase comparator is then a square wave with a variable duty-cycle and is up to the low pass filter to extract only the component continues to be applied to the oscillator voltage-controlled VCO. As can be seen on the diagram the entire system is negative feedback that tends to stabilize the VCO frequency equal to the input of reference but, as a result of hardware used in the phase comparators, the two signals, there will usually be a fixed phase difference, the previous situation goes under the name of "signal lock". The Fujitsu MB1502 PLL, utilizing BI-CMOS technology, is a single chip serial input PLL synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary 11bit programmable counter) and analogue switch to speed up lock up time.
PLL parameters
The microcontroller BS2-IC communicates with the PLL using three data lines (Latch enable, Data, Clock). The synchronous serial protocol (SPI) is used to load data into the latch R, N, A and SW registers. The data must be transferred in this order: 1) 2) 3) 4) 5) 6) registers SW, R; control bit C=1; clock pulse (PULSOUT); registers N, A; control bit C=0; clock pulse (PULSOUT).
With this procedure each value is loaded in the respective latch that stores and provides the corresponding divisor.
SHIFTOUT DataPin, ClockPin, MSBFIRST, [1\1] SHIFTOUT DataPin, ClockPin, MSBFIRST, [640\14] SHIFTOUT DataPin, ClockPin, MSBFIRST, [1\1] PULSOUT LatchEnablePin, 15 SHIFTOUT DataPin, ClockPin, MSBFIRST, [N\11] SHIFTOUT DataPin, ClockPin, MSBFIRST, [A\7] SHIFTOUT DataPin, ClockPin, MSBFIRST, [0\1] PULSOUT LatchEnablePin, 15 ' BIT SW ' register R ' bit C=1 ' LOAD N ' LOAD A ' bit C=0
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Fig. 10: MB1502 internal registers
How to calculate the N and A values ?

Lets do an example. Supposing we want to know the N and A paramenters for a 145 Mhz frequency: RIF = 12.5 Khz = 12500 Hz P = 64 F = 145 Mhz = 145000000Hz
FVCO = RIF [(P N ) + A]
To compute N and A: Division factor: FDC =
FVCO 145000000 = = 181.25 P RIF 64 12.5
N = integer part(FDC) = integer part(181.25) = 181 A =P * decimal(FDC) = 64*0.25 = 16
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Registers N and A for each frequency

Transmission Frequency 144,000 144,025 144,050 144,075 144,100 144,125 144,150 144,175 144,200 144,225 144,250 144,275 144,300 144,325 144,350 144,375 144,400 144,425 144,450 144,475 144,500 144,525 144,550 144,575 144,600 144,625 144,650 144,675 144,700 144,725 144,750 144,775 144,800 N 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 181 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 0 A Reception Frequency 133,300 133,325 133,350 133,375 133,400 133,425 133,450 133,475 133,500 133,525 133,550 133,575 133,600 133,625 133,650 133,675 133,700 133,725 133,750 133,775 133,800 133,825 133,850 133,875 133,900 133,925 133,950 133,975 134,000 134,025 134,050 134,075 134,100 N 166 166 166 166 166 166 166 166 166 166 166 166 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 167 A 40 42 44 46 48 50 52 54 56 58 60 62 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

147,825 147,850 147,875 147,900 147,925 147,950 147,975 148,000

184 184 184 184 184 184 184 185

50 52 54 56 58 60 62 0

137,125 137,150 137,175 137,200 137,225 137,250 137,275 137,300

171 171 171 171 171 171 171 171

26 28 30 32 34 36 38 40
Fig. 11: PLL parameters datasheet
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Schematics
The circuit diagram is spread over five figures. Figure 1 shows the CPU circuit, Figure 2 the PLL schematic, Figure 3 the receiver schematic, Figure 4 the transmitter circuit and Figure 5 the power commutation circuit.
C59 10 nF
GND
CPU +
IN
OUT
C60 10 nF
C61 47 mF
DB9 6 7 8 9
RS-232 1 2 3 4 5 IC1 Parallax Basic Stamp BS2-IC 1 2 SOUT SIN ATN VSS P0 P1 P2 P3 P4 P5 P6 P7 VIN VSS RES VDD P15 P14 P13 P12 P11 P10 P9 P8 24 23 22 21 20 19 18 17 16 15 14 13 R42 R44 R45 R51 C55 10 nF
+5V (*)
+5V (*) R41 10K
3 4 5 6
R46 R47 4K7 4K7 R52 4K7 220R 220R 220R 220R R43 4K7
C57 10 nF
R40 CPU.P2 10K CPU.P3 CPU.P4 CPU.P5 CPU.P6 CPU.P7
7 8 9 10 11 12
Freq Mid Freq Micr
IC11 LM7805 GND CPU + C62 10 nF 1 1 IN OUT 2 C63 10 nF
1 2 3
I/O +5V GND
Parallax Serial LCD Display
Figure 13: CPU
16
LM7805 GND 1 IN OUT 2
C49 100 nF 1
C50 100 nF
CPU.P0 IC4 MB1502 R P Fout BISW FC LE LD 8 Fin Data Clock 15 14 13 12 11 GND 10 9 16
C41 10 pF

R13 220R LED1 C40 47 pF 3 VP C43 10 nF 4 VCC C44 100 nF 5 D0 IC5 LM358 OUT1 IN1 IN1 + GND R34 C48 10 nF 10K R33 1K C45 4.7 mF IN2 + 5 7 IN2 6 R35* 680R R32 C46 470R 6 1 mF OUT2 C51 7 100 nF R35 10K VCC 8 R36 560R C42 30 pF 1 OSC IN X2 8 Mhz 2 Osc OUT C85 1 nF 2 3 R38 10K 4 R37 10K 1 C C C R39 100K L TX+ 1 uH R49 10K L C60 R48 10K R50 10K VR1 100K R54 100K R56 3K3 C53 1 mF TR4 BC547 C52 1 mF R53 100K C54 10 mF R55 390R Microphone
VCO POS-200
VCO.TX
VCC
RF OUT
GND
GND
GND
GND2
VCO.RX
Figure 14: PLL
GND
V-Tune
17
Meter RX 100R 1W IC8 LM7805 GND 1 IN D8 1N4148 R20 4K7 TR2 D7 BC547 1N4148 R69 100K VR3 100K 3K9 R23 C34 100 mF C32 47 nF C31 RV2 47 nF PWR-METER R19 100K C35 100 nF C28 100 nF C29 1 nF R24 470K C30 1 nF R22 4K7 R18 1K OUT R25 220R L C18 100 nF 1 1 C39 100 nF C38 100 nF 2 R17 12K RV1 10K
IC7 LM7808 GND 1 IN OUT 2
Muting
RX +
C16 100 nF
12
15
16
14
11
13
10 9
GND
Filter IN
Mixer IN
L2 R10 18K
R12 680R R15 10K IC2 MC3372 Osc1 Osc2 MixOut VCC C17 10 nF
Mute
Meter drive
Squelch IN
Recov. Audio
C6 10 nF C9 100 pF C12 1 nF
R3 27R
G2 G1 S BF988
MFST2
Filter OUT
Limiter IN
Decoupling
Limiter OUT
D1 R11* 18R C10 10 nF R8 1M R9 390R X1 10.245 Mhz
4148
L1
C3 6.8 pF C21 68 pF
C13 100 nF R11 100K C11 100 nF L3 C14 10 nF C15 10 nF TR1 BFR89 L4 XF1 SFVLF10M7LF00-B0 R16 22K Quad IN C23 100 nF C24 100 nF CF2 CFW455D R30 1K8 C25 100 nF C22 220 pF C26 R29 47K R28 47K VCO.RX

R14 100R C19 100 nF C20 10 nF C27 4.7 mF R13 100R
R5 18K
C7 10 nF C8 10 nF
R4 100K
R6 100R
AF Gain
1 C33 10 nF 2 3 D3 1N4148 C36 100 nF R26 10K 4 VP IN +
IC3 TDA7052 OUT N.C. GND1 VC GND2 OUT + 8 7 6 5 S
C1 3.3 pF
C2 G2 100 pF
G1
MSFT1 BF988
C4 R7 5.6 pF 56K
R1 330K
CPU.P1 TR3 BC547 L5 C37 10 nF R68 220R
D2 1N4148
R2 560R
C5 4700 pF
Figure 15: receiver
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TX+ C78** 1 mF C70 100 nF R66 390R C69 1 nF C68 1 nF 1 VCO.TX IC6 MAV-11 C79 30 pF C74 33 pF C71 68 pF 2 L9 L7 4 R67 390R C78* 100 nF
VR2 100K
L10 C78 1 nF D6* AA119
RL.RX A R67 220R C72 4700 pF L12 L11 TR11 2N4427 C75 20 pF D6 1N4148 C73 39 pF L13 RELE
L8
C76 30 pF
C77 1 nF
L6
Figure 16: transmitter

G D5 1N4007 TR8 BD140 TR5 BC547 PLL + R61 4K7 C81 00 nF C64 10 nF P TR10 BD140 TR9 BD140 TR6 BC547 R64 220R R62 220R CPU +
TR7 BC547
TX +
C66 10 nF
RX +
R65 4K7
C83 00 nF
R63 4K7
Figure 17: Power commutation
C82 00 nF
10 nF C65
19
R60 220R
Parts List
Capacitors
C46,C52,C53,C78** C12,C29,C30,C68,C69,C77, C78,C85 C54 C10,C14,C15,C17,C20,C33, C37,C43,C48,C55,C57,C59, C6,C60,C62,C63,C64,C65, C66,C7,C8 C41,C60 C34 C,C11,C13,C16,C18,C19, C23,C24,C25,C26,C28,C35, C36,C38,C39,C44,C49,C50, C70,C78*,C81,C82,C83 C51 C2,C9 C75 C22 C1 C42,C76,C79 C74 C73 C27,C45 C61 C31,C32 C40 C5,C72 C4 C3 C21,C71 4 8 1 1 mF 1 nF 10 mF
21 2 1
10 nF 10 pF 100 mF electrolytic
23 1 2 1 1 1 3 1 1 2 1 2 1 2 1 1 2
100 nF 220 mF 100 pF 20 pF 220 pF 3.3 pF 30 pF variable capacitor 33 pF 39 pF 4.7 mF electrolytic 47 mF electrolytic 47 nF 47 pF 4700 pF 5.6 pF 6.8 pF 68 pF
Resistors R11,R19,R39,R4,R53, R54,R69,RV2,VR1,VR2,VR3 R13,R14,R6 RX R15,R26,R34,R35,R37,R38, R40,R41,R48,R49,R50,RV1 R17 R5, R10 R11* R18,R33 R30 R8 R13,R25,R42,R44,R45,R51, R60,R62,R64,R67,R68 R16 R3 R1 R55,R66,R67,R9 R56 R23 R24
11 3 1 12 1 2 1 2 1 1 11 1 1 1 4 1 1 1
100K 1/6 W 100R 1/6 W 100R 1 W 10K 1/6 W 12K 18K 18R 1K 1K8 1M 1/6 1/6 1/6 1/6 1/6 1/6 W W W W W W
220R 1/6 W 22K 1/6 W 27R 1/6 W 330K 1/6 W 390R 1/6 W 3K3 1/6 W 3K9 1/6 W 470K 1/6 W
20
R32 R28,R29 R20,R22,R43,R46,R47,R52, R61,R63,R65 R2,R36 R7 R12,R35* Transistors TR1 TR2,TR3,TR4,TR5,TR6,TR7 TR8,TR9, TR10 TR11 Crystals X1 X2 Mosfet MFST2,MSFT1 Integrated Circuits IC5 IC11,IC8,IC9 IC7 IC10 IC6 IC4 IC2 IC1 IC3 Diodes D5 D6* D1,D2,D3,D6,D7,D8 Coils L1,L2 L3,L4 L5 L6,L9 L7,L8 L11,L12,L13,L7 L,L10 Ceramic filters CF1 CF2 Miscellaneus VCO SP Meter LCD RELE LED1
1 2 9 2 1 2 1 6 3 1
470R 1/6 W 47K 1/6 W 4K7 1/6 W 560R 1/6 W 56K 1/6 W 680R 1/6 W BFR89 BC547 BD140 2N4427
1 1 2 1 3 1 1 1 1 1 1 1 1 1 6 2 2 1 2 2 3 2 1 1 1 1 1 1 1 1
10.245 Mhz 8 Mhz BF988 LM358 LM7805 LM7808 LM7809 Mini-Circuits MAV-11 Fujitsu MB1502 Motorola MC3372 Basic Stamp BS2-IC, Parallax item code BS2-IC Philips TDA7052 1N4007 AA119 1N4148 Coilcraft 146-04J08SL 10.7 Mhz green IF 455 Khz black IF 0.33 uH 3 turns on air (diameter 4 mm) wire 0.8 mm 4 turns on air (diameter 4 mm) wire 0.8 mm 1 uH Murata SFVLF10M7LF00-B0 Murata CFW455D Mini-Circuits POS-200 8 ohm SPEAKER Meter 4x20 Serial LCD (Backlit), Parallax item code 27979 12V two ways rele LED
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Semiconductors outline drawings

Component BF988 Outline drawing
BFR99
BC547
BD140
MAV-11
22
POS-200
2N4427
LM780XX
23
PCB layout
The PCB was designed using Sprint Layout Software, it is a double face circuit.
Fig. 18: PCB Front view
Fig. 19: PCB back view
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Fig. 20: functional blocks on PCB
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Firmware
' ========================================================================= ' ' File...... PP-002m PP-002m.bs2 ' Purpose... (144-148 Mhz) 2m RTX Firmware ' Author.... IZ0ROO, Paolo Pinto ' E-mail.... iz0roo@fastwebnet.it ' Started... 09-01-2011 ' Updated... 09-20-2011 ' ' {$STAMP BS2} ' {$PBASIC 2.5} ' ' ========================================================================= ' Serial baud rates #SELECT $STAMP #CASE BS2, BS2E, BS2PE T2400 CON 396 T9600 CON 84 T19K2 CON 32 #CASE BS2SX, BS2P T2400 CON 1021 T9600 CON 240 T19K2 CON 110 #ENDSELECT LcdBaud CON T19K2 ' Parallax Serial LCD pin LCD PIN 8 LcdBkSpc LcdRt LcdLF LcdCls LcdCR LcdBLon LcdBLoff LcdOff LcdOn1 LcdOn2 LcdOn3 LcdOn4 LcdLine1 LcdLine2 LcdLine3 LcdLine4 LcdCC0 LcdCC1 LcdCC2 LcdCC3 LcdCC4 LcdCC5 LcdCC6 LcdCC7 muting PIN 1 INPUT muting ' assigns PLL spi bus lines ClockPin PIN 7 DataPin PIN 6 LatchEnablePin PIN 5 ' PLL registers and parameters N1 VAR Byte N2 VAR Byte N VAR Byte A VAR Word A1 VAR Word A2 VAR Word TMP VAR Byte TMP2 VAR Byte LOW LatchEnablePin ' Frequency range LFrequ VAR Word HFrequ VAR Word FStep VAR Word Frequ VAR Word ' initialize latch output CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON CON $08 $09 $0A $0C $0D $11 $12 $15 $16 $17 $18 $19 $80 $94 $A8 $BC $F8 $F9 $FA $FB $FC $FD $FE $FF ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' move cursor left move cursor right move cursor down 1 line clear LCD (use PAUSE 5 after) move pos 0 of next line backlight on backlight off LCD off LCD on; cursor off, blink off LCD on; cursor off, blink on LCD on; cursor on, blink off LCD on; cursor on, blink on move to line 1, column 0 move to line 2, column 0 move to line 2, column 0 move to line 2, column 0 define custom char 0 define custom char 1 define custom char 2 define custom char 3 define custom char 4 define custom char 5 define custom char 6 define custom char 7
' MB1504 clock pin ' MB1504 data pin ' MB1504 latch pin
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Frequ2
VAR
Word
LFrequ=44000-10700 HFrequ=48000-10700 Frequ=LFrequ ' Assigns buttons to BS2 pins pttBtn PIN 9 pttBtnWrk VAR Byte upBtn PIN 11 upBtnWrk VAR Byte midBtn PIN 12 midBtnWrk VAR Byte downBtn PIN 10 downBtnWrk VAR Byte TXState VAR Byte ' Start main program Main: TXState=1 ' Initialize LCD DISPLAY HIGH LCD PAUSE 100 SEROUT LCD, LcdBaud, [LcdBLon] PAUSE 550 SEROUT LCD, LcdBaud, [LcdCls] PAUSE 750 SEROUT LCD, LcdBaud, [(LcdLine1), DEC 1, DEC Frequ+10700, " Mhz SEROUT LCD, LcdBaud, [(LcdLine3), "PP-002m rel. 1.0"] SEROUT LCD, LcdBaud, [(LcdLine4), "(C) 2011 by IZ0ROO"] ' enable PLL circuit HIGH 2 ' set start frequency (144.00 Mhz) N=166 A=40 GOSUB PLL ' calls PLL subroutine ' enable RX circuit LOW 4 'TX OFF HIGH 3 'RX ON N2=180 A2=0 TXState=1 ' STARTS LISTENING FOR BUTTON PRESSED ' It controls the PTT (Push To Talk) line from microphone to enable TX and disable RX PTT: BUTTON pttBtn, 0, 0, 15, pttBtnWrk, 0, No_PressPTT IF TXState=1 THEN LOW 3 'RX OFF HIGH 4 'TX ON TMP=N N=N2 TMP2=A A=A2 GOSUB PLL N=TMP A=TMP2 TXState=0 ENDIF GOTO PTT ' PTT not pressed, RX ON and TX OFF No_PressPTT: IF TXState=0 THEN GOSUB PLL ' calls PLL subroutine ' enable RX circuit LOW 4 'TX OFF HIGH 3 'RX ON TXState=1 N=166 A=40
"]
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ENDIF ' It controls the UP button to increase the frequency FrequUP: BUTTON upBtn, 0, 100, 15, upBtnWrk, 0, FrequMID TXState=1 IF Frequ=LFrequ THEN ' if low limit frequency A1=40 ' set register (RX) A to initial value A2=0 ' set register (TX) A to initial value ENDIF IF Frequ<=HFrequ-25 THEN Frequ=Frequ+25 ' frequency < high limit ' increases frequency 25 Khz
' RX Frequency parameters N1=(Frequ/800)+125 ' computes N parameter for PLL IF (Frequ//800)=0 THEN A1=0 ELSE A1=A1+2 IF A1>62 THEN A1=0 ENDIF ENDIF N=N1 A=A1 GOSUB PLL ' TX Frequency parameters N2=((Frequ+10700)/800)+125 IF Frequ=LFrequ THEN A2=0 ENDIF IF ((Frequ+10700)//800)=0 THEN A2=0 ELSE A2=A2+2 IF A2>62 THEN A2=0 ENDIF ENDIF SEROUT LCD, LcdBaud, [(LcdLine1), DEC 1, DEC Frequ+10700, " Mhz"] ENDIF FrequMID: BUTTON midBtn, 0, 100, 15, midBtnWrk, 0, FrequDOWN TXSTate=1 N2=181 A2=16 N1=167 A1=56 N=N1 A=A1 Frequ=34300 GOSUB PLL SEROUT LCD, LcdBaud, [(LcdLine1), DEC 1, DEC Frequ+10700, " Mhz"] ' It controls the DOWN button to decrease the frequency FrequDOWN: BUTTON downBtn, 0, 100, 15, downBtnWrk, 0, No_PressDOWN TXSTate=1 IF Frequ=LFrequ THEN A1=40 A2=0 ENDIF IF Frequ>=LFrequ+25 THEN Frequ=Frequ-25 ' RX Frequency parameters N1=(Frequ/800)+125 IF (Frequ//800)=0 THEN A1=0 ELSE A1=A1-2 IF A1=65534 THEN
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A1=62 ENDIF ENDIF N=N1 A=A1 GOSUB PLL ' TX Frequency parameters N2=((Frequ+10700)/800)+125 IF ((Frequ+10700)//800)=0 THEN A2=0 ELSE A2=A2-2 IF A2=65534 THEN A2=62 ENDIF ENDIF SEROUT LCD, LcdBaud, [(LcdLine1), DEC 1, DEC Frequ+10700, " Mhz"]
ENDIF
' down button not pressed No_PressDOWN: TXState=1 IF muting=0 THEN SEROUT LCD, LcdBaud, [(LcdOn1), (LcdLine2), "MUTING OFF ELSE SEROUT LCD, LcdBaud, [(LcdOn1),(LcdLine2), "MUTING ON ENDIF GOTO PTT ' PLL Subroutine, it sends division parameters to PLL PLL: SHIFTOUT DataPin, ClockPin, MSBFIRST, [1\1] ' SHIFTOUT DataPin, ClockPin, MSBFIRST, [640\14] ' SHIFTOUT DataPin, ClockPin, MSBFIRST, [1\1] ' PULSOUT LatchEnablePin, 15 SHIFTOUT DataPin, ClockPin, MSBFIRST, [N\11] SHIFTOUT DataPin, ClockPin, MSBFIRST, [A\7] SHIFTOUT DataPin, ClockPin, MSBFIRST, [0\1] PULSOUT LatchEnablePin, 15 RETURN
"] "]
through SPI protocol BIT SW register R bit C=1
' LOAD N ' LOAD A ' bit C=0
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Calibration
CPU programming Before tuning the radio, You have to upload the firmware in the CPU. To calibrate the radio You will need the following tools: signal generator; digital frequency meter; VHF receiver on the working frequencies of the transceiver. The calibration of the radio is required to obtain the best signal reception and the best signal transmission. I suggest to tune the generator at the frequency of 145 MHz, modulating the signal at 7 kHz, connect its output at the entrance of the antenna and set the signal level at 50 uV. PLL calibration Connect the digital frequency meter to adjust the PLL reference oscillator. 1) measure the frequency from the IC4 Pin 1; 2) adjust the C42 variable capacitor in order to obtain an 8 Mhz reading. Receiver calibration: Once activated, the generator, You will need to: 1) tune the generator on 145 Mhz modulating the carrier with a 1 Khz signal; 2) tune the radio on 145 Mhz 3) adjust the IFs L3 and L4 for the maximum s-meter deviation; 4) adjust the s-meter trimmer if it isnt possible to see any movement from the instrument; 5) adjust the coils L1 and L2 to increase the s-meter reading; 6) repeat the procedure from point 3 up to reach the best signal reading; 7) adjust the coil L5 to obtain the lower sound distortion. Transmitter calibration: 1) tune the radio on 145 Mhz; 2) connect a 50 ohm load or an antenna; 3) push the PTT button; 4) adjust the C79, C75, C76 capacitors in order to obtain the maximum deviation of the s-meter; 5) adjust the VR2 Trimmer to bring the s-meter indicator up to the maximum reading; 6) adjust the VR1 modulation trimmer to get the best modulation. In this case it is necessary the use of a receiver tuned on 145 Mhz used to listen at the transmitted sound.
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Components Suppliers
Parallax: Digikey: RF Microwaves: Printed Circuit Board Manufacturer: Coilcraft: (special thanks to "Coilcraft" for coils samples): http://www.parallax.com http://www.digikey.com http://www.rfmicrowave.it http://www.pcb4u.it http://www.coilcraft.com
Software
Printed Circuit Board cad: Sprint Layout 5.0: Schematic Diagram: TinyCAD ver.2.80.03: Parallax BS-2 PBasic Editor: http://www.abacom-online.de http://tinycad.sourceforge.net http://www.parallax.com
Note
Gerber files are available on request.
Limitation of incidental or consequential damages

The construction of this device is the responsibility of the reader. The author will not be liable for any special, indirect, incidental or consequential damages, including but not limited to any loss of business or profits.
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Pictures
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FM Transceiver Project (144-148 MHZ)

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How does the transceiver work?

QRP 2m FM Transceiver Project

IZ0ROO, Paolo Pinto

QRP 2m FM Transceiver PP-002m

QRP 2m FM Transceiver PP-002m

QRP 2m FM Transceiver PP-002m

QRP 2m FM Transceiver PP-002m

QRP 2m FM Transceiver PP-002m

Fig. 1: RTX block diagram

CPU (Central Processing Unit)

QRP 2m FM Transceiver PP-002m

Fig. 2: Basic Stamp schematic diagram 7

QRP 2m FM Transceiver PP-002m

Fig. 3: Main blocks with data / power lines

Pin name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11

Signal PLL lock (from MB1502)

0 Error ON OFF OFF OFF NA NA NA NA PRESSED PRESSED PRESSED

Fig. 4: CPU lines description

QRP 2m FM Transceiver PP-002m

Fig. 5: finite automata representing the states: RX and TX

QRP 2m FM Transceiver PP-002m

Fig. 6: software flowchart

QRP 2m FM Transceiver PP-002m

Fig. 7: MC3372 and TDA7052 pinout

QRP 2m FM Transceiver PP-002m

Fig. 8: POS-200 functional data

Fig. 9: PLL description

QRP 2m FM Transceiver PP-002m

QRP 2m FM Transceiver PP-002m

Fig. 10: MB1502 internal registers

How to calculate the N and A values ?

FVCO = RIF [(P N ) + A]

To compute N and A: Division factor: FDC =

FVCO 145000000 = = 181.25 P RIF 64 12.5

N = integer part(FDC) = integer part(181.25) = 181 A =P * decimal(FDC) = 64*0.25 = 16

QRP 2m FM Transceiver PP-002m

Registers N and A for each frequency

Fig. 11: PLL parameters datasheet

QRP 2m FM Transceiver PP-002m

+5V (*) R41 10K

R40 CPU.P2 10K CPU.P3 CPU.P4 CPU.P5 CPU.P6 CPU.P7

Freq Mid Freq Micr

IC11 LM7805 GND CPU + C62 10 nF 1 1 IN OUT 2 C63 10 nF

I/O +5V GND

Parallax Serial LCD Display

Figure 13: CPU

QRP 2m FM Transceiver PP-002m

LM7805 GND 1 IN OUT 2

CPU.P0 IC4 MB1502 R P Fout BISW FC LE LD 8 Fin Data Clock 15 14 13 12 11 GND 10 9 16

QRP 2m FM Transceiver PP-002m

Figure 14: PLL

IC7 LM7808 GND 1 IN OUT 2

D1 R11* 18R C10 10 nF R8 1M R9 390R X1 10.245 Mhz

QRP 2m FM Transceiver PP-002m

IC3 TDA7052 OUT N.C. GND1 VC GND2 OUT + 8 7 6 5 S