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    Digital Cycle Sheet

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    Kristy Jose
    This document provides an overview of experiments conducted in a digital logic lab course. The experiments cover topics including basic logic gates, combinational circuits, adders and subtractors, seven segment displays, encoders/decoders, multiplexers, sequential circuits, counters, and synchronous/asynchronous circuits. The objectives are to introduce students to Altera Quartus II software for schematic design and ModelSim simulator, and to demonstrate various digital logic design concepts through hands-on experiments.

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    Download as PDF, TXT or read online from Scribd

    Digital Cycle Sheet

    Uploaded by

    Kristy Jose
    52 views4 pages
    This document provides an overview of experiments conducted in a digital logic lab course. The experiments cover topics including basic logic gates, combinational circuits, adders and subtractors, seven segment displays, encoders/decoders, multiplexers, sequential circuits, counters, and synchronous/asynchronous circuits. The objectives are to introduce students to Altera Quartus II software for schematic design and ModelSim simulator, and to demonstrate various digital logic design concepts through hands-on experiments.

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    cycle sheeet for digital

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    This document provides an overview of experiments conducted in a digital logic lab course. The experiments cover topics including basic logic gates, combinational circuits, adders and subtractors, seven segment displays, encoders/decoders, multiplexers, sequential circuits, counters, and synchronous/asynchronous circuits. The objectives are to introduce students to Altera Quartus II software for schematic design and ModelSim simulator, and to demonstrate various digital logic design concepts through hands-on experiments.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    52 views4 pages

    Digital Cycle Sheet

    Uploaded by

    Kristy Jose
    This document provides an overview of experiments conducted in a digital logic lab course. The experiments cover topics including basic logic gates, combinational circuits, adders and subtractors, seven segment displays, encoders/decoders, multiplexers, sequential circuits, counters, and synchronous/asynchronous circuits. The objectives are to introduce students to Altera Quartus II software for schematic design and ModelSim simulator, and to demonstrate various digital logic design concepts through hands-on experiments.

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    Download as PDF, TXT or read online from Scribd
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    VIT

    UNIVERSITY
    SCHOOL OF COMPUTER SCIENCE AND ENGINEERING B.Tech Computer Science and Engineering CSE 109 Digital Logic Lab

    CYCLE SHEET
    ntroduction Lab! Introduction to Altera uartu! II and Altera DE "oard O"#ecti$e!% &' To introduce !tudent! (it) uartu! II !o*t(are *or !c)e+atic de!i,n -' To introduce !tudent! (it) Model.Si+ Si+ulator /' To !)o( t)e 0roce!! o* do(nloadin, t)e de!i,n to )ard(are E"periment 1! Logic #ate$ &' Veri*1 trut) ta"le o* AND2 OR2 and NOT ,ate! -' Veri*1 trut) ta"le o* NAND and NOR ,ate! /' Veri*1 trut) ta"le o* 3OR and 3NOR ,ate! 4' S)o( t)at NAND and NOR are uni$er!al ,ate!' 5' Veri*1 De.Mor,an6! la( *or t)ree $aria"le!' E"periment %! Combinational circuit$ &' You !)ould lau,) at a #o7e i* it i! *unn12 it i! in ,ood ta!te2 and it i! not o**en!i$e to ot)er!2 or i* it i! told in cla!! "1 1our 0ro*e!!or 8re,ardle!! o* ()et)er it i! *unn1 and in ,ood ta!te9 and it i! not o**en!i$e to ot)er!' I+0le+ent u!in, "a!ic ,ate!' -' T)e co+0an1 !a*e !)ould "e unloc7ed onl1 ()en Mr' :one! i! in t)e o**ice or Mr' E$an! i! in t)e o**ice2 and onl1 ()en t)e co+0an1 i! o0en *or "u!ine!!2 and onl1 ()en t)e !ecurit1 ,uard i! 0re!ent' I+0le+ent u!in, onl1 NAND ,ate!' /' You !)ould (ear 1our o$er!)oe! i* 1ou are out!ide in a )ea$1 rain and 1ou are (earin, 1our ne( !uede !)oe!2 or i* 1our +ot)er tell! 1ou to' E;0re!! t)e ,i$en 0ro"le+ in POS *or+ o* e;0re!!ion' I+0le+ent u!in, onl1 NOR ,ate! 4' Four c)air! are 0laced in a ro(% Eac) c)air +a1 "e occu0ied 8&9 or e+0t1 8<9' F8 A2 B2 C2 D9 i! & i** t)ere are +ore 0eo0le !ittin, in t)e le*t t(o c)air! t)an in t)e ri,)t t(o c)air!' Reali=e t)e ,i$en 0ro"le+ in all *our di**erent *or+! o* >oolean e;0re!!ion! E"periment &! 'dder$ and Subtractor$ &' De!i,n a *ull adder u!in, t(o )al* adder!' -' De!i,n a co+"inational circuit (it) t)ree in0ut!2 ;2 12 and =2 and t)ree out0ut!2 A2 > and C u!in, *ull adder and an in$erter' ?)en t)e "inar1 in0ut i! <2 &2 -2 or /2 t)e "inar1 out0ut i! one ,reater t)an t)e in0ut' ?)en t)e "inar1 in0ut i! 42 52 @2 or A2 t)e "inar1 out0ut i! one le!! t)an t)e in0ut' /' De!i,n a *ull !u"tractor u!in, t(o )al* !u"tractor!' 4' I+0le+ent t)e *our >oolean *unction! li!ted u!in, t)ree )al* .adder! DB E B AC>C D A>CC F B A>CC D 8AC D >C9C G B A>C

    E"periment (! Se)en Segment Di$pla* and Code Con)erter$ &' To de!i,n t)e >CD to !e$en !e,+ent circuit 8u!e !e$en !e,+ent di!0la1 to !)o( t)e out0ut9 -' De!i,n a circuit to di!0la1 t)rice o* a nu+"er on !e$en !e,+ent di!0la1 8Con!ider +a;i+u+ in0ut nu+"er to "e - "it9 /' De!i,n a co+"inational circuit ()ic) con$ert! - 4 - & code to E 4 .- .& code' 4' A circuit )a! *our in0ut! RSTU and *our out0ut! VWYZ. RSTU re0re!ent! a "inar1 coded. deci+al di,it' VW re0re!ent! t)e Fuotient and YZ t)e re+ainder ()en RSTU i! di$ided "1 / 8VW and YZ re0re!ent -."it "inar1 nu+"er!9' A!!u+e t)at in$alid in0ut! do not occur' De!i,n a code con$erter ()ic) con$ert! RSTU to VWYZ' E"periment +! Binar* ,arallel 'dder and -agnitude Comparator &' De!i,n - . "it 0arallel adderG!u"tractor circuit' -' De!i,n >CD adder u!in, "inar1 0arallel adder!' /' De!i,n E;ce!!.5 to >CD code con$erter u!in, "inar1 0arallel adder' 4' Deter+ine ()ic) o* t)ree ,i$en in0ut! A2 >2 and C i! ,reate!t u!in, -."it Ma,nitude Co+0arator ()ere A2 >2 and C are -.di,it "inar1 nu+"er!' E"periment .! Decoder and Encoder &' To de!i,n - to 4 line decoder -' De!i,n a lo,ic circuit to control t)e tra**ic li,)t a! 0er t)e ,i$en detail!' Ve)icle detection !en!or! are 0laced alon, C and D 8+ain road9 and lane! A and > 8acce!! road9' T)e!e !en!or out0ut! are LO? 8<9 ()en no $e)icle i! 0re!ent and HIGH 8&9 ()en a $e)icle i! 0re!ent' T)e inter!ection tra**ic li,)t i! to "e controlled accordin, to t)e *ollo(in, lo,ic% a' T)e ea!t.(e!t 8E.?9 tra**ic li,)t (ill "e ,reen ()ene$er "ot) lane! C and D are occu0ied' "' T)e E.? li,)t (ill "e ,reen ()ene$er eit)er C or D i! occu0ied "ut lane! A or > are not occu0ied' c' T)e nort).!out) 8N.S9 li,)t (ill "e ,reen ()ene$er "ot) lane! A and > are occu0ied "ut C or D are not occu0ied' d' T)e N.S li,)t (ill al!o "e ,reen ()en eit)er A or > i! occu0ied ()ile C and D are "ot) $acant' e' T)e E.? li,)t (ill "e ,reen ()en no $e)icle! are 0re!ent' U!in, t)e !en!or out0ut! A2 >2 C and D a! in0ut!2 N.S and E.? "e t(o out0ut! t)at ,o )i,) ()en t)e corre!0ondin, li,)t to "e ,reen' Si+ulate t)e a"o$e !cenario u!in, decoder!' /' De!i,n a deci+al to >CD Encoder' 4' To de!i,n and i+0le+ent E line to / line 0riorit1 encoder' Include an out0ut HE6 8ena"le9 to indicate t)at at lea!t one in0ut i! H&6' E"periment /! -ultiple"er$ and De0multiple"er$ &' S)o( )o( t(o 4.to.& and one -.to.& +ulti0le;er! could "e connected to *or+ an E.to.& MU3 (it) t)ree control in0ut!' -' De!i,n a 4."it E$en 0arit1 C)ec7er u!in, a +ulti0le;er /' De!i,n -.to.4 line de.+ulti0le;er u!in, NOR ,ate! 4' De!i,n a circuit ()ic) 0er*or+ 3 I Y i* A B & and Y I3 i* A B<' Hint% U!e a -."it !u"tractor and t(o -."it - ; & MU3'

    E"periment 1! Se2uential circuit$ and Shi3t regi$ter$

    &' A !eFuential circuit )a! t(o *li0.*lo0! A and >2 t(o in0ut! ; and 12 and an out0ut =' T)e *li0. *lo0 in0ut *unction! and circuit *unction! are a! *ollo(!% :A B ;>D1C>C JA B ;1C>C :> B ;AC J> B ;1CDA K B ;1A D ;C1C> To o"tain t)e !tate ta"le and i+0le+ent t)e circuit to $eri*1 t)e o"tained !tate ta"le -' For t)e *ollo(in, !eFuential net(or72 *ind t)e ne;t.!tate eFuation *or eac) *li0.*lo0' U!in, t)e!e ne;t.!tate eFuation!2 con!truct t)e !tate ta"le and !tate dia,ra+'

    /' Tran!*er t)e content! o* re,i!ter HA6 to re,i!ter H>6 in a !erial +anner u!in, !)i*t re,i!ter!' T)e content! o* t)e re,i!ter HA6 need to "e retained' 4' I+0le+ent a *our "it !erial adder u!in, !)i*t re,i!ter E"periment 9! S*nchronou$ Counter$ &' De!i,n and i+0le+ent *our "it !1nc)ronou! u0 I do(n "inar1 counter -' De!i,n and i+0le+ent a "inar1 counter (it) t)e re0eated !eFuence a! <2 &2 /2 A2 @2 4 u!in, SR *li0 *lo0!' /' De!i,n Mod.L Counter u!in, 4."it "inar1 counter (it) 0arallel load' 4' De!i,n and i+0le+ent *our "it :o)n!on counter E"periment 10! '$*nchronou$ counter$ &' De!i,n and i+0le+ent a!1nc)ronou! "inar1 counter -' De!i,n and i+0le+ent a!1nc)ronou! >CD counter /' Deter+ine t)e count !eFuence o* t)e counter and identi*1 (eat)er t)e counter i! !el*.!tartin, or not'

    4' De!i,n a Mod.@ ri00le counter'

    '$$ignment$
    &' -' /'

    Accu+ulator ALU >idirectional S)i*t Re,i!ter'

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