BU1924
BU1924
BU1924
Audio ICs
!Applications RDS / RBDS compatible FM receivers for American and European markets, car stereos, high-fidelity stereo systems and components, and FM pagers.
!Features 1) Low current. 2) Two-stage anti-aliasing filter (LPF). 3) 57kHz band-pass filter. 4) DSB demodulation (digital PLL). 5) Quality indication output for demodulated data.
1/5
BU1924 / BU1924F
Audio ICs
!Block diagram
120k
100k
Vref
(3)
anti-aliasing filter
(16) RCLK
(1)
QUAL
VSS1
(6)
VDD2
PLL 1187.5Hz
Bi-phase decoder
Differential decoder
(2)
RDATA
VSS2
T1
33pF
33pF
1 : VDD1 and VDD2 are separated within the IC. 2 : Have VDD2 (digital power supply) of a sufficiently low impedance. 3 : Match the capacitor constants with the crystal manufacturer.
RCLK
(N.C.)
VDD2
XO
VSS2
T1
XI
16
15
14
13
12
11
10
1 QUAL
2 RDATA
3 Vref
4 MUX
5 VDD1
6 VSS1
7 VSS3
8 CMP
T2 9
2/5
BU1924 / BU1924F
Audio ICs
!Pin descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol QUAL RDATA Vref MUX VDD1 VSS1 VSS3 CMP T2 T1 VSS2 VDD2 XI XO (N.C.) RCLK Crystal oscillator Demodulator clock Digital power supply 2.7V to 5.5V Connects to 4.332MHz oscillator (refer to input/output circuits) 1187.5Hz clock (refer to the timing diagram) Test input Open or connected to ground Type B Analog power supply 2.7V to 5.5V GND Comparator input C-junction (refer to input/output circuits ) Pin name Functions Input/Output type Type C Type C Type E Type F Type D Demodulator quality Good data : High, bad data : Low Demodulator data Reference voltage Input Refer to output data timing 1/2 VDD1 (refer to input/output circuits) Composite signal input (refer to input/output circuits)
Type A Type C
Type B
Type C
Type D
Type E
Type F
VREF
3/5
BU1924 / BU1924F
Audio ICs
!Electrical characteristics (unless otherwise noted, Ta = 25C, VDD1 = VDD2 = 5.0V, VSS1 =VSS2 = VSS3 = 0.0V)
Parameter
Operating current Reference voltage Input current 1 Output current 1 Input current 2 Output current 2 Output high level voltage 1 Output low level voltage 1 Filter block Center frequency Gain Attenuation 1 Attenuation 2 Attenuation 3 S / N ratio Demodulator RDS detector sensitivity RDS input level Data rate Clock transient vs. data
Not designed for radiation resistance.
Conditions
56.5 20 18 65 35 1.0
57.0 23 22 80 50 35
mVrms mVrms Hz s
RDATA
T1 T1=T2=4.3S
T5
T1
T3 T3=T4=421S
T4 T5=T6=416.7S
T2
T6
T2
The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the rising or falling edge of the clock as the reference. The data is valid for 416.7s. after the reference clock edge.
QUAL pin operation : Indicates the quality of the demodulated data. (1) Good data : HI (2) Poor data : LO
4/5
BU1924 / BU1924F
Audio ICs
!Electrical characteristic curves
30 20 10
FILTER GAIN : G (dB)
0 10 20 30 40 50 60 70 10
20
30 40
50
60
70
80
90 100
FREQUENCY : f (kHz)
19.40.3 16 9
10.00.2
6.50.3
16
6.20.3
8 7.62
0.51Min.
4.40.2
3.20.2 4.250.3
1
0.30.1
2.54 0.50.1 0~15
1.50.1
0.11
1.27
0.40.1
0.3Min. 0.15
DIP16
SOP16
0.150.1
5/5