Adaptive Noise Filter Cancellaton VHDL Code
Uploaded by
Sirisha KurakulaAdaptive Noise Filter Cancellaton VHDL Code
Uploaded by
Sirisha KurakulaADAPTIVE NOISE FILTER CANCELLATON VHDL CODE
----------------------------------------------------------------adaptivefilter.vhd
----------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adaptivefilter is
port (
a1: in std_logic_vector(31 downto 0);
b1: in std_logic_vector(31 downto 0);
mu2: in std_logic_vector(31 downto 0);
ndfi: in std_logic;
rfdfi: out std_logic;
clk: in std_logic;
resultfi: out std_logic_vector(31 downto 0);
rdyfi: out std_logic);
end adaptivefilter;
architecture Behavioral of adaptivfilter is
signal xin0 : std_logic_vector(31 downto 0):=
"11000000000000000000000000000000";
signal xin1 : std_logic_vector(31 downto 0):=
"11000000000000000000000000000000";
signal wt0 : std_logic_vector(31 downto 0):=
"11000000000000000000000000000000";
signal wt1 : std_logic_vector(31 downto 0):=
"11000000000000000000000000000000";
signal rfdmul0, rfdmul1, rfdmul2, rfdmul3, rfdmul4, rfdad0, rfdad1, rfdad2,
rfdsub0 : std_logic:=1;
signal resultad0, resultad1, resultad2, resultmul0, resultmul1, resultmul2,
resultmul3, resultmul4, resultsub0 : std_logic_vector(31 downto 0):=
"11000000000000000000000000000000";
signal ndfi2, ndad, ndsub0, rdymul0, rdymul1, rdymul2, rdymul3, rdymul4,
rdyad0, rdyad1, rdyad2, rdysub0:std_logic:=0;
component fadder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
operation: in std_logic_vector(5 downto 0);
operation_nd: in std_logic;
operation_rfd: out std_logic;
clk: in std_logic;
result: out std_logic_vector(31 downto 0);
rdy: out std_logic);
end component;
component fmultiplier
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
operation_nd: in std_logic;
operation_rfd: out std_logic;
clk: in std_logic;
result: out std_logic_vector(31 downto 0);
rdy: out std_logic);
end component;
begin
mul0: fmultiplier port map(xin0,wt0,ndfi2,rfdmul0,clk,resultmul0,rdymul0);
mul1: fmultiplier port map(xin1,wt1,ndfi2,rfdmul1,clk,resultmul1,rdymul1);
ndad<=rdymul0;
add0: fadder port map
(resultmul0,resultmul1,"000000",ndad,rfdad0,clk,resultad0,rdyad0);
sub: fadder port map
(b1,resultad0,"000001",rdyad0,rfdsub0,clk,resultsub0,rdysub0);
mul2: fmultiplier port map
(mu2,resultsub0,rdysub0,rfdmul2,clk,resultmul2,rdymul2);
mul3: fmultiplier port map
(resultmul2,xin0,rdymul2,rfdmul3,clk,resultmul3,rdymul3);
mul4: fmultiplier port map
(resultmul2,xin1,rdymul2,rfdmul4,clk,resultmul4,rdymul4);
add1: fadder port map
(wt0,resultmul3,"000000",rdymul4,rfdad1,clk,resultad1,rdyad1);
add2: fadder port map
(wt1,resultmul4,"000000",rdymul4,rfdad2,clk,resultad2,rdyad2);
resultfi<=resultad0;
rdyfi<=rdyad2;--last ready output
rfdfi<=rdyad0;--last ready for data;not giving;
process( ndfi)
begin
ndfi2<=ndfi;
end process;
READ_NET: process
begin
wait until ndfi = 1;
xin1<=xin0;
xin0<=afi;
end process READ_NET;
READ_wt: process
begin
wait until rdyad2= 1;
wt0<=resultad1;
wt1<=resultad2;
end process READ_wt;
end Behavioral;
-----------------------------------------------------------testbench.vhd
-----------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY testbench is
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT adaptivefilter
PORT(
a1 : IN std_logic_vector(31 downto 0);
b1 : IN std_logic_vector(31 downto 0);
mu2 : IN std_logic_vector(31 downto 0);
ndfi : IN std_logic;
rfdfi : OUT std_logic;
clk : IN std_logic;
resultfi : OUT std_logic_vector(31 downto 0);
rdyfi : OUT std_logic);
END COMPONENT;
signal a1 : std_logic_vector(31 downto 0) := (others => 0);
signal b1 : std_logic_vector(31 downto 0) := (others => 0);
signal mu2 : std_logic_vector(31 downto 0) :=
"00111110000110011001100110011010"; --(0.15)
signal
signal
signal
signal
signal
ndfi : std_logic := 0;
clk: std_logic := 0;
rfdfi : std_logic;
resultfi : std_logic_vector(31 downto 0);
rdyfi : std_logic;
-- Clock period definitions
constant clk_period: time := 2000 ns;
constant nd_period: time := 0.2 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: adaptivfilter PORT MAP (
a1 => a1,
b1 => b1,
mu2 => mu2,
ndfi => ndfi,
rfdfi => rfdfi,
clk => clk,
resultfi => resultfi,
rdyfi => rdyfi);
-- Clock process definitions
clk_process :process
begin
clk <= 0;
wait for clk_period/2;
clk <= 1;
wait for clk_period/2;
end process;
ndfi_process :process
begin
ndfi <= 0;
wait for 500 ns ;
ndfi <= 1;
wait for clk_period;
ndfi <= 0;
wait for 0.175 ms ;
end process;
REA_NET: process
begin
a1 <="00111111100000000000000000000000";
b1 <="00111110100111100011011101111010";
wait for nd_period;
a1 <="00111110100111100011011101111010";
b1 <="00111111100000000000000000000000";
wait for nd_period;
a1 <="10111111010011110001101110111101";
b1 <="00111110100111100011011101111010" ;
wait for nd_period;
a1 <="10111111010011110001101110111101";
b1 <="10111111010011110001101110111101";
wait for nd_period;
a1 <="00111110100111100011011101111010";
b1 <="10111111010011110001101110111101";
wait for nd_period;
end process REA_NET;
END behavior;
