June 2008 Rev 10 1/46

1
M95320 M95320-W M95320-R
M95640 M95640-W M95640-R
32 Kbit and 64 Kbit serial SPI bus EEPROMs
with high-speed clock
Features
Compatible with SPI bus serial interface
(positive clock SPI modes)
Single supply voltage:
4.5 to 5.5 V for M95320 and M95640
2.5 to 5.5 V for M95320-W and M95640-W
1.8 to 5.5 V for M95320-R and M95640-R
10 MHz, 5 MHz or 2 MHz clock rates
5 ms write time
Status Register
Hardware protection of the Status Register
Byte and Page Write (up to 32 bytes)
Self-timed programming cycle
Adjustable size read-only EEPROM area
Enhanced ESD protection
More than 1 million Write cycles
More than 40-year data retention
Packages
ECOPACK

(RoHS compliant)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2 x 3 mm
www.st.com
Contents M95320, M95640, M95320-x, M95640-x
2/46
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 V
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 V
CC
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M95320, M95640, M95320-x, M95640-x Contents
3/46
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
List of tables M95320, M95640, M95320-x, M95640-x
4/46
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Operating conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29
Table 15. DC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 29
Table 16. DC characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. AC characteristics (M95320 and M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. AC characteristics (M95320-W and M95640-W, device grade 6). . . . . . . . . . . . . . . . . . . . 32
Table 19. AC characteristics (M95320-W and M95640-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33
Table 20. AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. AC characteristics (M95640-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22. SO8N 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 38
Table 23. TSSOP8 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 39
Table 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 26. Available M95320x products (package, voltage range, temperature grade) . . . . . . . . . . . 42
Table 27. Available M95640x products (package, voltage range, temperature grade) . . . . . . . . . . . 42
Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
M95320, M95640, M95320-x, M95640-x List of figures
5/46
List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Serial output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. SO8N 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38
Figure 19. TSSOP8 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Description M95320, M95640, M95320-x, M95640-x
6/46
1 Description
The M95320, M95320-W, M95320-R, M95640, M95640-W and M95640-R are electrically
erasable programmable memory (EEPROM) devices. They are accessed by a high-speed
SPI-compatible bus.
The M95320, M95320-W and M95320-R are 32 Kbit devices organized as 4096 x 8 bits.
The M95640, M95640-W and M95640-R are 64 Kbit devices organized as 8192 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Figure 1. Logic diagram
Figure 2. 8 pin package connections
1. See Package mechanical data section for package dimensions and how to identify pin-1.
AI01789C
S
V
CC
M95xxx
HOLD
V
SS
W
Q
C
D
D V
SS
C
HOLD Q
S V
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
M95320, M95640, M95320-x, M95640-x Description
7/46

Table 1. Signal names
Signal name Description
C Serial Clock
D Serial data input
Q Serial data output
S Chip Select
W Write Protect
HOLD Hold
V
CC
Supply voltage
V
SS
Ground
Signal description M95320, M95640, M95320-x, M95640-x
8/46
2 Signal description
During all operations, V
CC
must be held stable and within the specified valid range:
V
CC
(min) to V
CC
(max).
All of the input and output signals must be held high or low (according to voltages of V
IH
,
V
OH
, V
IL
or V
OL
, as specified in Table 13 to Table 16). These signals are described next.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Dont Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
M95320, M95640, M95320-x, M95640-x Signal description
9/46
2.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write operations.
2.7 V
SS
ground
V
SS
is the reference for the V
CC
supply voltage.
2.8 V
CC
supply voltage
Refer to Section 4.1: Supply voltage (V
CC
) on page 12.
Connecting to the SPI bus M95320, M95640, M95320-x, M95640-x
10/46
3 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 3. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI bus
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this will ensure that S and C do not become high at the
same time, and so, that the t
SHCH
requirement is met. The typical value of R is 100 k.
AI12836b
SPI bus master
SPI memory
device
SDO
SDI
SCK
C Q D
S
SPI memory
device
C Q D
S
SPI memory
device
C Q D
S
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W HOLD W HOLD W HOLD
R R R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
M95320, M95640, M95320-x, M95640-x Connecting to the SPI bus
11/46
3.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M95320, M95640, M95320-x, M95640-x
12/46
4 Operating features
4.1 Supply voltage (V
CC
)
4.1.1 Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage
within the specified [V
CC
(min), V
CC
(max)] range must be applied (see Table 8, Table 9 and
Table 10). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (t
W
). In
order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
CC
/V
SS
package
pins.
4.1.2 Device reset
In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
CC

reaches the POR threshold voltage (this threshold is lower than the minimum V
CC
operating
voltage defined in Table 8, Table 9 and Table 10).
When V
CC
passes over the POR threshold, the device is reset and in the following state:
in the Standby Power mode
deselected (note that when the device is deselected it is necessary to apply a falling
edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is
not executed)
Status register values:
the Write Enable Latch (WEL) bit is reset to 0
the Write In Progress (WIP) bit is reset to 0
the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
4.1.3 Power-up conditions
When the power supply is turned on, V
CC
continuously rises from V
SS
to V
CC
. During this
time, the Chip Select (S) line is not allowed to float but should follow the V
CC
voltage, it is
therefore recommended to connect the S line to V
CC
via a suitable pull-up resistor (see
Figure 3).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V
CC
rise time must not vary faster than 1 V/s.
Important note: When V
CC
passes over the POR threshold (see Section 4.1.2: Device
reset), the device is reset and enters the Standby Power mode. However, the device must
not be accessed until V
CC
reaches a valid and stable V
CC
voltage within the specified
[V
CC
(min), V
CC
(max)] ranges defined in Table 8, Table 9 and Table 10.
M95320, M95640, M95320-x, M95640-x Operating features
13/46
4.1.4 Power-down
At power-down (continuous decrease in V
CC
below the minimum V
CC
operating voltage
defined in Table 8, Table 9 and Table 10), the device must be:
deselected (Chip Select (S) should be allowed to follow the voltage applied on V
CC
)
in Standby Power mode (that is there should not be any internal write cycle in
progress).
4.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
CC
, as specified in Table 13 to Table 16.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to I
CC1
.
4.2.1 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Dont Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
Figure 5. Hold condition activation
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
Operating features M95320, M95640, M95320-x, M95640-x
14/46
4.3 Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.4 Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
The last bit of the instruction can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The next rising edge of Serial Clock (C) might (or might not) be the next bus
transaction for some other device on the SPI bus.

Table 2. Write-protected block size
Status Register bits
Protected block
Array addresses protected
BP1 BP0 64 Kbit devices 32 Kbit devices
0 0 none none none
0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh
1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh
1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh
M95320, M95640, M95320-x, M95640-x Memory organization
15/46
5 Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
AI01272C
HOLD
S
W Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
Y

D
e
c
o
d
e
r
C
D
Q
Size of the
Read only
EEPROM
area
Status
Register
Instructions M95320, M95640, M95320-x, M95640-x
16/46
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device
automatically deselects itself.

6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 7. Write Enable (WREN) sequence
Table 3. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
C
D
AI02281E
S
Q
2 1 3 4 5 6 7
High Impedance
0
Instruction
M95320, M95640, M95320-x, M95640-x Instructions
17/46
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
2 1 3 4 5 6 7
High Impedance
0
Instruction
Instructions M95320, M95640, M95320-x, M95640-x
18/46
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The Status Register format is shown in Table 4 and the status and control bits of the Status
Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
M95320, M95640, M95320-x, M95640-x Instructions
19/46
Figure 9. Read Status Register (RDSR) sequence
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven high, the self-timed Write Status Register cycle (whose duration is t
W
) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
C
D
S
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
0
AI02031E
Q 7 6 5 4 3 2 1 0
Status Register Out
High Impedance
MSB
7 6 5 4 3 2 1 0
Status Register Out
MSB
7
Instructions M95320, M95640, M95320-x, M95640-x
20/46

The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
low
or by driving Write Protect (W) low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Table 5. Protection modes
W
signal
SRWD
bit
Mode
Write protection of the
Status Register
Memory content
Protected area
(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
Unprotected area
(1)
1 0
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction has
set the WEL bit)
The values in the BP1 and
BP0 bits can be changed
Write Protected
Ready to accept
Write instructions
0 0
1 1
0 1
Hardware
Protected
(HPM)
Status Register is Hardware
write protected
The values in the BP1 and
BP0 bits cannot be changed
Write Protected
Ready to accept
Write instructions
M95320, M95640, M95320-x, M95640-x Instructions
21/46

Figure 10. Write Status Register (WRSR) sequence
Table 6. Address range bits
(1)
1. b15 to b13 are Dont Care on the 64 Kbit devices.
b15 to b12 are Dont Care on the 32 Kbit devices.
Device 32 Kbit devices 64 Kbit devices
Address bits A11-A0 A12-A0
C
D
AI02282D
S
Q
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15
High Impedance
Instruction Status
Register In
0
7 6 5 4 3 2 0 1
MSB
Instructions M95320, M95640, M95320-x, M95640-x
22/46
6.5 Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Dont Care.
C
D
AI01793D
S
Q
15
2 1 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27
14 13 3 2 1 0
28 29 30
7 6 5 4 3 1 7 0
High Impedance
Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
M95320, M95640, M95320-x, M95640-x Instructions
23/46
6.6 Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts from the rising edge of Chip Select (S), and continues for a period t
WC
(as
specified in Table 18 to Table 20), at the end of which the Write in Progress (WIP) bit is reset
to 0.
If, though, Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Dont Care.
C
D
AI01795D
S
Q
15
2 1 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27
14 13 3 2 1 0
28 29 30
High Impedance
Instruction 16-Bit Address
0
7 6 5 4 3 2 0 1
Data Byte
31
Instructions M95320, M95640, M95320-x, M95640-x
24/46
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Dont Care.
C
D
AI01796D
S
34 33 35 36 37 38 39 40 41 42 44 45 46 47 32
C
D
S
15
2 1 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27
14 13 3 2 1 0
28 29 30
Instruction 16-Bit Address
0
7 6 5 4 3 2 0 1
Data Byte 1
31
43
7 6 5 4 3 2 0 1
Data Byte 2
7 6 5 4 3 2 0 1
Data Byte 3
6 5 4 3 2 0 1
Data Byte N
M95320, M95640, M95320-x, M95640-x Power-up and delivery state
25/46
7 Power-up and delivery state
7.1 Power-up state
After Power-up, the device is in the following state:
Standby Power mode
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
not in the Hold condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Maximum rating M95320, M95640, M95320-x, M95640-x
26/46
8 Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.

Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
T
STG
Storage temperature 65 150 C
T
A
Ambient operating temperature 40 130 C
T
LEAD
Lead temperature during soldering See note
(1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
C
V
O
Output voltage 0.50 V
CC
+0.6 V
V
I
Input voltage 0.50 6.5 V
V
CC
Supply voltage 0.50 6.5 V
V
ESD
Electrostatic discharge voltage (human body
model)
(2)
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )
4000 4000 V
M95320, M95640, M95320-x, M95640-x DC and AC parameters
27/46
9 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.




Figure 14. AC measurement I/O waveform
Table 8. Operating conditions (M95320 and M95640)
Symbol Parameter Min. Max. Unit
V
CC
Supply voltage 4.5 5.5 V
T
A
Ambient operating temperature (device grade 3) 40 125 C
Table 9. Operating conditions (M95320-W and M95640-W)
Symbol Parameter Min. Max. Unit
V
CC
Supply voltage 2.5 5.5 V
T
A
Ambient operating temperature (device grade 6) 40 85 C
Ambient operating temperature (device grade 3) 40 125 C
Table 10. Operating conditions (M95320-R and M95640-R)
Symbol Parameter Min.
(1)
1. This product is under development. For more information, please contact your nearest ST sales office.
Max.
(1)
Unit
V
CC
Supply voltage 1.8 5.5 V
T
A
Ambient operating temperature 40 85 C
Table 11. AC measurement conditions
(1)
1. Output Hi-Z is defined as the point where data out is no longer driven.
Symbol Parameter Min. Typ. Max. Unit
C
L
Load capacitance 30 pF
Input rise and fall times 50 ns
Input pulse voltages 0.2V
CC
to 0.8V
CC
V
Input and output timing reference voltages 0.3V
CC
to 0.7V
CC
V
AI00825B
0.8V
CC
0.2V
CC
0.7V
CC
0.3V
CC
Input and Output
Timing Reference Levels
Input Levels
DC and AC parameters M95320, M95640, M95320-x, M95640-x
28/46


Table 12. Capacitance
(1)
1. Sampled only, not 100% tested, at T
A
=25C and a frequency of 5MHz.
Symbol Parameter Test condition Min. Max. Unit
C
OUT
Output capacitance (Q) V
OUT
= 0 V 8 pF
C
IN
Input capacitance (D) V
IN
= 0 V 8 pF
Input capacitance (other pins) V
IN
= 0 V 6 pF
Table 13. DC characteristics (M95320 and M95640, device grade 3)
Symbol Parameter Test condition Min. Max. Unit
I
LI
Input leakage current V
IN
= V
SS
or

V
CC
2 A
I
LO
Output leakage current S = V
CC
, V
OUT
= V
SS
or

V
CC
2 A
I
CC
Supply current
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 5V, Q = open
4 mA
I
CC1
Supply current
(Standby)
S = V
CC
, V
CC
= 5 V,
V
IN
= V
SS
or

V
CC
5 A
V
IL
Input low voltage 0.45 0.3 V
CC
V
V
IH
Input high voltage 0.7 V
CC
V
CC
+1 V
V
OL
(1)
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
Output low voltage I
OL
= 2 mA, V
CC
= 5 V 0.4 V
V
OH
(1)
Output high voltage I
OH
= 2 mA, V
CC
= 5 V 0.8 V
CC
V
M95320, M95640, M95320-x, M95640-x DC and AC parameters
29/46


Table 14. DC characteristics (M95320-W and M95640-W, device grade 6)
Symbol Parameter Test condition Min. Max. Unit
I
LI
Input leakage current V
IN
= V
SS
or

V
CC
2 A
I
LO
Output leakage current S = V
CC
, V
OUT
= V
SS
or

V
CC
2 A
I
CC
Supply current
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 2.5 V, Q = open
3 mA
C = 0.1V
CC
/0.9V
CC
at 10 MHz,
V
CC
= 3.0 V, Q = open
4 mA
I
CC1
Supply current
(Standby)
S = V
CC
, V
CC
= 2.5 V
V
IN
= V
SS
or

V
CC
1 A
S = V
CC
, V
CC
= 5.0 V
V
IN
= V
SS
or

V
CC
2 A
V
IL
Input low voltage 0.45 0.3V
CC
V
V
IH
Input high voltage 0.7V
CC
V
CC
+1 V
V
OL
Output low voltage
I
OL
= 1.5 mA, V
CC
= 2.5 V or
I
OL
= 2 mA, V
CC
= 5.5 V
0.4 V
V
OH
Output high voltage
I
OH
= 0.4 mA, V
CC
= 2.5 V or
I
OH
= 2 mA, V
CC
= 5.5 V
0.8V
CC
V
Table 15. DC characteristics (M95320-W and M95640-W, device grade 3)
Symbol Parameter Test condition Min. Max. Unit
I
LI
Input leakage current V
IN
= V
SS
or

V
CC
2 A
I
LO
Output leakage current S = V
CC
, V
OUT
= V
SS
or

V
CC
2 A
I
CC
Supply current
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 2.5 V, Q = open
3 mA
I
CC1
Supply current (Standby) S = V
CC
, V
CC
= 2.5 V, V
IN
= V
SS
or

V
CC
2 A
V
IL
Input low voltage 0.45 0.3V
CC
V
V
IH
Input high voltage 0.7V
CC
V
CC
+1 V
V
OL
Output low voltage I
OL
= 1.5 mA, V
CC
= 2.5 V 0.4 V
V
OH
Output high voltage I
OH
= 0.4 mA, V
CC
= 2.5 V 0.8V
CC
V
DC and AC parameters M95320, M95640, M95320-x, M95640-x
30/46

Table 16. DC characteristics (M95320-R and M95640-R)
Symbol Parameter Test condition Min. Max. Unit
I
LI
Input leakage current V
IN
= V
SS
or

V
CC
2 A
I
LO
Output leakage current
S = V
CC
, voltage applied on Q =
V
SS
or

V
CC
2 A
I
CCR
Supply current (Read)
V
CC
= 2.5 V, C = 0.1V
CC
/0.9V
CC

at maximum clock frequency,
Q = open
3 mA
V
CC
= 1.8 V, C = 0.1V
CC
/0.9V
CC
at maximum clock frequency,
Q = open
2 mA
I
CC1
Supply current (Standby)
V
CC
= 5 V, S = V
CC
,
V
IN
= V
SS
or

V
CC
2 A
V
CC
= 2.5 V, S = V
CC
,
V
IN
= V
SS
or

V
CC
1 A
V
CC
= 1.8 V, S = V
CC
,
V
IN
= V
SS
or

V
CC
1 A
V
IL
Input low voltage
1.8 V < V
CC
< 2.5 V 0.45 0.25V
CC
V
2.5 V < V
CC
< 5.5 V 0.45 0.3V
CC
V
V
IH
Input high voltage
1.8 V < V
CC
< 2.5 V 0.75V
CC
V
CC
+1 V
2.5 V < V
CC
< 5.5 V 0.7 V
CC
V
CC
+1 V
V
OL
Output low voltage
V
CC
= 2.5 V, I
OL
= 1.5 mA or
V
CC
= 5.5 V, I
OL
= 2 mA
0.2V
CC
V
V
CC
= 1.8 V, I
OL
= 0.15 mA 0.3 V
V
OH
Output high voltage
V
CC
= 2.5 V, I
OH
= 0.4 mA or
V
CC
= 5.5 V, I
OH
= 2 mA or
V
CC
= 1.8 V, I
OH
= 0.1 mA
0.8 V
CC
V
M95320, M95640, M95320-x, M95640-x DC and AC parameters
31/46

Table 17. AC characteristics (M95320 and M95640, device grade 3)
Test conditions specified in Table 10 and Table 11
Symbol Alt. Parameter Min. Max. Min.
(1)
Max.
(1)
Unit
f
C
f
SCK
Clock frequency D.C. 5 D.C. 10 MHz
t
SLCH
t
CSS1
S active setup time 90 30 ns
t
SHCH
t
CSS2
S not active setup time 90 30 ns
t
SHSL
t
CS
S deselect time 100 40 ns
t
CHSH
t
CSH
S active hold time 90 30 ns
t
CHSL
S not active hold time 90 30 ns
t
CH
(2)
t
CLH
Clock high time 90 42 ns
t
CL
(2)
t
CLL
Clock low time 90 40 ns
t
CLCH
(3)
t
RC
Clock rise time 1 2 s
t
CHCL
(3)
t
FC
Clock fall time 1 2 s
t
DVCH
t
DSU
Data in setup time 20 10 ns
t
CHDX
t
DH
Data in hold time 30 10 ns
t
HHCH
Clock low hold time after HOLD not active 70 30 ns
t
HLCH
Clock low hold time after HOLD active 40 30 ns
t
CLHL
Clock low set-up time before HOLD active 0 0 ns
t
CLHH
Clock low set-up time before HOLD not active 0 0 ns
t
SHQZ
(3)
t
DIS
Output disable time 100 40 ns
t
CLQV
t
V
Clock low to output valid 60 40 ns
t
CLQX
t
HO
Output hold time 0 0 ns
t
QLQH
(3)
t
RO
Output rise time 50 40 ns
t
QHQL
(3)
t
FO
Output fall time 50 40 ns
t
HHQV
t
LZ
HOLD high to output valid 50 40 ns
t
HLQZ
(3)
t
HZ
HOLD low to output high-Z 100 40 ns
t
W
t
WC
Write time 5 5 ms
1. These timings are offered with grade3 devices referenced with PB process letters only (see the last digits in the Part
numbering).
2. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
3. Value guaranteed by characterization, not 100% tested in production.
DC and AC parameters M95320, M95640, M95320-x, M95640-x
32/46

Table 18. AC characteristics (M95320-W and M95640-W, device grade 6)
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 10 MHz
t
SLCH
t
CSS1
S active setup time 30 ns
t
SHCH
t
CSS2
S not active setup time 30 ns
t
SHSL
t
CS
S deselect time 40 ns
t
CHSH
t
CSH
S active hold time 30 ns
t
CHSL
S not active hold time 30 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
t
CLH
Clock high time 42 ns
t
CL
(1)
t
CLL
Clock low time 40 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 2 s
t
CHCL
(2)
t
FC
Clock fall time 2 s
t
DVCH
t
DSU
Data in setup time 10 ns
t
CHDX
t
DH
Data in hold time 10 ns
t
HHCH
Clock low hold time after HOLD not active 30 ns
t
HLCH
Clock low hold time after HOLD active 30 ns
t
CLHL
Clock low set-up time before HOLD active 0 ns
t
CLHH
Clock low set-up time before HOLD not active 0 ns
t
SHQZ
(2)
t
DIS
Output disable time 40 ns
t
CLQV
t
V
Clock low to output valid 40 ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 40 ns
t
QHQL
(2)
t
FO
Output fall time 40 ns
t
HHQV
t
LZ
HOLD high to output valid 40 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 40 ns
t
W
t
WC
Write time 5 ms
M95320, M95640, M95320-x, M95640-x DC and AC parameters
33/46

Table 19. AC characteristics (M95320-W and M95640-W, device grade 3)
Test conditions specified in Table 11 and Table 9
Symbol Alt. Parameter
2.5 V to 5.5 V 3.0 V to 5.5 V
(1)
Unit
Min. Max. Min. Max.
f
C
f
SCK
Clock frequency D.C. 5 D.C. 10 MHz
t
SLCH
t
CSS1
S active setup time 90 30 ns
t
SHCH
t
CSS2
S not active setup time 90 30 ns
t
SHSL
t
CS
S deselect time 100 40 ns
t
CHSH
t
CSH
S active hold time 90 30 ns
t
CHSL
S not active hold time 90 30 ns
t
CH
(2)
t
CLH
Clock high time 90 42 ns
t
CL
(2)
t
CLL
Clock low time 90 40 ns
t
CLCH
(3)
t
RC
Clock rise time 1 2 s
t
CHCL
(3)
t
FC
Clock fall time 1 2 s
t
DVCH
t
DSU
Data in setup time 20 10 ns
t
CHDX
t
DH
Data in hold time 30 10 ns
t
HHCH
Clock low hold time after HOLD not active 70 30 ns
t
HLCH
Clock low hold time after HOLD active 40 30 ns
t
CLHL
Clock low set-up time before HOLD active 0 0 ns
t
CLHH
Clock low set-up time before HOLD not active 0 0 ns
t
SHQZ
(3)
t
DIS
Output disable time 100 40 ns
t
CLQV
t
V
Clock low to output valid 60 40 ns
t
CLQX
t
HO
Output hold time 0 0 ns
t
QLQH
(3)
t
RO
Output rise time 50 40 ns
t
QHQL
(3)
t
FO
Output fall time 50 40 ns
t
HHQV
t
LZ
HOLD high to output valid 50 40 ns
t
HLQZ
(3)
t
HZ
HOLD low to output high-Z 100 40 ns
t
W
t
WC
Write time 5 5 ms
1. These timings are offered with grade3 devices referenced with /PB process letters only (see the last digits in the Part
numbering).
2. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
3. Value guaranteed by characterization, not 100% tested in production.
DC and AC parameters M95320, M95640, M95320-x, M95640-x
34/46

Table 20. AC characteristics (M95320-R)
Test conditions specified in Table 11 and Table 10
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 5 MHz
t
SLCH
t
CSS1
S active setup time 60 ns
t
SHCH
t
CSS2
S not active setup time 60 ns
t
SHSL
t
CS
S deselect time 90 ns
t
CHSH
t
CSH
S active hold time 60 ns
t
CHSL
S not active hold time 60 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
t
CLH
Clock high time 90 ns
t
CL
(1)
t
CLL
Clock low time 90 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 2 s
t
CHCL
(2)
t
FC
Clock fall time 2 s
t
DVCH
t
DSU
Data in setup time 20 ns
t
CHDX
t
DH
Data in hold time 20 ns
t
HHCH
Clock low hold time after HOLD not active 60 ns
t
HLCH
Clock low hold time after HOLD active 60 ns
t
CLHL
Clock low set-up time before HOLD active 0 0
t
CLHH
Clock low set-up time before HOLD not active 0 0
t
SHQZ
(2)
t
DIS
Output disable time 80 ns
t
CLQV
t
V
Clock low to output valid 80 ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 80 ns
t
QHQL
(2)
t
FO
Output fall time 80 ns
t
HHQV
t
LZ
HOLD high to output valid 80 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 80 ns
t
W
t
WC
Write time 5 ms
M95320, M95640, M95320-x, M95640-x DC and AC parameters
35/46

Table 21. AC characteristics (M95640-R)
Test conditions specified in Table 10 and Table 11
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 2 MHz
t
SLCH
t
CSS1
S active setup time 150 ns
t
SHCH
t
CSS2
S not active setup time 150 ns
t
SHSL
t
CS
S deselect time 200 ns
t
CHSH
t
CSH
S active hold time 150 ns
t
CHSL
S not active hold time 150 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
t
CLH
Clock high time 200 ns
t
CL
(1)
t
CLL
Clock low time 200 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 2 s
t
CHCL
(2)
t
FC
Clock fall time 2 s
t
DVCH
t
DSU
Data in setup time 50 ns
t
CHDX
t
DH
Data in hold time 50 ns
t
HHCH
Clock low hold time after HOLD not active 150 ns
t
HLCH
Clock low hold time after HOLD active 150 ns
t
CLHL
Clock low set-up time before HOLD active 0 0
t
CLHH
Clock low set-up time before HOLD not active 0 0
t
SHQZ
(2)
t
DIS
Output disable time 200 ns
t
CLQV
t
V
Clock low to output valid 200 ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 200 ns
t
QHQL
(2)
t
FO
Output fall time 200 ns
t
HHQV
t
LZ
HOLD high to output valid 200 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 200 ns
t
W
t
WC
Write time 5 ms
DC and AC parameters M95320, M95640, M95320-x, M95640-x
36/46
Figure 15. Serial Input timing
Figure 16. Hold timing
C
D
AI01447d
S
MSB IN
Q
tDVCH
High impedance
LSB IN
tSLCH
tCHDX
tCLCH
tSHCH
tSHSL
tCHSH tCHSL tCH
tCL tCHCL
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQV tHLQZ
M95320, M95640, M95320-x, M95640-x DC and AC parameters
37/46
Figure 17. Serial output timing
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Package mechanical data M95320, M95640, M95320-x, M95640-x
38/46
10 Package mechanical data
In order to meet environmental requirements, ST offers the M95640 in ECOPACK

packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
Figure 18. SO8N 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.

Table 22. SO8N 8 lead plastic small outline, 150 mils body width, package
mechanical data
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ Min Max Typ Min Max
A 1.75 0.0689
A1 0.10 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.011 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.10 0.0039
D 4.90 4.80 5.00 0.1929 0.189 0.1969
E 6.00 5.80 6.20 0.2362 0.2283 0.2441
E1 3.90 3.80 4.00 0.1535 0.1496 0.1575
e 1.27 0.05 - -
h 0.25 0.50 0.0098 0.0197
k 0 8 0 8
L 0.40 1.27 0.0157 0.05
L1 1.04 0.0409
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M95320, M95640, M95320-x, M95640-x Package mechanical data
39/46
Figure 19. TSSOP8 8 lead thin shrink small outline, package outline
1. Drawing is not to scale.

Table 23. TSSOP8 8 lead thin shrink small outline, package mechanical data
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 0.0256
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
0 8 0 8
TSSOP8AM
1
8
CP
c
L
E E1
D
A2 A

e b
4
5
A1
L1
Package mechanical data M95320, M95640, M95320-x, M95640-x
40/46
Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.

Table 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
mechanical data
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ Min Max Typ Min Max
A 0.55 0.45 0.6 0.0217 0.0177 0.0236
A1 0.02 0 0.05 0.0008 0 0.002
b 0.25 0.2 0.3 0.0098 0.0079 0.0118
D 2 1.9 2.1 0.0787 0.0748 0.0827
D2 1.6 1.5 1.7 0.063 0.0591 0.0669
E 3 2.9 3.1 0.1181 0.1142 0.122
E2 0.2 0.1 0.3 0.0079 0.0039 0.0118
e 0.5 - - 0.0197 - -
L 0.45 0.4 0.5 0.0177 0.0157 0.0197
L1 0.15 0.0059
L3 0.3 0.0118
ddd
(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measurement.
0.08 0.08
D
E
UFDFPN-01
A
A1
ddd
L1
e b
D2
L
E2
L3
M95320, M95640, M95320-x, M95640-x Part numbering
41/46
11 Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 25. Ordering information scheme
Example: M95640 W MN 6 T P /P
Device type
M95 = SPI serial access EEPROM
Device function
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating voltage
blank = V
CC
= 4.5 to 5.5 V
W = V
CC
= 2.5 to 5.5 V
R = V
CC
= 1.8 to 5.5 V
Package
MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MB = MLP8 (2x3 mm)
Device grade
6 = Industrial temperature range, 40 to 85 C.
Device tested with standard test flow
3 = Device tested with high reliability certified flow
(1)
automotive temperature range
(40 to 125 C)
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
P or G = ECOPACK (RoHS compliant)
Process letter
(2)
2. The Process letter only concerns Grade-3 devices.
/P or /PB = DP26% Chartered
Part numbering M95320, M95640, M95320-x, M95640-x
42/46


Table 26. Available M95320x products (package, voltage range, temperature grade)
Package
M95320
4.5 V to 5.5 V
M95320-W
2.5 V to 5.5 V
M95320-R
1.8 V to 5.5 V
SO8 (MN) Range 3
Range 6
Range 3
Range 6
TSSOP (DW) -
Range 6
Range 3
Range 6
MLP 2 3 mm (MB) - - Range 6
Table 27. Available M95640x products (package, voltage range, temperature grade)
Package
M95640
4.5 V to 5.5 V
M95640-W
2.5 V to 5.5 V
M95640-R
1.8 V to 5.5 V
SO8 (MN) Range 3
Range 6
Range 3
Range 6
TSSOP (DW) -
Range 6
Range 3
Range 6
MLP 2 3 mm (MB) - - Range 6
M95320, M95640, M95320-x, M95640-x Revision history
43/46
12 Revision history

Table 28. Document revision history
Date Revision Changes
13-Jul-2000 1.2
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp
1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data
16-Mar-2001 1.3
Test condition added I
LI
and I
LO
, and specification of t
DLDH
and t
DHDL

removed.
t
CLCH
, t
CHCL
, t
DLDH
and t
DHDL
changed to 50ns for the -V range.
-V Voltage range changed to 2.7V to 3.6V throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
Bus Master and Memory Devices on the SPI bus illustration updated.
Package Mechanical data updated
19-Jul-2001 1.4 M95160 and M95080 devices removed to their own data sheet
06-Dec-2001 1.5
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.
08-Feb-2002 2.1
Announcement made of planned upgrade to 10MHz clock for the 5V, 40
to 85C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002 2.2
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write
cycles distinguished on front page, and in the DC and AC Characteristics
tables
26-Mar-2003 2.3
Process identification letter corrected in footnote to AC Characteristics
table for temp. range 3
26-Jun-2003 2.4
-S voltage range upgraded by removing it and inserting -R voltage range
in its place
15-Oct-2003 3.0 Table of contents, and Pb-free options added. V
IL
(min) improved to -0.45V
21-Nov-2003 3.1 V
I
(min) and V
O
(min) corrected (improved) to -0.45V
28-Jan-2004 4.0 TSSOP8 connections added to DIP and SO connections
24-May-2005 5.0
M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.
20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.
Description of Power On Reset: VCC Lock-Out Write Protect updated.
Product List summary table added. Absolute Maximum Ratings for
V
IO
(min) and V
CC
(min) improved. Soldering temperature information
clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. t
CHHL
(min) and t
CHHH
(min) is t
CH
for products under S
process. t
HHQX
corrected to t
HHQV
.
Figure 16: Hold timing updated.
Revision history M95320, M95640, M95320-x, M95640-x
44/46
07-Jul-2006 6
Document converted to new ST template.
Packages are ECOPACK compliant. PDIP package removed.
SO8N package specifications updated (see Table 22 and Figure 18).
M95640-S and M95320-S part numbers removed (DC and AC parameters
updated accordingly).
How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 4: SPI modes supported updated and Note 2 added. First three
paragraphs of Section 4: Operating features replaced by Section 4.1:
Supply voltage (V
CC
).
T
A
added to Table 7: Absolute maximum ratings. I
CC
and I
CC1
updated in
Table 13, Table 13, Table 14 and Table 16. V
OL
and V
OH
updated in
Table 14. I
CC
updated in Table 15. Data in Table 16 is no longer
preliminary.
t
CH
updated in Table 18. Table 21: AC characteristics (M95640-R) added.
Timing line of t
SHQZ
modified in Figure 17: Serial output timing.
Process letter added to Table 25: Ordering information scheme, Note 2
removed. Note 2 removed from Figure 2.
09-Oct-2007 7
JEDEC standard revision updated to D in Note 1 below Table 7: Absolute
maximum ratings.
Note 2 removed below Figure 3 and explanatory paragraph added.
Section 4.1: Supply voltage (V
CC
) updated. Table 6: Address range bits
corrected.
Products operating at V
CC
= 4.5 V to 5.5 V are no longer available in the
device grade 6 T
A
temperature range.
I
CC
and I
CC1
parameters modified in Table 14: DC characteristics
(M95320-W and M95640-W, device grade 6).
Maximum frequency for M95640-W and M95320-W upgraded from 5 MHz
to 10 MHz in the device grade 6 T
A
temperature range (Table 18: AC
characteristics (M95320-W and M95640-W, device grade 6) modified
accordingly).
Table 27: Available M95640x products (package, voltage range,
temperature grade): /PB process letter added, /P process letter removed.
Blank option removed below Plating technology in Table 25: Ordering
information scheme.
Table 26 and Table 27 added. Small text changes.
Table 24: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead,
package mechanical data updated.
Package mechanical inch values calculated from mm and rounded to 4
decimal digits in Section 10: Package mechanical data.
17-Dec-2007 8
Section 2.7: V
SS
ground added.
Device behavior when V
CC
passes over the POR threshold updated (see
Section 4.1.2: Device reset and Section 4.1.4: Power-down).
V
IL
and V
IH
modified in Table 16: DC characteristics (M95320-R and
M95640-R).
t
W
, write time, modified in Table 20: AC characteristics (M95320-R) and
Table 21: AC characteristics (M95640-R). Small text changes.
Table 28. Document revision history (continued)
Date Revision Changes
M95320, M95640, M95320-x, M95640-x Revision history
45/46
20-Mar-2008 9
Section 4.1: Supply voltage (V
CC
) updated.
10 MHz frequencies added to Table 17: AC characteristics (M95320 and
M95640, device grade 3) and Table 19: AC characteristics (M95320-W
and M95640-W, device grade 3).
Small text changes.
23-Jun-2008 10
Section 4.1: Supply voltage (V
CC
) updated.
Table 16: DC characteristics (M95320-R and M95640-R) modified.
Figure 15: Serial Input timing, Figure 16: Hold timing and Figure 17: Serial
output timing modified.
Table 28. Document revision history (continued)
Date Revision Changes
M95320, M95640, M95320-x, M95640-x
46/46


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