6/20/2014 Introduction to Verilog Abstraction Levels (Theory) : FPGA & Embedded Systems Lab : Computer Science & Engineering

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Introduction to Verilog Abstraction Levels
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Aim Pre Test Theory Procedure and Demo Simulation Post Test Reference People Feedback

Verilog HDL:

Verilog is both the structural and functional language. Internals of each module can be defined at five levels of abstraction, depending on the
need of the design. The module behaves identically with the external environment irrespectively of the level of abstraction at which the module is
described. Internals of the module are hidden from the environment. Thus, the level of abstraction to describe the module can be changed
without any change in the environment.
The levels are described below:

1. Switch (Transistor) Level
The lowest level of abstraction for a digital HDL would be the switch level, which refers to the ability to describe the circuit as a netlist of
transistor switches. A more detailed modeling scheme that can catch some additional electrical problems when transistors are used in this
way. Now, little-used because circuits generally arent built this way.

Switch Primitives:

Unidirectional Primitives Bidirectional Primitives
cmos nmos pmos pullup rcoms rnmos rpmos pulldown tran tranif0 tranif1 rtran rtranif0 rtranif1

Switch Instantiation:

Unidirectional Switchs Bidirectional Switchs
[r]nmos n1 (drain,source,gate);
[r]pmos p1 (drain,source,gate);
[r]cmos c1(drain, source, ngate, pgate) ;
[r]tran t1 (inout1,inout2);
[r]tranif0 t2 (data1, data2, control);
[r]tranif1 t3 (data1, data2, control);

Example 1: CMOS Inverter

module cmos_inv (In, Out); // module declaration
input In;
output Out;
supply1 vdd;
supply0 gnd;
pmos p1(Out, vdd, In); // pmos instantiation
nmos n1(Out, gnd, In); // nmoc instantiation
endmodule
Fig. CMOS Inverter Verilog code


2. Gate (Structural) Level

A slightly higher level of abstraction would be the gate level, which refers to the ability to describe the circuit as a netlist of primitive logic gates
and functions. The gates have one scalar output and multiple scalar inputs.

Gate Primitives:

Gate Type Description Instantiation Syntax
and N-input AND gate and a1(out,in1,in2) ;
nand N-input NAND gate nand a2(out,in1,in2) ;
or N-input OR gate or a3(out,in1,in2) ;
nor N-input NOR gate nor a4(out,in1,in2) ;
.....
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nor N-input NOR gate nor a4(out,in1,in2) ;
xor N-input XOR gate xor x1(out,in1,in2) ;
xnor N-input XNOR gate xnor x2(out,in1,in2) ;
not 1-input NOT gate not g1 (out , in) ;
buf 1-input & N-output BUF gate buf b1_2 (out1,out2, in) ;
bufif1 1-input,1-output,1-control BUF gate bufif1 b0(out,in,control) ;
bufif0 1-input,1-output,1-control BUF gate bufif0 b1(out,in,control) ;
notif1 1-input,1-output,1-control NOT gate notif1 b2(out,in,control) ;
notif0 1-input,1-output,1-control NOT gate notif0 b3(out,in,control) ;

Example 2: 2-1 Multiplexer

We will design 2-1 Multiplexer with one select signal. S0 is a selected signal wire. The I/O diagram and truth table for the Multiplexer are
shown below.

module mux2_1 (o1,in1,in2,S0); //module
output o1;
input in1,in2,S0;
and a1 (Q, in1, S0); //and instantiation
not n1 (P,S0); // not instantiation
and a2 (R, in2, P); // and instantiation
or o1 (o1, Q, R); // or instantiation
endmodule

Fig. Multiplexer 2:1 Verilog Code

3. Data Flow Level

For small circuits, the gate level modeling approach works very well because the number of gates is limited and designer can instantiate and
connects every gate individually. However in complex design the number of gates is very large. Thus implementing the function at a level higher
than gate level is good choice. Dataflow modeling has become a popular design approach as logic synthesis tools have become sophisticated.
This approach allows the designer to concentrate on optimizing the circuit in terms of data flow.

I. Continuous Assignments:
It is the most basic statement in dateflow level, used to drive a value onto a net. It replaces gates in the description of the circuit and describes
the circuit at a higher level of abstraction.
A continuous assignment statement starts with the keyword assign.
Syntax : assign [ delay ] net = expression;
Example : assign sum = a ^ b;

II. Implicit Continuous Assignment:
Instead of declaring a net and then writing a continuous assignment on the net. Verilog provides a shortcut by which a continuous assignment
can be placed on a net when it is declared. There can be only one implicit declaration assignment per net because a net is declared only once.
Example: wire out= in1 & in2;

Example 3: 2-4 Line Decoder

module deco2_4 (EN, A0, A1, D0, D1, D2, D3);//module
input EN, A0, A1;
output D0, D1, D2, D3;
assign D0 =(EN & ~A1 & ~A0);
assign D1 =(EN & ~A1 & A0);
assign D2 =(EN & A1 & ~A0);
assign D3 =(EN & A1 & A0);
endmodule
Fig. Line Decoder (2-4) Verilog Code

4. Functional and Algorithmic Level (Behavioral Modeling)

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Verilog provides the designer the ability to describe the design functionality in an algorithmic manner. In other words the designer describes the
behavior of the circuit. The abstraction in this modeling is as simple as writing the logic in C language. Verilog behavioral models contain
procedural statements that control the simulation and manipulate variables of the data types previously described. The activity starts at the
control constructs initial and always. Each initial statement and each always statement starts a separate activity flow. All of the activity flows are
concurrent, allowing the user to model the inherent concurrence of hardware.

Procedural assignments:
Procedural assignments are used for updating reg, integer, time, real, realtime, and memory data types.
The left hand side of a procedural assignment could be:
reg, integer, real, realtime, or time data type.
Bit-select of a reg, integer, or time data type, rest of the bits are untouched
Part-select of a reg, integer, or time data type, rest of the bits are untouched.
Memory word.
Syntax: wire out= in1 & in2;

I. Blocking assignments:
Blocking assignment statements are executed in the order they are specified in a sequential block.
Example: initial
begin
a = 1 ;
b = #35 ;
end

II. Non-blocking assignments:
The nonblocking assignment allows assignment scheduling without blocking the procedural flow.
Syntax: initial
begin
a<=1 ;
b<= # 35 ;
end

Conditional (if-else) statement:
The condition (if-else) statement is used to make a decision whether a statement is executed or not. The keywords if and else are used to
make conditional statement.
Syntax: if (condition_1)
statement 1;
else if (condition_2)
begin
statement 2;
end
else
statement 3;

Case statement:
The case statement is a multi-way decision statement that tests whether an expression matches one of the expressions and branches
accordingly. Keywords case and endcase are used to make a case statement. The case statement syntax is as follows.
Syntax: case (expression)
case 1: statement_1;
case 2: statement_2;
case 3: statement_3;
default: default_statement;
endcase

Loop statement:
There are four types of looping statements in Verilog:
for loop
while
forever
Repeat


Syntax:
for loop while loop forever loop Repeat loop
initial
begin
a = 20;
for (i =1;
i<25;i=i+1)
begin
a=a+1;
end

initial
begin
a = 20;
i = 0;
while (i <
a)
begin
i = i +
1;
a = a -
1;
end

initial
begin
clk = 0;
forever #5 clk =
~clk;
end

initial
begin
x = 0;
repeat( 16 )
begin
#2 $display("y=
", y);
x = x + 1;
end



Example 4: 8-bit Binary Counter

6/20/2014 Introduction to Verilog Abstraction Levels (Theory) : FPGA & Embedded Systems Lab : Computer Science & Engineering : COE PUNE Virtual Lab
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module half_add (S, C, A, B);
input A, B;
output S, C;
reg S, C;
always @ (A or B)
begin
S = A ^B;
C = A & B;
end
Fig. Binary counter(8-bit) Verilog Code

5. Register transfer Level (RTL Modelling)

Describes a system by the flow of data and controls signals within and between functional blocks. It's a behavioral design concept in which you
make HDL models of registered circuits and how signals interact between them such as memories, flip flops, latches, shift registers, and so
on. RTL is a combination of Behavioral and Data flow modeling which should be synthesizable. RTL description is more complex and less
technology dependent than behavior hardware description.

Example 5: 2-1 Multiplexer


module mux2to1 (in1,in2, S0, o1);
input in1,in2,S0;
output o1;
always_comb begin
case (sel)
1b0 :o1 = in1;
1b1 : o1 = in2;
default : o1 = 1bx;
endcase
end
Fig. Multiplexer 2:1 Verilog Code

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