Computational task can be classified into 2 types:

1)Compute bound 2)I/O bound

Compute bound:
If the no. of operations is larger than that of input and output elements.
I/O bound:
no(operations) < no(i/o elements)

In​ I/O bound task​ any attempt to speed up can come from increase in memory bandwidth.
Speeding up a compute bound task can be accomplished by systolic approach.

Systolic array based matrix multiplication:

1)​https://www.youtube.com/watch?v=cmy7LBaWuZ8
2)​http://web.cecs.pdx.edu/~mperkows/temp/May22/0020.Matrix-multiplication-systolic.pdf
3)​http://ecelabs.njit.edu/ece459/lab3_helpnotes.php
4)​http://ecelabs.njit.edu/ece459/lab3.php
VERILOG SOURCE:​https://www.hdlworks.com/hdl_corner/verilog_ref/index.html

VERILOG REVIEW
Verilog Example:(From INTEL)
1) https://www.intel.com/content/www/us/en/programmable/support/support-resourc
es/design-examples/design-software/verilog.html#using
$test$plusargs ,$value$plusargs

This is a system function supported in Verilog (and SystemVerilog) to read a command

line argument and have conditional code implementation accordingly
In Verilog-1995, an integer number with a base specified was
always treated as an unsigned value
2.5 Numbers
Constant numbers can be specified as integer constants (defined in 2.5.1) or real constants.
2.5.1 Integer constants
Integer constants can be specified in decimal, hexadecimal, octal, or binary format.
There are two forms to express integer constants.

The first form is a simple decimal number, which shall be specified as a sequence of digits 0
through 9, optionally starting with a plus or minus unary operator.

The second form specifies a size constant, which shall be composed of up to three tokens—an
optional size constant, a single quote followed by a base format character, and the digits
representing the value of the number.

Simple decimal numbers without the size and the base format shall be treated as signed
integers​, whereas the numbers specified with the base format shall be treated as signed
integers if the s designator is included or as unsigned integers if the base format only is used.
The s designator does not affect the bit pattern specified,only its interpretation.

A plus or minus operator preceding the size constant is a unary plus or minus operator. ​A plus
or minus operator between the base format and the number is an illegal syntax.

Negative numbers shall be represented in 2 s complement form.

NOTES:
1) Sized negative constant numbers and sized signed constant numbers are
sign-extended when assigned to a reg data type, regardless of whether the reg itself is
signed or not.
CONFUSED HOW TO HANDLE NEGATIVE NOS.
????
Continuous assignment:(Dataflow modelling)
Continuous assignments are not the same as procedural continuous assignments. Continuous
assignments are declared outside of procedural blocks. They automatically become active at time zero,
and are evaluated concurrently with procedural blocks, module instances, and primitive instances.

Structured Procedure :
There are 2 structured procedure statements in verilog ​1) Always 2)Initial
All other behavioural statements can appear only within these 2 statements.
Each Initial and always statement represent a separate activity flow in verilog.
Each activity flow start at simulation time 0. Activity flow run in parallel in verilog rather than in
sequence.
Initial statement:
For this we use = operator.

NOTE:
CONDITIONAL STATEMENT:
CASE STATEMENT:
We can see in if-else-if(type-3 conditional statement theree are many alternatives out of which
only 1 is true and gets executed. This can be achieved using case statement.
MEMORY ADDRESSING CONCEPTS
Generate block & Hierarchy names
Handling unconnected port:
When connecting ports by name, an unconnected port can be indicated either by omitting it in
the port list, or by providing no expression in the parentheses [i.e., .port_name ()].
E.g.
ff2(.qbar(out2), .clear(in2), .preset(in1), .q());it is legal here q is unconnected/floating port.
// ff3(.q(out3),.clear(in1),,,); ​is illegal
PORT DATA TYPES:

Inout Port:
A ​OE​ controlled bidirectional pin in Verilog HDL. The value of ​OE​ determines whether
bidir​ is an input, feeding in ​inp​, or a tri-state, driving out the value ​b​.
bidir<= (​OE​)?dataout : 1’bz; (Code for inout port) It synthesizes to tristate gate with
dataout being input signal ,​OE being control signal and bidir being
Output signal.
RTL NOTES:
#########(VERILOG)
Blocking assignment statements are executed sequentially in the order they are listed
in a block of statements. Nonblocking assignments are executed concurrently by evaluating
the set of expressions on the right-hand side of the list of statements; they do not
make assignments to their left-hand sides until all of the expressions are evaluated.
use blocking assignments in combinational logic. Use nonblocking assignments when modeling
concurrent execution (e.g., edge-sensitive behavior such as synchronous, concurrent register
transfers) and when modeling latched behavior

######verilog
Primitives such as​ and​ are n -input primitives. They can have any number of scalar inputs
(e.g., a three-input and primitive). The buf and not primitives are n -output primitives.
A single input can drive multiple output lines distinguished by their identifiers.
output [0: 3] D;
wire [7: 0] SUM;
The first statement declares an output vector D with four bits, 0 through 3. The second
declares a wire vector SUM with eight bits numbered 7 through 0. ( Note : The first (leftmost)
number (array index) listed is always the most significant bit of the vector.)
SUM[2: 0] specifies the three least significant bits of vector SUM .
net is not a keyword, but represents a class of data types, such as ​wire , wor, wand, tri,
supply1, and supply0.
Nets ​supply1​ and ​supply0​ represent power supply and ground, respectively. They are used to
hardwire an input of a device to either 1 or 0.
The procedural assignment statements inside the always block are executed every time
there is a change in any of the variables listed after the @ symbol.

$display —display a one-time value of variables or strings with an end-of-line return,

$write —same as $display , but without going to next line,
$monitor —display variables whenever a value changes during a simulation run,

E.gs:
$display ("%d %b %b", C, A, B);
NOTE:
IF statement without else part, Case statement without all cases/ default statement ,
Unspecified Conditional operator (? : ) is synthesized to latches which is not desired in
design bcz of power and timing issues.

​ Interview Questions:

1)Function ,Task concept

2)Difference between dataflow and Behavioural modelling
3)Uses,Difference of Blocking and Non-blocking assignment
4)Is reg data type synthesize to HW register?
5)Writing 32 inputs of a mux in compact form
6)Vector ,array in Verilog
7)Handling Negative number in Verilog,1’s ,2.s complement their difference which is better?
8)What is full case and parallel case in verilog
9)Verilog code for swapping of 2 variable by using both blocking and non blocking