AC

-D
,C
TS
Verilog HDL
AC

Introduction
©

Aug 2010 © Ganesh Khedkar 1

Brief History of Verilog HDL
• Originated in 1980, at Automation Integrated Design
Systems, well known as Gateway Design Automation, for

AC
verification.
• Verilog is invented as “Simulation Language”.

-D
• Designed by Phil Moorby and Prabhu Goel.
• 1989 Cadence Design System acquired Gateway Design

,C
Automation.
• 1990 Verilog became open language.
TS
• Verilog became “IEEE Standard 1364” in 1995.
• The revision of the language is done in 2001 and 2005.
AC
• The Verilog IEEE 1364-2001 is in use.
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Aug 2010 © Ganesh Khedkar 2

Feature of Verilog
• Verilog is case sensitive.
• Most of the syntax is adopted from “C”. [ BUT it may not

AC
work like it works in “C”]
• Verilog simulator has to manage less data compare to

-D
VHDL simulator.
• Verilog can be used to model a digital system as

,C
algorithmic, RTL, gate and switch level.
• Verilog can’t be used for system level modeling.
TS
• Advanced simulation features like TEXTIO, PLI simpler.
• User can’t define anything.
AC
• There is no concept of package.
©

Aug 2010 © Ganesh Khedkar 3

Identifiers
• Identifiers are the names Verilog uses for the objects in a
design.

AC
• The basic rule are as follows,

-D
– May contain letters (a-z, A-Z), digit (0-9), _ and $.

,C
– Must start with letters or underscore.
TS
– Are case sensitive.
AC
– Other printable ASCII character may be used in an
escaped identifier.
©

– shiftreg_a, _bus3, \bus+index, \***error_condition***

Aug 2010 © Ganesh Khedkar 4

Numbers
• Default base is 10.

AC
• Syntax
Number_of_bits’radix value

-D
• Radix specifier

,C
– ‘b or ‘B : Binary
– ‘d or ‘D : Decimal
TS
– ‘o or ‘O : Octal
– ‘h or ‘H : Hexadecimal
AC

• Signed Numbers
– (s/S) before radix-specifier will be interpreted as 2C.
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Aug 2010 © Ganesh Khedkar 5

Number Examples
• 659 // is a decimal number
• ‘h837F //is a hexadecimal number

AC
• 3’b011 // is a 3-bit binary number
• 5’O473 // is a 5-bit octal number

-D
• 8’d -6 // is an illegal syntax

,C
• -8’d6 // defines the 2’s complement of 6, (8-bit)
• 4’shf //denotes the 4-bit number “1111”, to be
TS
//interpreted as 2C number or “-1”. This is
//equivalent to -4’h1
AC
• -4’sd15 //equivalent to –(-4’d1), “0001”
• 11’h0z3 //0000zzzz0011
• 32’h12ab_f001
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Aug 2010 © Ganesh Khedkar 6

Module
• In Verilog, design has only one design unit. It is known
as module.

AC
• Module declaration:

-D
module <module_name>(<name_of_ports>);

,C
//definition of ports;
//definition of data objects;
TS
//behavioral or RTL code;
endmodule //no semicolon
AC
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Aug 2010 © Ganesh Khedkar 7

Module (contd.)
• It describes both designer interface to other designs in
the system environment; and its functional composition.

AC
• All the declaration used within a model must be declared

-D
locally within the module.

,C
• Functional composition is a description of structure
using primitives, data-flow assignment and sequential
constructs. TS
AC
• A module can be instantiated inside another module as
component.
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Aug 2010 © Ganesh Khedkar 8

Types of ports
• Verilog supports three types of I/O connections.

AC
– input: ports defined as input are input ports

-D
– output: these ports can be read back internally.

,C
– inout: bi-directional ports defined as inout ports. Inout
ports can never be updated in procedural assignment
statement. TS
AC
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Aug 2010 © Ganesh Khedkar 9

Nets
• Represents physical connection between devices.
• Some time also called as wire.

AC
• The default net type is plain wire with no special property.
• Ex:
– wire, tri : default net type, plain wire

-D
– supply0, supply1 : power and ground rails
– wor,trior : multiple drivers that are Wire-ORed

,C
– wand, triand : multiple drivers that are Wire-ANDed
– trireg : nets with capacitive storage
– tri1, tri0 TS : pull up or down when not driven
AC
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Aug 2010 © Ganesh Khedkar 10

Declaring Nets
• Syntax
– net_type [range] [delay] list_of_variables;

AC
• ex:

-D
– wand w; // A scalar net of type “wand”.

,C
– tri [15:0] busa; // a 16-bit three-state bus;
TS
– wire [0:31] w1,w2; // Two 32 bit wires with msb= bit 0
AC
– wire #5 addr_sel; //a scalar wire with delay

– wire [7:0] mux [15 : 0]; // 2D wire

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Aug 2010 © Ganesh Khedkar 11

Registers & its type
• A register maintains its value between discrete assignments.

AC
• Assignments to reg’s is done in procedural block.

• Used to model synchronous hardware and to apply stimulus

-D
in the testbench.

,C
• Verilog language offers four type of register data type:
– integer : signed 32 bit integer variable.
TS
– real : Signed double precision floating-point variable
– reg : Unsigned storage of varying bit width
AC
– time : Unsigned 64 bit integer variable

• Do not imply structural storage elements as implemented in

©

Hardware.

Aug 2010 © Ganesh Khedkar 12

Parameter
• A parameter is untyped constant.

AC
• Can be used as substitute for a constant or literal.

-D
• Can be changed on instance by instance basis.

,C
• ex:
parameter cycle = 20;
TS
parameter prop_del = 3;
parameter setup = cycle/2 – prop_del;
AC
parameter file = “../src/data_input.txt”;
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Aug 2010 © Ganesh Khedkar 13

Choosing Correct Datatype
• Follow these rules when choosing between net and
register data type:

AC
– An input or inout port must be a net.

– An output port can be a register data type.

-D
,C
– A signal assigned a value in a procedural block must
be a register data type.
TS
AC
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Aug 2010 © Ganesh Khedkar 14

Continuous Assignment
• Used to model combinational circuit.
– Syntax :

AC
• assign [drive_strength] [delay] list_of_assignments;

-D
• LHS is any net type.
• Automatically get evaluated when any of the operands

,C
change.
• Can not occur in sequential block.
TS
• Can make explicit or implicit continuous assignment.
– Ex:
AC
wire ab;
assign ab = a & b; //explicit
wire in_ = ~in; //implicit
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Aug 2010 © Ganesh Khedkar 15

Ex
Module
assigns(o1,o2,SUM,eq,AND,OR,even,odd,one,COUT,a,b,CIN,in,A,B);

AC
output [7:0] o1,o2;
output [31:0] SUM;
output eq,AND,OR,even,odd,one,COUT;

-D
input a,b,CIN;
input [7:0] in;
input [31:0] A,B;

,C
wire [7:0] #3 o2;//no assignments yet, but a delay
TS
tri AND = a&b,OR=a|b; //two assignments
wire #5 eq = (a ==b); //implicit, with delay
wire (weak1,strong0) [7:0] #(3,5,2) o1 = in; // strength and delays
AC

assign o2[7:4]=in[3:0],o2[3:0]=in[7:4];//part-select
tri #5 even = ^in, odd = ~^in;// delay, two assignments
wire one = 1'b1;//constant assignment
©

assign {COUT,SUM}= A+B+CIN;// assignment to a concatenation

endmodule
Aug 2010 © Ganesh Khedkar 16
Primitives
• Verilog has a set of twenty-six built in primitives

AC
• Organized as follows
– Logic Gates : and, or, xor, xnor, nand, nor

-D
– Buffers : buf, not, pullup, pulldown, etc.
– Transistor : nmos, pmos, cmos etc.

,C
• First port in built in primitive is output.
TS
• The same primitive can be used for more number of
AC
inputs.

• The few primitives can have more than one output.

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Aug 2010 © Ganesh Khedkar 17

Simple program for 2:1 mux

AC
-D
module mux(OUT, A, B, SEL);

,C
output OUT;
input A,B,SEL;
TS
not I1 (sel_n, SEL);
and I2 (sel_a, A, SEL);
AC

and I3 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);
©

endmodule

Aug 2010 © Ganesh Khedkar 18

2:1 mux (New ANSI C Style, 2001)
module mux(output OUT,
input A, B, SEL);

AC
not I1 (sel_n, SEL);

-D
and I2 (sel_a, A, SEL);
and I3 (sel_b, sel_n, B);

,C
or I4 (OUT, sel_a, sel_b);

endmodule
TS
AC
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Aug 2010 © Ganesh Khedkar 19

Primitive declaration
• Syntax
– gate_type [drive_strength] [delay] [instance_name]

AC
[terminal,.. ];

-D
• Ex : notif1 #3 n1 (inv_out, in1, cntr);

,C
• Rise, fall and turnoff delay
• notif1 #(3, 4, 5) n1 (inv_out, in1, cntr);
TS
• minimum, typical, maximum delay
AC
• notif1 #(3:4:5, 8:10:12, 15:16:17) n1 (inv_out, in1, cntr);
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Aug 2010 © Ganesh Khedkar 20

Component Instantiation
• Syntax
– name_of_component label (assignment of ports);

AC
• Assignment of ports is done by

-D
– Positional mapping
– Naming mapping

,C
• Syntax
.port_name (net_to_be_connected)
TS
AC
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Aug 2010 © Ganesh Khedkar 21

2 bit mux

module mux2(OUT, A, B, SEL);

AC
output [1:0] OUT;

-D
input [1:0] A,B;
input SEL;

,C
mux hi (OUT[1], A[1], B[1], SEL);
TS
mux lo (OUT[0], A[0], B[0], SEL);
AC
endmodule
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Aug 2010 © Ganesh Khedkar 22

Example of naming mapping

module mux2(output [1:0] OUT,

AC
input [1:0] A,B,
input SEL);

-D
mux hi (.OUT(OUT[1]), .A(A[1]), .B(B[1]), .SEL(SEL));

,C
mux lo (.OUT(OUT[0]), .A(A[0]), .B(B[0]), .SEL(SEL));
TS
endmodule
AC
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Aug 2010 © Ganesh Khedkar 23

2 bit mux using Array of instances

AC
module mux2(output [1:0] OUT,
input [1:0] A,B,

-D
input SEL);

,C
mux m1[1:0] (.OUT(OUT), .A(A), .B(B), .SEL(SEL));

endmodule
TS
AC
©

Aug 2010 © Ganesh Khedkar 24

Assignment

• Write the code for single bit full adder and extend it up to

AC
4 bit using the idea of component instantiation.

-D
• Write the program for D latch using gate primitive.

,C
TS
AC
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Aug 2010 © Ganesh Khedkar 25

Operators
• Arithmetic operator
+, -, *, /, % (mod)

AC
• Equality operators

-D
== (Logical equality), === (case equality), <=, >=, <, >

,C
• Logical operator
!(not), &&(and), ||(or)
TS
• Logical bitwise operator OR Unary Reduction operators
AC
|, &, ^, ~, ~^
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Aug 2010 © Ganesh Khedkar 26

Operators
• Shift operator
<< (shift left), >> (shift right), >>>(Signed shift

AC
Right),<<<(Signed Shift Left)

-D
• Concatenation
{ } // e.g.: B[1:0] = {B1, B0};

,C
• Conditional operator
TS
<condition>? <true>:<false>
AC
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Aug 2010 © Ganesh Khedkar 27

Sizing and signing
reg [3:0] a, b;
reg [7:0] c;

AC
...

-D
a = -1; //1111

,C
b = 8; //1000
c = 8; //00001000
c = c + a;
TS
//00010111
b = b + a; //0111
AC
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Aug 2010 © Ganesh Khedkar 28

Concatenation Operation
• Ex:
reg [7:0] a, b, c, d, y;

AC
a = 8’b00000011;

-D
b = 8’b00000100;
c = 8’b00011000;

,C
d = 8’b11100000;
y = {a[1:0], b[2], c[4:3], d[7:5]};
TS
• You can concatenate an unlimited number of operands,
AC
separating with comma.

• Don’t do n[7:0] = {3’b011, ‘b0};

©

• Do this n[7:0] = {3’b011, 5‘b0}; OR n[7:0] = {3’b011, {5{1‘b0}}};

Aug 2010 © Ganesh Khedkar 29
Negation Operators
• The logical negation operation (!) produces a 0, 1, or x
scalar value.

AC
• The bitwise negation operator (~) inverts each bit of the

-D
operands.

,C
• !4’b0100 //0
• !4’b0000 //1
• !4’b00z0 //x
TS
• !4’bx000 //x
AC
• ~4’b01zx //10xx
©

Aug 2010 © Ganesh Khedkar 30

Unary Reduction Operators
• The Unary reduction operators (&, |, ^, ^~) produces 0,
1, or X.

AC
• They operates across all bits of a vector.

-D
• Ex
&4’b1110 //0

,C
&4’b1111 //1

|4’b0000 //0
TS
|4’b1000 //1
AC

^4’b1110 //1
©

^~4’b1110 //0

Aug 2010 © Ganesh Khedkar 31

Bit-Wise Operator
• The bit-wise operators (&, |, ^, ^~) operate on each
individual bit of a vector.

AC
• Ex
4’b01zx & 4’b0000 //0000

-D
4’b01zx & 4’b1100 //0100

,C
4’b01zx | 4’b1111 //1111
4’b01zx | 4’b0011 //0111
TS
4’b01zx ^ 4’b1111 //10xx
AC
4’b01zx ^~ 4’b0000 //10xx
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Aug 2010 © Ganesh Khedkar 32

Shift Operators
• The shift operators (<<,>>) shift the left or right the
number of times given by the right operand.

AC
• Ex

-D
8’b00011000 << 2 //01100000

,C
8’b00011000 >> 2 //00000110

8’b00011000 << -2
TS //00000000
AC
8’b00011000 << 1’bx //xxxxxxxx
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Aug 2010 © Ganesh Khedkar 33

Equality Operators
• Logical equality operator

AC
== 0 1 Z X
0 1 0 X X
1 0 1 X X

-D
Z X X X X

,C
X X X X X

TS
• Case equality operator
=== 0 1 Z X
AC

0 1 0 0 0
1 0 1 0 0
©

Z 0 0 1 0
X 0 0 0 1

Aug 2010 © Ganesh Khedkar 34

Conditional Operator

module (in1, in2,op, sel);

AC
input in1, in2,sel;
output op;

-D
assign op = sel ? in1 : in2 ;

,C
endmodule
TS
AC
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Aug 2010 © Ganesh Khedkar 35

Operator Precedence

Type of Operator Symbols

AC
Concatenation & replication { } {{ }}
Unary ! ~ & ^ ^~

-D
Arithmetic * / %

,C
+ -
Logical Shift << >>
Relational
TS < <= > >=
Equality == != === !==
AC

Binary Bit-wise & ^ ^~ |

Binary Logical && ||
©

Conditional ?:

Aug 2010 © Ganesh Khedkar 36

Lab assignment
• Design 4:16 decoder using shift operator.

AC
• Design 8:3 priority encoder

-D
,C
TS
AC
©

Aug 2010 © Ganesh Khedkar 37