Analog and Digital Electronics

18CS33
Venugopala Rao A S
Dept. of Computer Science and Engineering
SMVITM Bantakal Udupi
venugopalrao.cs@sode-edu.in
 Introduction to VHDL
• Syllabus
• Introduction to VHDL:
• VHDL description of combinational circuits,
• VHDL Models for multiplexers,
• VHDL Modules.
• Latches and Flip-Flops:
• Set Reset Latch,
• Gated Latches,
• Edge-Triggered D Flip Flop
• SR Flip Flop,
• J K Flip Flop,
• T Flip Flop,
• Flip Flop with additional inputs,
• Asynchronous Sequential Circuits
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 Introduction to VHDL
• Hardware Description Language / HDL
• Is the textual description of a digital circuit.

• Allows us to describe a circuit using words and symbols.

• Textual description is converted into configuration data and

implements the desired functionality.

• Allows a digital system to be designed and debugged at a

higher level before implementation at the gate and flip-flop
level.
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 Introduction to VHDL
• Using HDL we are able
• Describe a large complex design requiring hundreds of logic
gates in a convenient manner, in a smaller space.
• Use software test-bench to detect functional error, if any, and
correct it (called simulation).
• Get hardware implementation details (called synthesis).
• Two widely used HDLs are
• Verilog
• VHDL (Very high speed integrated circuit Hardware Description
Language)

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 Introduction to VHDL
• VHDL
• Is a hardware description language used to describe the
behavior and structure of digital systems.
• The acronym VHDL stands for VHSIC Hardware
Description Language, (VHSIC- Very High Speed Integrated
Circuit)
• Is a general-purpose hardware description language.
• Used to describe and simulate the operation of a wide variety
of digital systems, ranging from a few gates to an
interconnection of many complex integrated circuits.
• A top-down design methodology in which the system is first
specified at a high level and tested using a simulator.
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 Introduction to VHDL
• VHDL can describe a digital system in 3 levels:
• Behavioural
• describes the behaviour of the design in terms of the circuit
and system behaviour using algorithms.
• Data flow
• describes the transfer of data from input to output and
between signals.
• Structural
• describes the circuit structure in terms of the logic gates used
and the interconnect wiring between the logic gates to form a
circuit netlist.
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 Introduction to VHDL
• Example for 3 levels :
• Behavioural
• A binary adder VHDL code in terms of its function of adding
two binary numbers, without giving any implementation
details.
• Data flow
• A binary adder VHDL code by giving the logic equations for
the adder.
• Structural
• A binary adder VHDL code in by specifying the
interconnections of the gates which make up the adder.
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 Introduction to VHDL
• VHDL Description of Combinational Circuits
• A signal is used to describe a signal in a physical system.

• Includes variables similar to variables in programming

languages.

• To obtain synthesizable code for hardware, signals should be

used to represent hardware signals.

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 Introduction to VHDL
• This high-level description uses language constructs that
resemble a high-level software programming language.
• VHDL is not case sensitive.
• Anything following a double dash (--) is treated as a
comment.
• Words such as and, or, and after are reserved words (or
keywords) which have a special meaning to the VHDL
compiler.
• Binary logical operators: and or nand nor xor xnor

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 Introduction to VHDL
• Signal names and other VHDL identifiers may contain
letters, numbers, and the underscore character (_).
• An identifier must start with a letter, and it cannot end with
an underscore.
• Every VHDL statement must be terminated with a
semicolon.
• Spaces, tabs, and carriage returns are treated in the same
way.
• This means that a VHDL statement can be continued over
several lines, or several statements can be placed on one line.

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 Introduction to VHDL
• “<=” is the signal assignment operator which indicates that
the value computed on the right-hand side is assigned to the
signal on the left side.

• Signal assignment statements are examples of concurrent

statements.

• The VHDL simulator monitors the right side of each

concurrent statement, and any time a signal changes, the
expression on the right side is immediately re-evaluated.

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 Introduction to VHDL
• The new value is assigned to the signal on the left side after
an appropriate delay.
• This is exactly the way the hardware works.

• Any time a gate input changes, the gate output is recomputed

by the hardware, and the output changes after the gate delay.

• In general, a signal assignment statement has the form

• signal_name <= expression [after delay];

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 Introduction to VHDL
• Consider the following circuit

• Behavioural description:
• E <= D or (A and B);
• Dataflow description:
• C <= A and B after 5 ns;
• E <= C or D after 5 ns;

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 Introduction to VHDL
• Structural description:
• Requires a two-input AND-gate component and a two-input
OR gate component be declared and defined.
• Components may be declared and defined either in a library
or within the architecture part of the VHDL code.
• Instantiation statements are used to specify how components
are connected.
• Instantiating a component is different than calling a function
in a computer program.
• An instantiated component computes a new output value
whenever its input changes.
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 Introduction to VHDL
• Each copy of a component requires a separate instantiation
statement to specify how it is connected to other components
and to the port inputs and outputs.
• An instantiation statement is a concurrent statement that
executes anytime one of the input signals in its port map
changes.
• Instantiating the AND gate and the OR gate of the circuit as
follows:
• Gate1: AND2 port map (A, B, C);
• Gate2: OR2 port map (C, D, E);

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 Introduction to VHDL

• Behavioural description:
• Dataflow description:
• Structural description:

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 Introduction to VHDL
• In the behavioral description E <= D or ( A and B); parentheses
are used to specify the order of operator execution.
• The dataflow description of the circuit
• C <= A and B after 5 ns;
• E <= C or D after 5 ns;
• Here it is assumed that each gate has a 5-ns propagation delay.
• When these statements are simulated, the first statement will be
evaluated any time A or B changes, and the second statement will
be evaluated any time C or D changes.
• E.g.: Suppose that initially A = 1, and B = C = D = E = 0.
• If B changes to 1 at time 0, C will change to 1 at time = 5 ns.
• Then, E will change to 1 at time = 10 ns.
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 Introduction to VHDL
• VHDL signal assignment statements, are examples of
concurrent statements.
• The VHDL simulator monitors the right side of each
concurrent statement, and any time a signal changes, the
expression on the right side is immediately re-evaluated.
• The new value is assigned to the signal on the left side after
an appropriate delay.
• This is exactly the way the hardware works
• Any time a gate input changes, the gate output is recomputed
by the hardware, and the output changes after the gate delay

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 Introduction to VHDL
• When we initially describe a circuit, we may not be
concerned about propagation delays.
• If we write
• C <= A and B;
• E <= C or D;
• this implies that the propagation delays are 0 ns.
• In this case, the simulator will assume an infinitesimal delay
referred to as Δ (delta).
• Assume that initially A =1and B = C = D = E = 0.
• If B is changed to 1 at time = 1 ns, then C will change at time
1+ Δ and E will change at time 1 + 2Δ.
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 Introduction to VHDL
• Here the order of the above concurrent statements is
unimportant. If we write
• E <= C or D;
• C <= A and B;
• the simulation results would be exactly the same as before.
• In general, a signal assignment statement has the form
• signal_name = expression [after delay];
• The expression is evaluated when the statement is executed,
and the signal on the left side is scheduled to change after
delay.

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 Introduction to VHDL
• The square brackets indicate that after delay is optional; they
are not part of the statement.
• If it is omitted, then the signal is scheduled to be updated
after a delta delay.
• VHDL program has no explicit loops.
• But concurrent statements may execute repeatedly as if they
were in a loop
• Consider an inverter with the output connected back to the
input

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 Introduction to VHDL
• If the output is ‘0’, then this ‘0’ feeds back to the input and
the inverter output changes to ‘1’ after the inverter delay,
(say 10 ns).
• Then, the ‘1’ feeds back to the input, and the output changes
to ‘0’ after the inverter delay.
• The signal CLK will continue to oscillate between ‘0’ and
‘1’, as shown in the waveform.

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 Introduction to VHDL
• The corresponding concurrent VHDL statement will produce
the same result.
• CLK <= not CLK after 10 ns;

• If CLK is initialized to ‘0’, the statement executes and CLK

changes to ‘1’ after 10 ns.
• Because CLK has changed, the statement executes again, and
CLK will change back to ‘0’ after another 10 ns.
• This process will continue indefinitely.

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 Introduction to VHDL
• On the other hand, the concurrent statement
• CLK = not CLK; -- results in error.

• Because there is 0 delay, the value of CLK will change at

times 0+Δ, 0 +2Δ, 0+3Δ, etc.
• Because Δ is an infinitesimal time, time will never advance
to 1 ns.
• The figure shows three gates that have the signal A as a
common input

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 Introduction to VHDL

• The corresponding VHDL code is given below

• -- when A changes, these concurrent
• -- statements all execute at the same time
• D <= A and B after 2 ns;
• E <= not A after 1 ns;
• F <= A or C after 3 ns;

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 Introduction to VHDL
• The three concurrent statements execute simultaneously
whenever A changes, just as the three gates start processing
the signal change at the same time.
• However, if the gates have different delays, the gate outputs
can change at different times.
• If the gates have delays of 2 ns, 1 ns, and 3 ns, respectively,
and A changes at time 5 ns, then the gate outputs D, E, and F
can change at times 7 ns, 6 ns, and 8 ns, respectively.
• The VHDL statements work in the same way. Even though
the statements execute simultaneously, the signals D, E, and
F are updated at times 7 ns, 6 ns, and 8 ns
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 Introduction to VHDL
• However, if no delays were specified, then D, E, and F
would all be updated at time 5+ Δ.
• In all these examples, every signal is of type bit, which
means it can have a value of ‘0’ or ‘1’. (Bit values in VHDL
are enclosed in single quotes to distinguish them from
integer values.)
• In digital design, we often need to perform the same
operation on a group of signals.
• A one-dimensional array of bit signals is referred to as a bit-
vector

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 Introduction to VHDL
• If a 4-bit vector named B has an index range 0 through 3,
then the four elements of the bit-vector are designated B(0),
B(1), B(2), and B(3).
• The statement B <= “0110” assigns ‘0’ to B(0), ‘1’ to B(1),
‘1’ to B(2), and ‘0’ to B(3).
• Consider an array of four AND gates as shown below.

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 Introduction to VHDL
• The inputs are represented by bit-vectors A and B, and the
outputs by bit-vector C.
• we can write four VHDL statements to represent the four
gates as shown below

• more efficient way is to write a single VHDL statement that

performs the and operation on the bit-vectors A and B.
• C <= A and B;

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 Introduction to VHDL
• When applied to bit-vectors, the and operator performs the
and operation on corresponding pairs of elements.
• If the preceding signal assignment statements contains “after
delay”, then it creates an inertial delay model
• consider the signal assignment C <= A and B after 10 ns;
• Assume A and B are initially 1, and A changes to 0 at 15 ns,
to 1 at 30 ns, and to 0 at 35 ns.
• Then C changes to 1 at 10 ns and to 0 at 25 ns, but C does
not change in response to the A changes at 30 ns and 35 ns
because these two changes occurred less than 10 ns apart.

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 Introduction to VHDL
• A device with an inertial delay of D time units filters out
output changes that would occur in less than or equal to D
time units
• VHDL can also model devices with an ideal (transport)
delay.
• Output changes caused by input changes to a device
exhibiting an ideal (transport) delay of D time units are
delayed by D time units, and the output changes occur even
if they occur within D time units.
• The VHDL signal assignment statement that models ideal
(transport) delay is
• signal_name <= transport expression after delay
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 Introduction to VHDL
• E.g.:
• C <= transport A and B after 10 ns;
• Assume A and B are initially 1 and A changes to 0 at 15 ns,
to 1 at 30 ns, and to 0 at 35 ns.
• Then C changes to 1 at 10 ns, to 0 at 25 ns, to 1 at 40 ns, and
to 0 at 45 ns.
• Note that the last two changes are separated by just 5 ns.

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 Introduction to VHDL
• VHDL Modules
• To write a complete VHDL module, we must declare all of the
input and output signals using an entity declaration, and then
specify the internal operation of the module using an architecture
declaration.
• E.g.: Consider the following figure.

• Let the entity declaration be given the name “two_gates” to the

module.
• The port declaration should specify the inputs and outputs to the
module.
• Here A, B, and D are input signals of type bit, and E is an output
signal of type bit.
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 Introduction to VHDL
• Let us name architecture as “gates”.
• The signal C is declared within the architecture because it is
an internal signal.
• The two concurrent statements that describe the gates are
placed between the keywords begin and end.
• Thus the corresponding VHDL code will be

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 Introduction to VHDL
• When we describe a system in VHDL, we must specify an
entity and an architecture at the top level, and also specify an
entity and architecture for each of the component modules
that are part of the system as shown below.

• Each entity declaration includes a list of interface signals that

can be used to connect to other modules or to the outside
world.
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 Introduction to VHDL
• We will use entity declarations of the form:

• The items enclosed in square brackets are optional.

• The interface-signal-declaration has the following form:

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 Introduction to VHDL
• The curly brackets indicate zero or more repetitions of the
enclosed clause.
• Input signals are of mode in, output signals are of mode out,
and bi-directional signals are of mode inout.
• The optional initial-value is used to initialize the signals on
the associated list; otherwise, the default initial value is used
for the specified type.

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 Introduction to VHDL
• with each entity, there will be one or more architecture
declarations of the form
architecture architecture-name of entity-name is
[declarations]
begin
architecture body
end [architecture] [architecture-name];
• In the declarations section, we can declare signals and
components that are used within the architecture.
• The architecture body contains statements that describe the
operation of the module.
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 Introduction to VHDL
• E.g.: Write the entity and architecture for a full adder module
• The entity specifies the inputs and outputs of the adder
module, as shown in Figure below.

• The port declaration specifies that X, Y and Cin are input

signals of type bit, and that Cout and Sum are output signals
of type bit.

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 Introduction to VHDL
• entity FullAdder is
port (X, Y, Cin: in bit; -- Inputs
Cout, Sum: out bit); -- Outputs
• end FullAdder;
--The operation of the full adder is specified by an architecture
declaration

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 Introduction to VHDL
• The architecture name (Equations) is arbitrary, but the entity
name (FullAdder) must match the name used in the
associated entity declaration.
• The VHDL assignment statements for Sum and Cout
represent the logic equations for the full adder.
• Several other architectural descriptions such as a truth table
or an interconnection of gates could have been used instead.
• In the Cout equation, parentheses are required around (X and
Y) because VHDL does not specify an order of precedence
for the logic operators.

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 Introduction to VHDL
• VHDL Models for Multiplexers
• Figure below shows a 2-to-1 multiplexer (MUX) with two
data inputs and one control input.

• The MUX output is F = A`I0 + AI1.

• The corresponding VHDL statement is
• F = (not A and I0) or (A and I1);

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 Introduction to VHDL
• Alternatively, we can represent the MUX by a conditional
signal assignment statement, as shown below.

• F <= I0 when A = '0' else I1;

• This statement executes whenever A, I0, or I1 changes.

• The MUX output is I0 when A = ‘0’, and else it is I1.
• In the conditional statement, I0, I1, and F can either be bits
or bit-vectors

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 Introduction to VHDL
• The general form of a conditional signal assignment
statement is
signal_name = expression1 when condition1
else expression2 when condition2
[else expressionN];
• This concurrent statement is executed whenever a change
occurs in a signal used in one of the expressions or
conditions
• If condition1 is true, signal_name is set equal to the value of
expression1, or else if condition2 is true, signal_name is set
equal to the value of expression2, etc
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 Introduction to VHDL
• The line in square brackets is optional.
• Cascading of two cascaded MUXes

• The output MUX selects A when E = ‘1’; or else it selects

the output of the first MUX, which is B when D = ‘1’, or else
it is C.
• This can be represented by a conditional signal assignment
statement.

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 Introduction to VHDL
• 4-to-1 MUX

• The logic equation for the 4-to-1 MUX is

• F =A`B`I0 + A`BI1 + AB`I2 + ABI3
• Thus, we can model the MUX using VHDL statement as
• F <= (not A and not B and I0) or (not A and B and I1) or
(A and not B and I2) or (A and B and I3);

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 Introduction to VHDL
• Another way to model the 4-to-1 MUX is to use a
conditional assignment statement
• F <= I0 when A&B = “00”
else I1 when A&B = “01”
else I2 when A&B = “10”
else I3;
• The expression A&B means A concatenated with B, that is,
the two bits A and B are merged together to form a 2-bit
vector
• This bit vector is tested, and the appropriate MUX input is
selected.
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 Introduction to VHDL
• For example, if A = ‘1’ and B = ‘0’, A&B = “10” and then I2
is selected.
• Instead of concatenating A and B, we could use a more
complex condition:

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 Introduction to VHDL
• A third way to model the MUX is to use a selected signal
assignment statement as shown below

• A&B cannot be used in this type of statement, so we first set

Sel equal to A&B.
• The value of Sel then selects the MUX input that is assigned
to F.
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 Introduction to VHDL
• The general form of a selected signal assignment statement is

• with expression_s select

• signal_s <= expression1 [after delay-time] when choice1,
• expression2 [after delay-time] when choice2,
• ...
• [expression_n [after delay-time] when others];
• This concurrent statement executes whenever a signal
changes in any of the expressions.
• First, expression_s is evaluated. If it equals choice1, signal_s
is set equal to expression1; if it equals choice2, signal_s is
set equal to expression2; etc.
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 Introduction to VHDL
• If expression_s is not equal to any of the enumerated
choices, signal_s is set equal to expression_n.
• The signal_s is updated after the specified delay-time, or
after Δ , if the “after delaytime” is omitted.

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 Introduction to VHDL
• Four-Bit Full Adder
• 4-bit binary adder can be obtained by connecting four full
adders in series as shown below

• We first declare the 4-bit adder as an entity.

• Because the inputs and the sum output are four bits wide, we
declare them as bit_vectors which are dimensioned 3 downto
0.
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 Introduction to VHDL
• Next, we specify the FullAdder as a component within the
architecture of Adder4.
• The component specification is very similar to the entity
declaration for the full adder, and the input and output port
signals correspond to those declared for the full adder.
• Following the component statement, we declare a 3-bit
internal carry signal C.

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 Introduction to VHDL

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 Introduction to VHDL
• In the body of the architecture, we create several instances of
the FullAdder component.
• Each copy of FullAdder has a name (such as FA0) and a port
map.
• The signal names following the port map correspond one-to-
one with the signals in the component port.
• Thus, A(0), B(0), and Ci correspond to the inputs X, Y, and
Cin, respectively.
• C(1) and S(0) correspond to the Cout and Sum outputs.
• Note that the order of the signals in the port map must be the
same as the order of the signals in the port of the component
declaration.
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 Introduction to VHDL
• This demonstrates how to construct a VHDL module using
an entity-architecture pair.
• The 4-bit adder module demonstrates the use of VHDL
components to write structural VHDL code.
• Components used within the architecture are declared at the
beginning of the architecture, using a component declaration
of the form

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 Introduction to VHDL
• The port clause used in the component declaration has the
same form as the port clause used in an entity declaration.
• The connections to each component used in a circuit are
specified by using a component instantiation statement of the
form

• The list of actual signals must correspond one-to-one to the

list of interface signals specified in the component
declaration.

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