Noise in Deep Submicron Digital Design

Kenneth L. Shepard and Vinod Narayanan

IBM T. J . Watson Research Center
Yorktown Heights, NY 10598
Abstract
As t echnol ogy scales i nt o t he deep s ubmi cr on regi me,
noi s e i mmu n i t y i s becoming a me t r i c of comparable
i mpor t ance t o area, timing, and power f o r t he analy-
si s and desi gn of VLSI s ys t ems . Th i s paper def i nes
noi s e as it pert ai ns t o digital s ys t ems and addresses
t he t echnol ogy t rends whi ch are bri ngi ng noi s e i ssues
t o t he f oref ront . The noi se sources whi ch are plagu-
ing di gi t al s ys t ems are ezpl ai ned. A met r i c referred t o
as noi s e st abi l i t y i s defined, and a st at i c noi se anal y-
si s met hodol ogy based o n t hi s met r i c is introduced t o
demons t r at e how noi se can be analyzed syst emat i cal l y.
Anal ys i s i s s ues associated wi t h on- chi p i nt erconnect
are also consi dered. Thi s paper concl udes with a dis-
cus s i on of t he device, ci rcui t , l ayout , and logic desi gn
i s s ues associated wi t h noi se.
1 Introduction
Noise immunity has always been a metric of interest in
analog circuit design where the noise sources of princi-
pal concern are those associated with physical effects
- shot noise, thermal noise, flicker noise, and burst
noise[l]. In contrast, the pervasiveness of digital sys-
tems is in great part due to their inherent noise im-
munity. Digital circuits use a range of analog voltages
to define a logic 1 and logic O, where degradation of
these voltages due to noise would cause them to fall
out of the valid ranges. High-gain logic gates, the best
examples being CMOS inverters, restore these logic
values by means of nonlinear voltage transfer charac-
teristics which significantly reduce noise near the high
and low voltage rails[2]. These gates are usually re-
ferred to as rest ori ng logic gates.
The high gain of digital circuits, however, results
in new man-made noise sources, which can be sev-
eral orders of magnitude greater than those associated
with the physical silicon devices. This first became a
problem in the context of mixed digital-analog ICs
in which the noisy digital circuits could strongly in-
fluence the noise-sensitive analog ones[3]. With the
continued scaling of CMOS technology and with per-
formance requirements which are driving designs in
the direction of more noise-sensitive dynamic circuits,
man-made noise sources are becoming an issue even
in purely digital designs. I n modern CMOS processes,
more levels of interconnect (>6 levels) are being
packed closer together (minimum spacing <0.3 p m) ,
increasing the amount of capacitive coupling between
nets. To maintain drive strength in the face of scaled-
down power supply voltages, threshold voltages are
1063-6757/96 $5.00 0 1996 IEEE
also scaled lower. Lower threshold voltages result in
lower noise margins and increased leakage noise. Noise
in deep submicron digital circuits must now be ana-
lyzed and designed as a metric of comparable impor-
tance to area, timing, and power.
2 Noise in deep submicron digital de-
signs
2.1 What is noise?
We begin this discussion with a few useful definitions.
An eval uat i on node is a circuit node that forms the
connection between channel connected components in
the design. Pass transistors are one exception to this
rule, in that it is useful to treat both the source and
drain as evaluation nodes. St at i c eval uat i on nodes
are evaluation nodes which always have a conducting
path to power or ground. St at i c ci rcui t s are circuits
in which all evaluation nodes are static. The imped-
ance which holds an evaluation node high or low is re-
ferred to as the node i mpedance. Dy nami c eval uat i on
nodes are evaluation nodes that during some part of
normal system operation are disconnected from power
and ground; that is, they have an infinite node imped-
ance and a logic value determined by a charge stored
on a capacitor. Dy nami c ci rcui t s are circuits which
contain dynamic evaluation nodes.
Noi s e can be defined as anything that causes the
voltage of an evaluation node to deviate from the nom-
inal supply or ground rails when it should otherwise
have a stable high or low value (i.e., the node is not
switching) as determined by the logic and delay of the
circuit.
Noise can be characterized by its peak magnitude
relative to the nominal supply and ground rails and
its behavior in the time-domain. Noise sources that
reduce an evaluation node voltage below the supply
level (VDD) are denoted VH, while noise sources that
increase an evaluation node voltage above the ground
level (GND) are denoted VL. Noise may also be boot-
strapping if it increases a node voltage above the sup-
ply level (V**) or below the ground level (VL.). For
the purposes of determining how circuits respond to
noise, one can abstract time-domain response into one
of two categories - DC noise and pulse noise as shown
in Figure 1. These two noise behaviors are discussed
in detail in the context of noise sources in Section 2.2.
Pulse noise on an otherwise high logic level is, for ex-
ample, denoted as VFl se while DC noise on an other-
wise high logic level is denoted as Vgc.
524
"DD .................................. ._____ Dc ...............................................................
(a) 1 f v u
................. _____.............
- vPul= v-
VDD t-
H
Figure 1: Time domain abstractions for noise: (a) DC
noise and (b) pulse noise
2.2 Noise sources in digital systems
The noise sciurces most relevant to digital design
are leakage nIDise, power supply noise, charge-sharing
noise, and crosstalk noise.
2.2.1 Leakage noise
Leakage noise is generally applied to the context of
dynamic nodes and comes from two sources. There is
leakage noise due to the off current of FETs, which
allows charge. to drain from or accumulate on the
dynamic node. This is largely due to subthreshold
current and is directly determined by the threshold
voltage and the temperature, Another leakage noise
source is minority carrier back-injection into the sub-
strate due to bootstrapping. This is sometimes re-
ferred to as substrate noise in the context of mixed
analog-digital. ICs[4]. One solution for substrate noise
is to introduce guard bands, n-type diffusions tied
to the supply voltage to collect the minority carrier
electrons[3, 51. Substrate noise becomes less of a prob-
lem at scaled power supply voltages because of the
need to bootstrap more than - 0.6V and, therefore,
is not considered in the static noise analysis methodol-
ogy discussed in Section 3. Leakage noise can also be
used in reference to static evaluation nodes, in which
the "leakage" is ratioed against a static path holding
the node in the opposite direction. Leakage noise is
a DC noise source because it changes the steady-state
logic high or low voltage value on a time scale which
is slowly varying with respect the the system clock, a
time scale which werefer to as the phase time.
2.2.2 Charge-sharing noise and crosstalk
Charge-sharing noise is produced by charge redistrib-
ution between a dynamic evaluation node and inter-
nal nodes of the circuit. Figure 2(a) shows a circuit
in which charge sharing noise is graphed under four
noise
conditions in Figure 2(b).l In (z), the charge shar-
ing noise is calculated in the absence of a half-latch
PFET device for Al l A2, A3, and A4 simultaneously
switching from low to high, while B1, B2, B3, and B4
are low. (ii) shows the same situation in the pres-
ence of a half-latch. In (iii), Al , A2, A3, and A4
are assumed to be logically orthogonal (i. e., at most
one of these signals may be '1' at the same time), a
Boolean satisfiability constraint that can be verified
through binary-decision diagram techniques[7, 81, but
no half-latch is used. In (iv), logical orthogonality and
a half-latch are assumed.
(bl
Figure 2: Charge sharing noise: (a) circuit and (b)
dynamic node voltage
Crosstalk noise is the voltage induced on a node due
to capacitive coupling to a switching node of another
net. Figure 3 shows the noise coupling onto three dif-
ferent types of evaluation nodes from a single noise
source switching with a fall time of loops with simple
capacitive coupling.
2.4 cy ' - - - 1
1110.0 i - . 0.5 1.0 1 3 211
nm
Figure 3: Coupling noise calculated for three circuit
topologies (a) Pass transistor (b) Two inverters (c)
Dynamic node of domino stage
Both crosstalk and charge-sharing noise are pulse
noise sources, in which the leading edge is determined
by a switching signal on the chip and the trailing edge
is determined by the node impedance charging or dis-
charing the capacitance of the evaluation node. The
time constant of this response is referred to as the
restoring time constant, since it is the time it takes
the node to be restored to its static value. For dy-
namic nodes, as in cases (iii) and (i) of Figure 2, this
'The simulations shown in this paper are performed in a
0 . 5 ~ ~ 7 1 CMOS process described in detail elsewhere [SI.
525
time constant is infinite (i.e., the node never recovers).
For static paths that drive through pass gates, as in
Figure 3(a), this time constant can be very long.
2.2.3 Power supply noise
Power supply noise explicitly refers to noise appearing
on the supply and ground nets of the chip and cou-
pled onto evaluation nodes through a FET conduction
path. Figure 4 shows the actual supply variation as
measured on a fourth-level metal sense point near the
on-chip cache of a CMOS microprocessor running at
a clock period of 7 nsec. Power supply noise contains
/
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~ ........................ .-r ...........................................
1 . I .
I .
--_I_ - _ _ _ - _ _ _ _ - - - -_ _ _ _ _ _ - - _ _ --
I
. .
I
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I
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8 .
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I . I .
I .
both a DC and sinusoidal content. The DC compo-
nent of power supply noise is produced by the IR drop
through the power and ground nets due to the aver-
age current demands over the chip. The DC compo-
nent of power supply noise can be reduced through a
denser or wider interconnect structure for the power
and ground network. The sinusoidal component of
power supply noise comes from the RLC response of
the chip and package to current demands that peak
at the beginning of the clock cycle. I n addition to si-
nusoidal variation, a sharply peaked current demand
may also produce higher frequency components, which
can be largely suppressed by the use or placement of
on-chip decoupling capacitors[9]. I n Figure 4, there is
some higher frequency content around 1 GHz. Since
power supply variations vary slowly relative to circuit
frequency response, they are generally treated as DC
for analysis purposes.
2.3 How do we know when the system will
function?
The fundamental goal of a conservative noise analysis
methodology is to guarantee that on every evaluation
node in the circuit, the correct 1 or 0 value is defined
by voltages that fall within one of two valid ranges for
all times that a stable high or low logic value should
be present as determined by the logic and delay of
the circuit. For dynamic evaluation nodes, this goal is
essential since no static path exists to restore the cor-
rect logic state in the case of noise. I t is also essential
for many bistable circuits. One example of this would
be VL* coupling noise feeding the pass gate of a latch
in which the gate of the pass gate is 0 and the latch
stores a 1. If TIL* exceeds the threshold voltage of the
NFET of the pass gate, the latch can be drained and
flipped to a 0 without a chance for recovery. Sta-
tic evaluation nodes in the absence of feedback will,
in general, recover from pulse noise if one waits for a
restoring time constant to elapse; however, the stabil-
ity of logic signals due to noise is not something that
is practical to manage in predicting performance and
cycle time.
One way to ensure functionality for static CMOS
logic gates is to define DC noise margins, NML and
NMH such that the bistable circuits shown in Figure
5 do not switch and NMH +NML is maximum[lO].
This corresponds to biasing each gate at the unity
gain point in its DC voltage transfer characteristic.
For noise V <NMH and VL <NML, gates will al-
ways be biased into regions of their voltage transfer
characteristics in which noise is attenuated.
U U
Figure 5: Latch circuits which define DC noise mar-
gins for CMOS NOR, NAND, and NOT gates.
DC noise margins are much too conservative to ap-
ply against the magnitude of pulse noise sources, be-
cause they fail to consider the fact that logic gates
act as low-pass filters. Noi s e t ol erance is a general-
ized view of noise margins applied to triangular pulsed
noise sources, in which different noise margins are cal-
culated for different pulse amplitudes and widths[l l].
In order to handle nonrestoring logic gates, such as
pass transistors, and provide more precision in han-
dling pulse noise and bootstrap noise sources, one can
further generalize the idea of noise tolerance, which
applies to an individual logic gate, to the concept of
noise stability which applies to the entire digital cir-
cuit. Consider the case in which noise is present on
every evaluation node juxtaposed in time in the worst
allowable way. The worst possible magnitude at which
noise can exist in the circuit defines a bias point. At
this bias point, the circuit is defined to be noise stable
if for any one noise source, a small change in its am-
plitude of c~K results in a noise amplitude change on
any evaluate node of 6 6 such that 16vj /SK 1 <1 with
i, j E { L, H, L*, H*}.
2. 4 Noise and delay
As an aside, capacitive coupling and power supply
variations can also have a direct effect on delay that
must also be considered independent of this noise
analysis. Leakage noise and power supply noise re-
sult in lower or higher supply levels, which reduce
526
or enhance the current drive of a circuit and conse-
quently increase or decrease the delay. Coupling noise
can cause the effective line capacitance to increase or
decrease in the presence of simultaneously switching
noisy lines, increasing or decreasing the delay.
3 Static noise analysis
In this section, we briefly introduce a static noise
analysis methodology, called Har mony, which en-
forces circuit stability. Details will be presented
elsewhere[l2]. Dynamic simulation is not feasible for
checking noise on designs with tens of millions of tran-
sistors. Instead, as with timing, static analysis tech-
niques which couple simulations on small numbers of
transistors (basically individual gates) with a path
trace are used. Worst-case preconditioning assump-
tions and (in most cases) worst-case temporal rela-
tionships drive the simulations. At the same time,
global interconnect is handled with more sophistica-
tion than local circuit interconnect in determining
the magnitude of coupling noise. Analysis is based on
constructing a noise graph abstraction, which follows
very closely 1,hetiming graphs used in static timing
analysis[l3]. As in the case of static timing analysis
in which waveforms are abstracted as saturate ramps,
the actual dynamic waveforms are simplified to pulse
or DC waveshapes. In the case of precharged logic,
only noise against the reset state is considered since
this is the transition that contains the logical informa-
tion of the ciIcuit. Power supply noise is also assumed
to be characterized by a DC value.
3.1 Constructing a noise graph
The steps to constructing a noise graph from a circuit
are outlined below.
3.1.1 Evaluation node identification and di-
rection setting
The evaluation nodes in the circuit are identified. Ba-
sic topologies; are recognized - restoring logic stages,
domino logic stages, simple inverter feedbacks, weak
pullups, and pass transistor stages. Evaluation nodes
which are precharged in dynamic logic stages are iden-
tified as precharge eval uat i on nodes. These nodes po-
tentially require charge-sharing noise calculation as
discussed in Section 3.1.3. Transistor directions are set
using the simple rules-based approach of J ouppi[ 141.
This is of principal concern for pass gates. Feedbacks
are recognized so that they can be independently pre-
conditioned. Floating capacitors are broken and tied
to ground w:hen connected to any nodes other than
evaluation nodes (i.e., coupling is only considered to
evaluation nodes). This is not a significant source of
error since evaluation nodes will be the only nodes
with significant interconnection length. Nodes which
feed NFET pass transistors are identified as bootstrap-
down eval uat i on nodes, since they will be sensitive to
V p while nodes which feed PFET pass transistors are
identified as bootstrap-up eval uat i on nodes since they
will be sensitive to V . .
3.1.2 Calculate the coupling noise and restor-
ing time constants for each evaluation
node in the circuit
For wire lengths less than - lmm, we ignore resis-
tance. In addition, all signals coupled to the given
evaluation node are assumed to switch simultaneously
at a minimum slew time (t;:,). I n Section 4, we
show how these assumptions are relaxed in the case
of long interconnect. Static paths are preconditioned
to keep the evaluation nodes quiet against the noise
source, including feedback paths. All pass transistors
are configured off except that configuration which pro-
duces the highest static resistance to supply or ground
to produce worst-case coupling noise on the node in
question. VH and Vh due to coupling are calculated
at each evaluation node, except precharge evaluation
nodes, for which only VH or VL is calculated, depend-
ing on whether the node is precharge high or low. For
bootstrap-down evaluation nodes, VL* is also calcu-
lated while for bootstrap-up evalaution nodes, VH-
is calculated. Each coupling noise waveshape is ab-
stracted as a pulse waveform with a leading edge deter-
mined by a maximum slew time (t;::) and a trailing
edge determined by a restoring time constant. Figure
3 shows the typical results of such a simulation.
3.1.3 Charge sharing noise is calculated on all
precharge evaluation nodes
Charge-sharing noise is calculated for all precharge
evaluate nodes identified topologically. In every stack
connected to the precharge evaluate node, the top de-
vice and bottom device are configured off. All other
devices in the leg of the NFET stack are on. The
top devices are then switched simultaneously for par-
allel stacks. In the presence of an evaluate NFET foot
device in the domino NFET stack, the foot device is
considered on. Logic constraints can be used to reduce
pessimism as shown in Figure 2. The charge sharing
and coupling noise are summed to determine the total
pulse noise on the evaluation node.
3.1.4 Draw the directed segments connecting
evalution nodes in the noise graph
Now that the evaluation nodes and pulse noise sources
on each of these nodes is defined, the next step is to
connect the nodes by directed segments according to
the circuit structure to define the noise graph.
There are two basic types of segments in a noise
graph - a rest ori ng segment and a propagat e segment.
A rest ori ng segment connects evaluation nodes in the
case that the DC transfer characteristic shows gain.
Restoring segments are identified by dashed lines and
connect inputs and outputs of restoring logic gates. A
propagate segment is one which propagates noise from
one evaluation node to another without gain. Chan-
nel conduction in a pass gate, for example, is repre-
sented by a propagate segment. Propagate segments
are denoted by solid lines. Both types of segments are
labelled by noise type. A power-supply noise segment
is a special propagate segment in which the source
527
node is ground or supply. The power supply noise is
propagated as VL from ground and VH from supply.
For bootstrap-up nodes, V * is also propagated from
supply and V p from ground. Figure 6 shows an ex-
ample of a noise graph, in this case for a latch driving
a domino gate.
I
-+
Figure 6: (a) Circuit and (b) noise graph for a latch
driving a domino stage
3.2 Propagating noise through a graph
Once the noise graph is constructed, it is searched
in a breadth-first fashion to propagate noise through
the network and, in the case of restoring segments, to
perform the sensitivity tests required to ensure noise
stability.
search
3.2.1 Propagate segments
On each propagate segment , the peak output voltage
waveform is calculated for the DC noise and pulse
noise appearing on the input. This peak voltage is
propagated as DC noise onto the output evaluation
node; therefore, the DC noise appearing on the in-
put is that propagated from previous stages as well as
that introduced as power supply noise. This assump-
tion introduces pessimism into the analysis but elim-
inates the need to propagate time-domain response
while taking into account the low-pass filter charac-
teristics of logic gates.
3.2.2 Restoring segments
For restoring logic, there will, in general, be multiple
inputs entering the same stage. A set of inputs form a
noi se equivalence class when the worst-case response
at the output is produced when those inputs are simul-
taneously excited by noise. This allows us to perform a
worst-case analysis for noise without knowledge of the
relative timing of noise events. Two distinct types of
simulations are performed for restoring logic segments.
The first is a simulation to check stability and the sec-
ond, performed conditionally based on the results of
the first, propagates noise to the output. In both sim-
ulations, for a given input and given noise type, VH or
V, other conduction paths in parallel with the one in
question are preconditioned on except for the tran-
sistor closest to the evaluate node, which will be noise
equivalent to the input under test. Feedback paths
are also preconditioned to hold the node at the static
level during both simulations.
The first simulation checks the condition of noise
stability, which must be done for restoring logic stages
since they have gain. Let i denote different inputs of
a noise equivalence class. Let (V,); denote the DC
voltage on input i, let ( Vr l s e) i denote the pulse volt-
age appearing on input i, and let V, be the output
voltage, then for all equivalence classes, for all i in an
equivalence class,
where p, v E { L, H, L*, H* . This is a sufficient con-
conditions localizes the global stability definition of
Section 2.3 to an effective stability analysis on a single
stage by requiring subunity sensitivity in magnitude
against all the noise propagated from previous stages.
The derivatives are evaluated at the bias point de-
termined by the noise appearing on the inputs of the
equivalence class. These sensitivities can be readily
calculated in certain timing simulators in the time-
domain by the direct or adjoint methods[l5, 161. In
the event of a violation, the noise and noise sensitivi-
ties for all the inputs in the equivalence class contain-
ing the violation are reported. The noise source (input
and DC/pulse) of the highest sensitivity is the most
likely candidate for repair.
For those equivalence classes which do have stabil-
ity violations, a second simulation is performed similar
to that performed for propagate segments in which the
actual DC and pulse noise is simultaneously applied to
each input in the class to determine the output noise.
For those equivalence classes which are in violation,
a recovery mechanism exists to provide a worst-case
voltage to propagate forward in the path search. In
this simulation the same pulse is applied to each in-
put in an equivalence class in the absense of a DC
bias to determine the output voltage at the unity gain
point. This generally represents the most pessimistic
output noise. Figure 7 shows the pulse transfer char-
acteristic that would be calculated as part of this
simulation for an and-or-invert gate for one particular
noise equivalence class with a restoring time constant
of Ins. The inset shows the configuration used in each
case. These look similar in their hysteretic behavior
to the AC transfer characteristics of Ref. 17.
dition to ensure circuit sta k ility. The first of the two
3.2.3
A DC noise value and a pulse noise value are stored
on each evaluation node during path traversal. When
Implied rules of the path trace
528
static timing analysis.
P I
Figure 7: Pulse transfer characteristic and-or-invert
static CMOS gate for (a){Al, Bl} VL + VH equiv-
alence class and (b) {Al, A2} V -+VL equivalence
class
multiple restoring segments converge on a node, the
propagated noise is the worst of the converged seg-
ments. When multiple propagate segments converge
on a node, the noise sources are summed. When prop-
agate and restoring segments converge on an evalua-
tion node, the worst of the propagated output noises
from the restoring segments is added to the sum of the
propagate segment noises.
4 Long interconnect analysis
In calculating coupling as in Section 3.1.2, we made
two significant simplifying assumptions regarding in-
terconnect - that we could ignore resistance and that
wecould assume that all of the coupling sources were
simultaneously switching. In calculating the coupling
noise in long interconnect, resistance must be consid-
ered. In addition, coupling noise calculation on long
interconnect :s one place where the addition of timing
information to break temporal correlation can have a
big effect on reducing pessimism in the analysis.
We define the primary net as the net on which we
wish to calculate the noise at each receiver. The sec-
ondary nets are those nets coupled to the primary
net. There itre two possible network simplifications
that can be used in long interconnect analysis, both
shown in Figure 8. Driver outputs are modeled as
resistances and receiver inputs are modeled as ca-
pacitances. These linear networks are easily ana-
lyzed by moment-matching techniques such as AWE
or PVL[18, l!)]. Four poles are usually more than ade-
quate to determine the response. In Figure 8(a only
the resistance of the primary net is considered. &he re-
sistances on the secondary nets are ignored. In Figure
8(b), the resistances on both primary and secondary
nets is considered, which is more accurate since it con-
siders RC delays in the secondary net. The coupling
capacitance between the secondary nets and other nets
is assumed tc, be grounded.
In both cases, two types of analysis are possible -
one that assumes worst case temporal correlation of
noise sources and one that attempts to break tempo-
ral correlation with the addition of information from
T
T
-
i
Figure 8: Long interconnect analysis for (a) resis-
tances only on the primary net and (b) for resistances
on both the primary and secondary nets
4.1 Worst-case temporal correlation of
In this case, each noise source is a voltage waveform
with a slew time t:::. The sources are applied one
at a time while the other sources are grounded and
the peak magnitudes are added at the receiver. This
is equivalent to assuming that the noise voltage ar-
rives at each coupling capacitor at the time required
to produce the worst coupling at the quiet receiver.
4.2 Using static timing analysis to break
temporal correlation
In this case, weconsider the following additional in-
formation from static timing analysis - early and late
mode arrival times and best case slews (t : f w) at each
Secondary net driver. Let the driver of secondary net
i begin rising at time t;. The problem is then to find
the times t, that fall within the valid early and late
mode arrival time windows for each secondary net dri-
ver that produce the highest peak coupling noise on
the given receiver. One can do this by calculating the
response for each driver individually and determining
the peak position at the quiet receiver. The peak po-
time t, skews. The worst-case combination that satis-
fies the timing orthogonality constraints is selected.
noise sources
sition skews immediately translate back to the arrival
529
4.3 Inductance
Wi th the increasing use of wide, thick wires and the
potential introduction of copper interconnect, induc-
tance is becoming a concern[20]. There are two condi-
tions which must be met for inductance to be signifi-
cant:
R <wC, where R is the resistance per unit
length, C is the inductance per unit length, and
w is the characteristic frequency, roughly deter-
mined by the typical slew times (t,) by w =27r/t,.
t, <2tf, where tf is the time-of-flight given by
tf =l&i? where C is the capacitance per unit
length and 1 is the length of the line[21].
Even if these two conditions are satisfied, the far
end response will behave like a distributed RC line
if RI >2Z0, where 2, is the characteristic impedance
of the line, given by 2, =m. The complexity in
calculating inductance is determining the current re-
turn path. Roughly speaking, the current will return
through the path of minimum R +j wC. For low U ,
the return path will be the path of minimum resis-
tance. I n the case of solder-ball flip-chip packaging in
which supply and ground are introduced throughout
the chip, this will be a return path through the package
for most long interconnect runs, a path of very high
inductance. As w increases, the current return will
seek a lower inductance (and higher resistance) return
on chip. In most cases, it will find a return on a power
or ground bus but in the absence of adequate power
or ground distribution, current may return through a
signal line.
Inductance in the global interconnect has two ef-
fects on noise. At the receivers of switching nets,
inductive ringing may be a concern. For quiet nets
within actively switching environments, inductive cou-
pling tends to worsen noise at the near end while re-
ducing noise at the far end.
To illustrate these points, five parallel lines on 2pm
thick copper interconnect are analyzed as shown in
Figure 9(a). The lines are 3.6pm spaced 1.8pm apart.
Line A is grounded and the current return path as-
sumed for inductance calculations. Line E is actively
switched while the other lines are held quiet by ac-
tive drivers. Figure 9(b) shows the response at the
near and far end of line E in the case of RC and RLC
modelling. There is ringing at the far end when induc-
tance is considered. Figure 9(c) shows the response at
the near and far end of line D. Including inductance
in the analysis reduces the noise at the far end while
increasing the noise at the near end.
5
There are many design techniques that can be used to
reduce noise. Many of these techniques are enforced as
rules early in the design process, while others must be
more carefully traded off. Certain circuit topologies
can be restricted because of their noise sensitivity. In
many cases, NFET-only pass gates are disallowed be-
cause of their sensitivity to power supply noise. Pass
Design issues in reducing noise
Figure 9: (a) Example long interconnect structure,
(b) response on the driver line, and (c) response on
the quiet line. Near end is dashed and far end is solid.
gates at the ends of long wires are almost always for-
bidden because of their sensitivity to bootstrapping
coupling noise. In general, buffers and inverters can
be introduced to clean up noise at the receivers of
noisy lines at the expense of additional delay. Charge-
sharing noise can be controlled to a considerable ex-
tent through the careful use of logic constraints as dis-
cussed in Section 3.1.3 and demonstrated in Figure 2
or through the addition of babysit devices to stat-
ically hold internal nodes high or low as the cost of
additional power.
Many device sizing techniques can be used to im-
prove noise margins, almost always at the expense of
additional delay. Half-latches can be added or sized
up for dynamic nodes. Device lengths can be tuned
up to increase thresholds and reduce leakage. Beta
ratios can be adjusted to improve one noise margin at
the expense of the other.
To reduce coupling noise, the spacing between wires
can be increased or signals can be alternately routed
with power or ground. These techniques have been
applied to constraint-driven routing, primarily in the
context of analog or mixed-signal ICs[22]. Sometimes
it is sufficient to increase the driver strength to help
hold the quiet line quiet, but this is less effective in
long wires because of resistive shielding. I n some cases
when coupling noise is accentuated by simultaneously
switching noise sources, buffers or inverters can be
added onto noisy nets as delay elements to offset their
switching times. In other cases, coupling noise can be
reduced by decreasing overall wire length by insert-
ing a repeater. In extreme cases, differential buses or
DCVS logic can be used.
6 Conclusions
In this paper, wehave defined noise and discussed
the noise sources relevant to digital systems. We have
also defined a metric, noise stability, for determin-
ing design goodness and described a static analysis
530
methodology for verifying a design against this metric.
Special modeling issues associated with long intercon-
nect were dixussed. Several future issues were noted
in the course of the discussion.
7 Acknowledgements
The authors gratefully acknowledge H. Smith and
D. Becker for helpful discussions about power supply
noise and for providing the data in Figure 4. The au-
thors also acknowledge C. Visweswariah for a careful
reading of the paper.
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