Noise and Jitter in CMOS Digitally Controlled

Delay Lines
Mónica J. FigueiredoAB, Rui L. AguiarB
A
Instituto Politécnico de Leiria, Escola Superior de Tecnologia e Gestão
B
Universidade de Aveiro, Dpt. Electrónica e Telecomunicações / Instituto de Telecomunicações
Email: monicaf@estg.ipleiria.pt, ruilaa@det.ua.pt

Abstract— Analysing the impact of noise sources on the In this paper, the relationship between design parameters
random instantaneous delay of a basic CMOS delay element is of delay circuits and the output jitter, noise induced, will be
important for understanding the performance of systems that analyzed. In section II a brief review of noise sources in
employ them, like voltage controlled delay lines or buffered CMOS digital circuits will be presented. The relationship
clock distribution networks. This paper presents a model for between noise and jitter in a basic CMOS delay element will
the analysis of noise induced jitter in CMOS delay cells and be modeled in section III. In section IV, a theoretical study
delay lines. Because the increasing switching noise levels is on the design of digitally controlled delay lines and the
becoming a serious impairment to the reliable use of analogue impact of circuit’s architecture in noise induced jitter is
controlled devices inside high frequency digital VLSI circuits, given. Section V provides conclusions.
this work focus primarily on digitally controlled delay lines.
For these circuits, the output capacitance and drivability of
delay elements are key parameters for the design of low jitter II. NOISE SOURCES IN CMOS DIGITAL CIRCUITS
delay lines. Simulation results are presented for a 0.35µm Physical noise arises from the discreteness nature of
CMOS technology. electronic charge and from the stochastic nature of the
electronic transport process. However, digital circuits are not
I. INTRODUCTION only subjected to physical noise; they create an additional
Noise has become a problem in the design of digital noise by virtue of their switching operation and the current
integrated circuits of comparable importance to area, timing, changes thus induced.
and power because of four main reasons: increasing
interconnect densities, faster clock rates, more aggressive use A. Physical Noise in CMOS Devices
of high performance circuit families, and scaling threshold The most common types of physical noise in the
voltages [1]. Noise is one of the causes of perturbations on frequencies of interest of actual digital systems are: thermal;
the clock network that lead to clock jitter. Since noise events flicker; and shot noise. The most common expressions for
are typically random in nature they have a random effect on the drain current noise spectral densities are given in Table 1
jitter which, if greater than a certain threshold, may cause [2], where gm is the transconductance at the bias point, γ is a
incorrect operation of the circuit. As clock frequencies bias-dependent factor, q is the electron charge, ID is the
become higher and higher, timing jitter has increasingly forward junction current, and KF, AF and EF are fitting
tighter limitations, and thus electronic circuitry is parameters from the Spice2 flicker noise model.
increasingly affected by noise.
Table 1 - Drain current noise spectral density
Delay elements are circuits with many applications in
VLSI circuits for clock generation, distribution and Thermal Noise σ I thermal = 4k BT γg m
synchronization. They are used in digital delay-locked loops
σ I flic ker = K F ( I DS )
AF
(DLLs), digitally controlled oscillators (DCOs), buffered Flicker Noise Cox L2eff f EF
clock distribution networks, and deskew circuits. In the
above mentioned applications, the delay element is one of Shot Noise σ I shot = 2qI D
the crucial components and its precision directly affects the
performance of these circuits. Delay can be controlled by
either analog or digital means. Although analog control has B. Circuit’s Noise
been widely used in the past and is still commonly used for Besides noise generated by elements, other sources of
its performance and simplicity, the increasing noise levels in noise exist at circuit level. Circuit’s noise may be classified
digital circuits have been driving the use of all digital as: power supply; substrate; and coupling noise (crosstalk).
architectures, which are traditionally seen as better in terms Crosstalk (both capacitive and inductive) and substrate noise
of noise. However, technology evolution has changed are typically addressed proactively or by repair schemes.
somewhat this picture and noise is now a problem even in Proper floorplanning, layout and routing can minimize their
purely digitally controlled designs. effects, and as thus they will not be addressed in this paper.

1-4244-0395-2/06/$20.00 ©2006 IEEE. 1356

 Power supply noise is usually classified as switching σ2I = ( 4k BT γζ + 2q ) ( I n sat + β I p sat ) (3)
noise or IR-drop noise. The former is produced by the
simultaneous switching of off-chip drivers and internal This current noise integrates on the load capacitor (CL)
circuits, while the last reflects the variations due to the
over a time window of width td to form a voltage ∆vn that
average current demands over the chip. Both affect the clock
modulates the time of the threshold crossing. Thus, the load
uncertainty, degrading system timing. Modeling these noise
capacitor filters out the high noise frequency components.
sources in large digital circuits is not a trivial task as they
The voltage noise power can therefore be modelled as being
depend on the circuit’s switching activity, parasitics
proportional to the load reactance multiplied by the total
coupling, package inductance, etc. An upper limit for the
noise current variance, as shown in (4).
switching noise has been derived in [3] and is presented in
(1), where Csw is the total chip switching capacitance, Cd is 1 td
the parasitic capacitance between power and ground, tsw is ∆vn = ∫ in ( t ) dt ⇒ ∆vn 2 ≈ σ2I ( ωCL )2 (4)
the transition time of the switching node and L is the C 0

effective inductance in the current path. Also, it is possible to

subtract a random voltage drop (∆VIR) to Vdd in this equation, B. Basic Delay Cell Jitter Model
in order to account for the random supply IR-drop. Based on the output voltage noise model, the white noise
induced jitter variance may be written following the FPT
∆vswmax = (Vdd ( Csw 2 ) ) ( 2C d + Csw + ( tsw
2
6L ) ) (1) model, and is shown in (5). It is interesting to notice that it
does not depend on the load capacitance. In fact, a higher
capacitance reduces the signal slew rate which increases
III. TIMING JITTER IN DELAY CELLS noise sensibility but on the other hand it integrates better the
When developing a model for calculating timing jitter noise current.
from a given total noise spectral density, two different
 C  ( 4k BT γζ + 2q ) ⋅ ( I n sat + β I p sat )
2
approaches have been followed in literature: the first passage 2 2
time model (FPT) [4], and the last passage time model (LPT) σ = ∆vn  L  = (5)
ω2 ⋅ ( I n sat − βI p sat )
w 2
[5]. The FPT model applies to ideal inverter cells, assuming  IL 
that subsequent stages in a series of gates begin to switch
exactly when their input crosses a particular voltage for the Switching noise also contributes to the total output jitter,
first time. Therefore, a given amount of voltage noise will but its influence is mostly determined by the output load
produce a variance in the time domain given by the slew rate capacitance. In fact, the switching noise induced jitter at the
of the input signal as shown in (2). inverter output may be written following the FPT model (6),
where the influence of a high output capacitance and short-
∆t 2 = ∆ v 2 ⋅ ( C L I L )
2
(2) circuit current (a high β) in its magnitude is significant.

( (I − β ⋅ I p sat ) )
2
In the LPT model it is assumed that only when the input σ 2sw = ∆vsw 2 ⋅ CL n sat (6)
crosses a particular voltage for the last time does the next
logic stage switch permanently. Although the LPT model Flicker noise introduces a low frequency random
gives results which differ from the FPT model by a non- component in the charging and discharging currents of the
negligible amount, no practical measurements have been delay cell. Due to its spectral content, we may assume that
published to prove its higher accuracy. Thus, the simplest during the threshold crossing it is virtually constant, and thus
FPT model has been chosen for this work. introduces only a deviation on the output slew rate (Fig. 1),
which will create a timing error during the threshold
A. Basic Delay Cell Noise Model crossing. This error is given in (7), where σflk is the standard
The basic and most widely used delay element in digital deviation of the drain noise current due to flicker noise.
circuits is the static CMOS inverter with a fixed or variable
output load. During a high to low transition at its output,
there are two current flows: the discharge current through the
NMOS transistor, and a bias-dependent current through the
PMOS transistor. If the input slew rate is lower or equal to
the output slew rate, both transistors will be in saturation
during the threshold crossing and the short-circuit current
can be significant. In this situation the output noise current
variation will be the sum of the individual PMOS and Figure 1. Charge current modulation due to flicker noise
NMOS noise current variances. Around the threshold
crossing the output noise variance will depend on the PMOS
and NMOS saturation currents, as shown in (3). Here, β is a CLVdd  1 1  σ flk ⋅ (1 + β ) CLVdd
∆tn =  − ≈ (7)

 I L flk I L  2 ( I n sat − βI p sat )
2
fit parameter to scale down the PMOS current and ζ relates 2
the drain currents to the transistor’s transconductance.

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 Flicker induced jitter variance may now be given as a Now, if we define δ as correlation parameter between 0
function of the flicker noise current spectral density (8). It and 1, the total jitter variance may be given by (11). This
shows that flicker noise induced jitter is highly dependent on result shows us that if there is a high correlation between the
the output capacitance and also on the short-circuit current. noise sources that induce the timing jitter, the total output
variance will be proportional to N*(N-1). However, if the
(
σ2flk = CLVdd (1 + β ) 2 ( I n sat − βI p sat ) ) ⋅σ
2 2 2
I flk (8) correlation is low, it will be only N times the intrinsic cell
variance, which is a significant reduction for large N.
Because these jitter components arise from uncorrelated σ2N = δ ( σ2N ) + (1 − δ ) ( σ2N ) = N σcell
2
(1 + gmc2 ) +
noise sources, the total jitter variance at the output of a corr un
(11)
delay cell may be given as the sum of the white, switching + δN σ 2
( N − 1) (1 + g 2
) + 2 Ng 
and flicker jitter variances, given in (5), (6) and (8).
cell  mc mc 

IV. TIMING JITTER IN DELAY LINES The number of delay elements (N) in the line depends on
the required total delay and may be calculated using a simple
Fixed delay elements may be cascaded and associated to delay model for the basic inverter [7]. In this model, different
some sort of multiplexer to create a delay line. The number propagation and transition times are considered for the high-
of the delay stages which the input clock signal goes through to-low and low-to-high transitions, depending essentially on
determines the total amount of delay. If the output load of the the load and on the transistors drivability. To build a SCI
basic inverter, or its drive current, can be digitally adjusted, it with the same delay, the total switched load capacitance
is possible to control the output slew rate and thus create a should be M times bigger than the unit inverter load
variable delay through the inverter. This may be done with a capacitance. Fig. 3 shows the SCI model used, with
digital shunt capacitor (SCI) inverter or with a current neighbour sections driven in phase opposition to achieve
starved delay element. However, when maximum speed and balanced rise and fall times. The number M was calculated
power consumption are of concern, SCI is generally using the same propagation time expressions used for the
preferred [6]. In Fig. 2 a delay line with fixed elements delay line, and the result in (12) was obtained.
associated to a multiplexer and a SCI are shown.
M = N −4 ⇔ M ≈ N , N >> 1 (12)

Figure 2. Digitally controlled a) delay line; b) SCI

In a delay line, if full cell switching is initiated when the Figure 3. Shunt capacitor delay line with two bufered elements
input voltage reaches a certain threshold, the voltage noise of
one stage simply shifts the timing of the beginning of the Because binary weighted shunt capacitor inverters may
next. For independent noise sources, the total jitter variance achieve the same phase ranges as delay lines with fewer
at the end of N stages is just N times the individual variances elements, there is a general belief that they produce less jitter
induced by noise sources. However, the noise at the output of as there is no jitter amplification. However, the delay control
the first cell will be amplified by the second cell in these lines is based on a variable slew rate, which affects
transconductance gain, filtered by its output capacitance and the signal’s sensibility to noise. In fact, while noise currents
sum up with its intrinsic noise. The jitter amplification are integrated by the circuit’s load capacitance, power supply
parameter (gmc) will therefore depend on the output noise is superimposed on the output voltage and jitter at the
capacitance (CL), on the inverter transconductance parameter cell’s output will be proportional to the total noise voltage
multiplied by the signal slew rate (13). Because the load
(gm) and on the noise frequency (ω), as shown in (9).
capacitance is MCL, flicker and switching noise induced jitter
will be M2 times higher than jitter at the output of a basic
= X C2 ⋅ σ2I amp = ∆vin2 ⋅ ( g m ωCL ) = ∆vin2 ⋅ g mc
2 2 2
∆vout (9)
delay cell, while the high load capacitance is responsible for
At the output of a delay line with N identical stages jitter the reduced contribution of the white noise current to the
variance is given by the sum of the intrinsic and amplified overall output noise voltage.
noise induced jitter variances, if they are not correlated.
⋅ ( MCL I L ) = σw2 + M 2 ⋅ ( σ2flk + σ 2sw ) (13)
2
However, jitter components may be correlated as both are σ2SCI = ∆vout
2

partially generated by power supply noise which affects

neighbouring cells equally and simultaneously. Therefore, These results have been drawn considering the same β
the total variance will be higher and a bound can be given by parameter in both circuits, which is not true. When the delay
the sum of the individual standard deviations when jitter is large in a SCI, the output slew rate is lower than the input
components are assumed to be totally correlated (10). slew rate and there is no short-circuit current during the
threshold crossing because one of the transistors is already at
(σ ) 2
N corr = N ⋅ ( σ 2N )un + 2 N 2 σ2cell g mc (10) cut-off during that period. This means that for a large delay
the parameter β will be ≈0 and it will increase for smaller

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delays, i. e., white noise induced jitter is smaller for higher factors may be tolerated if the output load capacitance is
delays in a SCI. This is exactly opposed to what happens in a increased. However, the usage of high output loads degrades
delay line, where jitter grows with the length of the line due the slew rate, which increases the range of noise frequencies
to noise accumulation and amplification. Thus, white noise that may be amplified and also the noise to jitter conversion.
induced jitter at the output of a delay line will always be
equal or higher than at the output of a SCI (Fig. 4). gmc = gm ω⋅ k ⋅ CL ≈ ( µ n 8ω⋅ k ⋅ L2 ) ⋅ (1 + β ) (15)

It should be remembered that we are only concerned with

the high frequency noise spectrum, as low frequency noise
( )
→ σ w2 SCI
current is not amplified by the delay cells. In fact, if the noise
period is higher than the signal’s rise/fall time, it will only
→ (σ ) 2
w Delay Line
have influence on the signal’s output slew rate. Thus, the
jitter amplification parameter is meaningful only for noise
frequencies above fx, which is the inverse of the mean
signal’s rise/fall time. Equation (16) was derived from the
Figure 4. Jitter amplification factor as a function of output capacitance rise/fall time equations given in [7], where AN and AP are
parameters which depend on the transistor’s drain saturation
To further compare both lines it is interesting to find out voltage. It shows that for the noise frequency band of interest
how many cells (N) should a delay line have in order to the amplification parameter is typically lower than unity.
exhibit a higher jitter than the SCI with NCL (N=M) of total This means that the delay line will perform better than a SCI,
capacitance. In this work, the multiplexer delay and induced even for non negligible noise correlation factors.
jitter has not been considered as it depends on the specific
circuit implementation. Also, we will only focus on flicker µ n CoxVDD ( I D 0 P AN + I D 0 N AP )  W 
and switching noise because white noise induced jitter does gmc < ⋅  ⋅ (1 + β ) (16)
not depend on the load. Using (12) and comparing (11) to 8π ⋅ I D 0 P I D 0 N L 
(13), the number N was found to be given by (14). This
equation states that there is no positive integer N for which V. CONCLUSIONS
the output jitter in a delay line is bigger than jitter at the
In this paper an analytical study of noise induced jitter in
output of a SCI as long as the jitter amplification parameter
two different CMOS digitally controlled delay lines is
is smaller than the condition shown in (14).
presented. Jitter induced by thermal noise at the output of a
basic inverter has been shown not to depend on the output
( δ − 1) ⋅ (1 + g mc2 ) 1 load capacitance. However, a SCI exhibits less jitter than a
N< , g mc < −1 (14)
δ ⋅ (1 + g mc ) − 1
2
δ delay line because there is only one transistor in conduction
during the threshold crossing. On the contrary, white noise
Considering an output load equal to kCL, the jitter induced jitter in a delay line is higher due to short-circuit
amplification parameter can be written as given in (15), for currents and grows with the selected delay. It has also been
Ln=Lp=L, Wp=3Wn=3W and µn=3µp. For a CMOS 0.35µm shown that the output capacitance determines the switching
technology, its magnitude is plotted in Fig. 5 as a function of and flicker noise induced jitter but has a negligible influence
the noise frequency spectrum, for different load capacitances on the jitter amplification phenomenon.
(k) and with the indication of different correlation factors (δ).
We assume that the noise frequencies that may be amplified REFERENCES
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