Department of

Electronics & Communication Engineering

Manual and Observation Book
Integrated Circuits Lab
By
K!rid"ar #a$u
%%%engglabsblogspotcom
K!rid"ar #a$u %%engglabsblogspotcom
Department of
Electronics & Communication Engineering
Integrated Circuits Lab
&ame of t"e student ' (((((((((((((((((((((((((((((((((((((((((((
Class ' ((((((((((((((((((((((((((((((((((((((((((((
#oll &o ' ((((((((((((((((((((((((((((((((((((((((((((
!emester ' ((((((((((((((((((((((((((((((((((((((((((((
)cademic *ear ' ((((((((((((((((((((((((((((((((((((((((((((
+
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I&,E-#),ED CI#C.I,! L)B
LI!, O/ E01E#IME&,!
2 ME)!.#EME&, O/ O13)M1 1)#)ME,E#!
+ O13)M1 CO&/I-.#),IO&! ' I&4E#,I&- & &O&3 I&4E#,I&-
)M1LI/IE#5 !.MMI&- )M1LI/IE# )&D 4OL,)-E /OLLO6E#
7 DE!I-& O/ I&,E-#),O#5 DI//E#E&,I),IO# CI#C.I,! .!I&- O13)M1
89):;2C<
; DE!I-& O/ /I#!, O#DE# LO631)!! & =I-=31)!! B.,,E#6O#,=
)C,I4E /IL,E#!
> DE!I-& O/ /I#!, O#DE# B)&D31)!! B.,,E#6O#,= )C,I4E /IL,E#
? DE!I-& O/ MO&O!,)BLE 5 )!,)BLE M.L,I4IB#),O# )&D !C=MI,,
,#I--E# CI#C.I,! .!I&- O13)M1 IC 9):;2C
: MO&O!,)BLE M.L,I4IB#),O# .!I&- IC >>> ,IME#
@ )!,)BLE M.L,I4IB#),O# .!I&- IC >>> ,IME#
A IC #E-.L),O# LI&E )&D LO)D #E-.L),IO& C=)#EC,E#I!,IC!
2B DE!I-& O/ )#I,=ME,IC CI#C.I,!
22 DE!I-& O/ CODE CO&4E#,E#!
2+ !,.D* O/ DECODE# )&D I,! )11LIC),IO&!
27 !,.D* O/ M.L,I1LE0E# )&D I,! )11LIC),IO&!
2; /LI1 /LO1! )&D I,!C CO&4E#!IO&
2> DE!I-& O/ !*&C=#O&O.! CO.&,E# 8 .!I&- /LI1 /LO1! )&D
!,)&D)#D IC CO.&,E#!<
2? DE!I-& O/ )!*&C=#O&O.! CO.&,E#
2: DE!I-& O/ !=I/, #E-I!,E#! )&D #I&- CO.&,E#!
2@ 1=)!E LOCKED LOO1 C=)#EC,E#I!,IC! )&D )11LIC),IO&!
2A DI-I,)L ,O )&)LO- CO&4E#,E#!
7
K!rid"ar #a$u %%engglabsblogspotcom
Department of
Electronics & Communication Engineering
Integrated Circuits Lab
&ame of t"e student'
Class BE'
#oll &o' )cademic *ear'
I&DE0
!l
&o
&ame of t"e EDperiment Date
Conducted
Initials of staff
!l &ame of t"e EDperiment Date Initials of staff
;
K!rid"ar #a$u %%engglabsblogspotcom
&o Conducted
>
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1. OP AMP PARAMETERS
AIM:
,o measure 8a< Input Bias current 8b< Input offset current 8c< Input offset voltage
and 8d< !le% rate for a given O1 )M1
APPARTUS REQUIRED:
2 O1 )M1 9):;2C IC 2no
+ #esistors' >ME 3 2no5+ME 3 +no52BBE 3 2no
7 Capacitors' BB29f F +no
; Dual #egulated 1o%er !upply 2no
> C#O 2no
? Digital Multimeter 2no
: Breadboard 2no
@ Connecting 6ires
THEORY:
O13)M1 is an important linear IC %"ic" is used in a number of electronic
applications suc" as )udio & #adio communication5 Medical Electronics5
Instrumentation Control5 etc ,"e circuit sc"ematic of an O13)M1 is s"o%n in t"e figure
It "as t%o input terminals and one output terminal and t%o supply terminals ,"e terminal
%it" a minus 83< is called as inverting terminal and t"e one %it" plus 8G< is called as non3
inverting terminal ,"e :;2 IC is an internally compensated O13)M1 )n O13)M1 IC
"as @ pins out of %"ic" > are basic terminals and t"e significance of ot"er terminals
varies %it" t"e type of t"e O13)M1 ,"e pin diagram of a DI1 :;2 IC is s"o%n as
follo%s'

Fig: Pin Diagram of IC A 741C.
/airc"ild "as originally manufactured t"e 9) :;2 IC but a number of manufacturers
like &ational semiconductor 8LM :;2<5 Motorola 8MC2:;2<5 ,eDas Instruments
8!&>+:;2<5 !ignetics 8&>:;2<also produced :;2 IC
?
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PROCEDURE:
a! M"a#$r"m"n% of In&$% 'ia# C$rr"n%'
8i< ,o measure inverting input bias current5 setup t"e circuit as s"o%n in t"e circuit
and measure t"e output voltage 4o substitute t"e values of 4o &# in t"e
follo%ing eHuation and obtain I
G
B
I
G
B I 4o J #
Fig: M"a#$r"m"n% of I()
8i< ,o measure t"e non3inverting input bias current 5 setup t"e circuit as s"o%n
and
measure t"e output voltage 4o and substitute t"e values of 4o &# in t"e
follo%ing eHuation and obtain IBG
IBG I 4o J #
Fig: M"a#$r"m"n% of I(*
:
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'! M"a#$r"m"n% of off#"% +$rr"n%'
Make connections as s"o%n in t"e /ig .se eHual resistors to cancel t"e
effect on t"e bias current
,"e offset current is given by
IioI 4oJ#f
Fig: M"a#$r"m"n% of Iio
+! M"a#$r"m"n% of in&$% off#"% ,o-%ag"' Connect t"e circuit as s"o%n in t"e
figure ,"e effect of t"e bias current is compensated by #c ,"e output voltage
4o can be eDpressed as follo%s
4oI 82G #f J#2 < 4io
Fig: M"a#$r"m"n% of .io
Measure t"e output voltage 4o using voltmeter and find 4io from t"e above
eDpression by substituting t"e values of #f5 #2 & 4io

/! M"a#$r"m"n% of #-"0 ra%":
@
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8i< Make t"e connections as s"o%n in t"e figure
Fig: M"a#$r"m"n% of S-"0 Ra%"
8ii< )d$ust t"e input sine %ave to get 2 4 peak3to3peak sine %ave at output
4o
4o I 2 4p3p at 2 K=K
8iii< !lo%ly increase t"e input signal freHuency until t"e output gets
distorted
8iv< Calculate t"e sle% rate !#I +Lf4m vJ9s5 %"ere 4m is t"e peak output
amplitude in volts and f is t"e freHuency in =K
8v< &o% apply sHuare %ave as an input of 2 4p3p
8vi< Increase t"e input freHuency slo%ly until t"e output is $ust barely a
triangular %ave ,"en t"e sle% rate is ! # I M4o J M t vJ9s
6"ere M4o is t"e c"ange in t"e output voltage amplitude in volts
M t is t"e time reHuired for M4o in 9seconds
.I.A .OCE QUESTIO1S:
82< 6"at are t"e ideal c"aracteristics of an O1 )M1N
8+< 6"at do you mean by t"e follo%ing termsN =o% to $ustify t"emN
8a< 4irtual !"ort 8b< 1artial O1 )M1 circuit
87< Define t"e follo%ing terms'
8a< Input Offset 4oltage
8b< Input Bias current
8c< CM##
8d< !le% #ate
2. OP)AMP CO1FI3URATIO1S
AIM: 8a< ,o design and verify t"e O13)M1 configurations
A
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i< Inverting )mplifier
ii< &on3inverting )mplifier
8b< ,o design and verify t"e follo%ing applications of O13)M1
i< !ummer ii< !ubtractor iii< 4oltage /ollo%er
APPARATUS REQUIRED :)
-eneral 1urpose IC ,rainer Kit
Dual #egulated 1o%er !upply 8B32>4<
Digital Multimeter
C#O
9):;2C IC
#esistors' 2kE 3 ; no52BkE 3 2&O
Connecting %ires
THEORY:
O13)M1 is an important linear IC %"ic" is used in a number of electronic
applications suc" as )udio & #adio communication5 Medical Electronics5
Instrumentation Control5 etc ,"e circuit sc"ematic of an O13)M1 is s"o%n in t"e figure
It "as t%o input terminals and one output terminal and t%o supply terminals ,"e terminal
%it" a minus 83< is called as inverting terminal and t"e one %it" plus 8G< is called as non3
inverting terminal ,"e :;2 IC is an internally compensated O13)M1 )n O13)M1 IC
"as @ pins out of %"ic" > are basic terminals and t"e significance of ot"er terminals
varies %it" t"e type of t"e O13)M1 ,"e pin diagram of a DI1 :;2 IC is s"o%n as
follo%s'
Fig: Pin Diagram of IC A 741C
/airc"ild "as originally manufactured t"e 9) :;2 IC but a number of manufacturers like
&ational semiconductor 8LM :;2<5 Motorola 8MC2:;2<5 ,eDas Instruments 8!&>+:;2<5
!ignetics 8&>:;2<also produced :;2 IC
SUMMER:
2B
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,"e follo%ing figure s"o%s t"e summer circuit using Operational )mplifier 8:;2 IC<
%"ic" is useful for adding t%o inputs of same amplitude or different amplitudes 8)C
signals or DC signals<
Eo I #f O e2 J #2 G e+ J #+ P
%"ere If I I2 G I+
if #f I #2 I #+5 t"en EBI e2G e+
PROCEDURE:
2 )pply t%o different signals 8!ineJ !HuareJ,riangle %aveforms or DC 4oltages< to t"e
,%o inputs iJp2 & iJp+
+ -ive t"e input signal amplitude of >4 & +4 O# +4 & 74 and observe t"e Output
4oltage signal amplitude
7 4erify t"e output at pin ? of t"e :;23summer circuit by varying t"e input voltages
; &otice t"at t"e output is al%ays eHual to t"e sum of t"e t%o inputs

SU(TRACTOR:
Operational )mplifier is also useful as a subtractor t"at means to subtract one signal from
anot"er signal5 %"ic" are applied to t"e inputs of t"e Operational )mplifier and is s"o%n
in /igure +
22
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PROCEDURE:
2 )pply t%o different sine %ave signals or DC signals to t"e inputs of subtractor of
different amplitudes #efer figure +
+ -ive t"e input signal amplitude of >4 & +4 O# +4 & 74 and observe t"e
Output voltage signal amplitude
7 4erify t"e output at pin ? of t"e :;2 !ubtractor circuit by varying t"e input
voltages
; &otice t"at t"e output is t"e true replica of t"e subtraction value of t"e t%o
inputs
I1.ERTI13 AMP4IFIER:
Inverting )mplifier is t"e one t"at s"ifts t"e p"ase of t"e input signal by 2@B
o
,"e circuit
of t"e Inverting )mplifier using O13)M1 :;2 IC is s"o%n in t"e figure %it" negative
feedback =ere t"e input is provided to t"e inverting terminal of t"e O13)M1 ,"e output
voltage eHuation is given as
4o I 3 #f J #2 84i <
PROCEDURE:
2 )pply t"e sine %ave as t"e input to t"e inverting amplifier circuit
+ !et t"e input amplitude to 2 4 peak3to3peak and freHuency of 2 K=K
7 Observe t"e output at pin ? of t"e :;2 IC
; &otice t"at t"e output %aveform is a s"ifted version of t"e input signal by 2@B
o

> 1lot t"e %aveforms on t"e grap" s"eet

? /ind t"e t"eoretical output voltage using t"e eHuation 4o I 3 #f J #2 4i
: 4erify t"e same %it" practical values
2+
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1O1)I1.ERTI13 AMP4IFIER:
In t"is mode %e give t"e input to t"e non3inverting terminal of t"e operational amplifier
!o5 t"ere is no p"ase difference bet%een t"e input and t"e output ,"e figure s"o%n
belo% is t"e circuit for non3inverting amplifier %it" negative feedback using O13)M1
:;2 IC
PROCEDURE:
2 )pply t"e sine %ave as t"e input to t"e inverting amplifier circuit
+ !et t"e input amplitude to B> 4 peak3to3peak and freHuency of 2 K=K
7 Observe t"e output at pin ? of t"e :;2 IC
; &otice t"at t"ere is no p"ase difference bet%een t"e input and t"e output
%aveforms
> 1lot t"e %aveforms on t"e grap" s"eet
? /ind t"e t"eoretical output voltage using t"e eHuation 4o I 82 G #f J #2 < 4i
: 4erify t"e same %it" practical values
.O4TA3E FO44O5ER:
4oltage /ollo%er is an amplifier of unity gain and t"e output follo%s t"e input voltage
,"e figure s"o%n belo% is t"e circuit for 4oltage /ollo%er using Operational )mplifier
:;2 IC 4oltage /ollo%er circuit can be used as a buffer %it" "ig" input impedance and
lo% output impedance ,"is a modified version of &on3inverting O13)M1 configuration
obtained by simply s"ort circuiting t"e output and non3inverting terminal 8#f I B<
27
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PROCEDURE:
2 )pply a sine %ave of 2Bm4 amplitude
+ -ive t"e input voltage signal freHuency from 2B =K to 2M=Kand note do%n t"e
output voltage amplitude
7 Calculate t"e gain from t"e value and dra% freHuency response c"aracteristics
%it" t"ese values
; &o% set t"e #L to any ot"er value and follo% t"e above procedure and dra% t"e
/reHuency response plots
2;
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2>
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6. DESI31 OF I1TE3RATOR A1D DIFFERE1TIATOR CIRCUIT USI13
OPAMP IC 741
AIM:
8a< ,o design and verify t"e %orking of an Integrator and differentiator circuit
using op3amp IC :;2
8b< Observe t"e output %aveforms by giving different input signals
APPARATUS:

!&O &ame Of t"e component #ange Qty
2
+
7
;
>
?
:
@
/reHuency -enerator
C#O
IC :;2
#esistors
Capacitors
Dual #egulated 1o%er !upply
Connecting %ires
Breadboard
+BM=R
2kE
2BkE
2BBkE
BBB29f
B29f
2
2
2
2
2
2
2
2
2
THEORY:
2?
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I1TE3RATOR:
Integrating circuit produces an output voltage %"ic" is proportional to t"e area
8amplitude multiplied by time< contained under t"e input %aveform Integrator is an
important configuration t"at is freHuently used in analog computers
,"e basic Integrator circuit is s"o%n in t"e fig %"ere by replacing a capacitor as
feedback element instead of #f in t"e inverting O13)mp configuration ,"e circuit
may be used to integrate t"e input voltage or current !uc" circuits eDtremely useful
in !ignal processing5 Computing and signal generating devices )s t"e c"arge passes
t"roug" t"e summing point !5 it is accumulated on t"e capacitor and a potential is
developed at t"e output terminal %it" t"e summing point at ground potential
)ssuming ideal O13)mp performance5 %e "ave
84i34s<J# I I and 4s34oI2Jc S I dt I 2J8#C<S 84i34s< dt
&o% 4sI34oJ) %"ic" tends to B since gain ) is very large
=ence 4o8t< I 32J8#C<S4idt
,"e above eHuation s"o%s t"at t"e output voltage is t"e integration of t"e input
voltage %it" respect to time
CIRCUIT DIA3RAM:
PROCEDURE:
2 Connect t"e circuit as per t"e circuit diagram on to t"e breadboard
+ !%itc" on t"e regulated po%er supply
2:
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7 )pply a sHuare %ave input of amplitude 24 at a freHuency of 2K=K
; Observe & sketc" t"e output %aveform using C#O
> 4erify %it" t"e eDpected t"eoretical %aveform
? Observe & sketc" t"e %aveforms for different input signals
DIFFERE1TIATOR:
) differentiating circuit is employed to produce output amplitude proportional to t"e
rate of c"ange of t"e input voltage ,"e output voltage is a positive DC level during
t"e time t"e input is negative3going and a negative voltage level %"ile t"e input is
positive going ie5 a sHuare %ave !ince t"e non3inverting terminal is eart"ed5 !
8!umming point< is also at t"e ground potential ,"e current Ic t"roug" t"e capacitor
is given by
Ic I
,"e current If t"roug" t"e feedback resistor is 84o J #f< !ince t"e Op3amp is assumed
to be ideal5 no current flo%s into t"e Op3)mp
,"us t"e output voltage is 8F#fC< times t"e derivative of t"e input voltage
CIRCUIT DIA3RAM:
2@
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PROCEDURE:
2 Connect t"e circuit as per t"e diagram
+ !%itc" on regulated po%er supply
7 )pply sHuare %ave input of amplitude 24 at a freHuency of 2 K=K
; Observe and sketc" t"e output %aveform using C#O
> #epeat steps ; & > for different freHuencies
? 4erify t"e obtained %aveform %it" t"eoretical %aveform

2A
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4. ACTI.E FI4TERS
I1TRODUCTIO1:
In electronic systems t"e desired signal is obscured by t"e noise !ignals are
distinguis"ed by t"eir freHuency c"aracteristics and t"e eDtraction of a signal from
un%anted signals can be accomplis"ed by some form of freHuency selective circuit or
filter /ilters can be constructed using only passive components ie5 resistors5 capacitors
and inductors but active filters %"ic" use active gain block5 toget"er %it" a resistor3
capacitor net%ork offer follo%ing main advantages'
8i< ,"ey eliminate t"e need for inductors %"ic" are large5 "eavy and
costly elements particularly in audio freHuency range
8ii< ,"ey provide gain & eDcellent isolation properties 8"ig" input
impedance and lo% output impedance<
8iii< )ctive filters are readily compatible %it" ICs due to lack of inductors
+B
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8iv< Due to eDcellent isolation property5 active filters can be designed and
tuned independently %it" minimal interaction
8v< ,"e range of t"e Huality factor 8Q< possible for active filters eDtends
up to fe% "undreds
,"ere are some limitations to active filter tec"niHues
8i< !tability considerations limit t"e use of most of t"e filters belo% 2BB K=K
8ii< ,"e selectivity and center freHuency are often very sensitive functions of gain
of Op3amp or absolute values of feedback components
8iii< ,o obtain t"e reHuired absolute tolerance remote control5 active filters reHuire
additional process steps5 suc" as use of t"in3film or "ybrid tec"nology
In certain applications5 it is Tpossible to overcome some of t"ese limitations of active
filters using alternate design tec"niHue One specific eDample of suc" tec"niHue is use of
a 1"ase Locked Loop 81LL< system to obtain desired selectivity function
Depending on t"e number of capacitors5 %e "ave first3order5 second3order and
"ig"er order filters Depending on t"e circuit configurations5 %e "ave Lo% pass filter
L1/<5 =ig" 1ass /ilter 8=1/<5 Band 1ass /ilter 8B1/< and Band Elimination /ilter 8BE/<
Depending upon t"e type of t"e circuit used5 %e "ave 4C4! 84oltage Controlled 4oltage
!ource< filters5 infinite gain multiple feedback filters and infinite gain state variable
feedback filter Depending on t"e met"od of design5 %e "ave Butter%ort" /ilter5
C"ebys"ev /ilter5 Bessel /ilter5 etc
Mainly t"e selection criterion rests on a costJperformance comparison bet%een t"e
different possible circuit configurations ,"e gain block selected is an operational
amplifier for filter realiKation
Basically an electric filter is a freHuency selective circuit t"at passes a specified band of
freHuencies and blocks or attenuates signals of freHuencies outside t"e band /ilters may
be classified in t"e follo%ing %ays'
8i< )nalog or Digital /ilters
8ii< 1assive or )ctive /ilters
8iii< )udio or #adio /reHuency /ilters
)ctive filters are almost used in all t"e fields of electronics and communication suc" as
#adio5 telep"one5 radar5 space satellites and medical eHuipment
+2
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4. FIRST ORDER 4O5 PASS (UTTER5ORTH FI4TER
AIM: ,o design t"e first order Lo% pass Butter%ort" filter for t"e given specifications
)nd obtain its c"aracteristics using Op3)mp
APPARATUS REQUIRED:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 Op3)mp IC U) :;2CJ 7>2 B2
+ #esistors 2B KE B7
7 Capacitors BB2 Uf B2
;
>
1otentiometer
-eneral purpose Ic
,rainer kit
+B KE
3
B2
B2

THEORY:
) first order lo%3pass Butter%ort" filter t"at uses an #C net%ork is s"o%n in t"e figure
,"e Op3)mp is used in t"e non3inverting configuration =ence it s"all not load t"e #C
net%ork ,"e resistors #f and #2 determine t"e voltage gain of t"e filter
,"e magnitude of t"e voltage gain of t"e lo% pass filter can be %ritten as
++
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,"e p"ase angle of lo%3pass filter is given by
,"us t"e lo%3pass filter "as a constant voltage gain )/ from "ig" cut3off freHuency fC )t
fC t"e gain is B:B: )/ and after fC it decreases at a constant rate %it" an increase in t"e
freHuency 6"en t"e freHuency is increased to 8one decade< t"e gain is divided by 2B It
means t"at t"e gain decreases +B dBJ decade Eac" time t"e freHuency is increased by 2B
=ence t"e rate at %"ic" t"e voltage gain rolls of after fC is +BdBJdecade or ?dBJoctave
,"e octave means a t%o fold increase in freHuency
CIRCUIT DIA3ARM:
DESI31 STEPS:
2 C"oose upper cut3off freHuency f=
+ !elect a value of C less t"an or eHual to 2 Uf
7 Calculate t"e value of # using # I 2J+Lfc
; /inally select t"e values of #/ and #2 depending on t"e desired pass band gain )/
using t"e gain eHuation
PROCEDURE:
2 /ollo% t"e design procedure and find t"e values of #/ and #2 and t"e
potentiometer by c"oosing t"e gain5 cut3off freHuency f= and capacitor value&o%
connect t"e circuit %it" t"e obtained component values as per t"e ckt diagram
+ )pply t"e )C signal as input of amplitude 245 +4or 74 peak3peak at t"e input
terminals of fiDed value
7 4ary t"e freHuency of iJp signal from 2B"K to 2M"K and note do%n value of oJp
signal amplitude 4o at freHuencies reHuired to plot t"e grap"
+7
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; /ind t"e ratio of 4o to 4i ie gain
> Dra% t"e freHuency response plot on semilog grap" s"eet
TA(U4AR CO4UM1:
Input signal amplitude 4i I
Frequency
(Hz)
V
o

(volts)
Gain = V
o
/
V
i
Gain (dB) = 20 log
(Vo /V
i
)
Fig: Fr"7$"n+8 R"#&on#" +9ar"+%"ri#%i+# of fir#% or/"r ($%%"r0or%9 4PF.
FIRST ORDER HI3H PASS FI4TER
AIM: ,o design t"e first order =ig" pass Butter%ort" filter for t"e given specifications
)nd obtain its c"aracteristics using Op3)mp
APPARATUS REQUIRED:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 Op3)mp IC U) :;2CJ 7>2 B2
+ #esistors 2B KE B7
7 Capacitors BB2 Uf B2
;
>
1otentiometer
-eneral purpose Ic
,rainer kit
+B KE
3
B2
B2
THEORY:
) first order =1/ is formed from t"e first order L1/ by interc"anging t"e components #
& C ) first order =1/ %it" a lo% cut3off is s"o%n in t"e figure
+;
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,"e output voltage is given by
6"ere )/ I 2 G 8#/ J #2< and fC I 2J8+V#C<
Magnitude of t"e voltage gain is given by
=ence =1/ is formed from L1/ by simply interc"anging # and C5 t"e design and
freHuency scaling procedures are also t"e same
CIRCUIT DIA3RAM:
DESI31:
)/ I 2 G 8#f J #2< and fL I 2J 8+V#C<
2 C"oose t"e lo%er cut3off freHuency fL
+ !elect a value of C less t"an or eHual to 2 Uf
7 Calculate t"e value of # using # I 2 J 8+VfLC<
; /inally select t"e values of #2 and #f depending on t"e value of desired pass3band
gain )/
EDample'
Design a "ig" pass filter %it" cut3off freHuency of 2 K=K %it" a pass band gain of +
!ol'
fL I 2 J 8+V#C<
Let C I BB2 f
+>
K!rid"ar #a$u %%engglabsblogspotcom
fL I 2K=K
# I 2>A KE
#eHuired gain )/ I + =ence #/ I #2 I 2B KE
PROCEDURE:
2 )t t"e input terminal apply a signal of 24 peak3to3peak Keep t"e value constant
+ 4ary t"e freHuency and measure t"e corresponding outputs
7 /ind t"e gain in dB
; Dra% t"e response curve
TA(U4AR CO4UM1:
Frequency
(Hz)
V
o

(volts)
Gain = V
o
/
V
i
Gain (dB) = 20 log
(Vo /V
i
)

:. (A1D PASS FI4TER USI13 OP)AMP
AIM:
,o study t"e first order Band3pass filter using :;2 Op3amp
APPARATUS:
2 Band3pass /ilter Kit
+ !ignal -enerator
7 C#O
; B&C probes and connecting %ires
CIRCUIT DIA3RAM:
+?
K!rid"ar #a$u %%engglabsblogspotcom
THEORY:
) freHuency selective electric circuit t"at passes electric signals of specified band of
freHuencies and attenuates t"e signals of freHuencies outside t"e band is called an electric
filter
)ctive filters use an Op3amp as t"e active element and resistors and capacitors as t"e
passive elements )lt"oug" t"e :;2 Op3amp %orks satisfactorily in t"ese filter circuits5
"ig" speed op3)mps suc" as LM72@ or ICL@B2: improve t"e filter performance t"roug"
t"eir increased sle% rates and "ig"er unity gain band3%idt"s
) filter %"ic" "as a pass3band bet%een cut3off freHuencies f= and fL suc" t"at f=WfL is
referred to as a band3pass filter )ny freHuency outside t"is pass band is attenuated
Basically t"ere are t%o types of band3pass filters' 82< 6ide band3pass filters 8+< &arro%
band3pass filters 6e %ill define a filter as a %ide band3pass filter if its figure of merit or
Quality factor QX 2B On t"e ot"er "and if QW 2B5 t"e filter is said to be narro% band3pass
filter ,"us Q is a measure of selectivity5 meaning "ig"er t"e value of Q5 t"e more
selective is t"e filter or t"e narro%er its Band%idt" 8B6< ,"e relations"ip bet%een Q5
t"e 73dB band%idt" and center freHuency fC is given by
Q I fCJ B6 I fCJ 8f= 3 fL<
/or t"e %ide band3pass filter t"e center freHuency fC can be defined as
fC I 8f=fL<
2J+
%"ere f= I =ig" cut3ff freHuency 8=K<
fL I Lo% cut3ff freHuency of t"e %ide3band filter8=K<
In a narro% band3pass filter5 t"e output voltage peaks at center freHuency
+:
K!rid"ar #a$u %%engglabsblogspotcom
) %ide band Fpass filter can be formed by cascading a =ig"3pass and Lo%3pass sections
,o obtain a Y+BdBJdec band3pass5 first order "ig"3pass and first order lo%3pass sections
are cascaded /or a Y;BdBJdec band pass filter5 second order =1/ and second order L1/
are connected ion series and so on In general5 t"e order of a band3pass filter depends on
t"e order of t"e "ig" pass and lo% pass circuits ,"e figure in t"e circuit diagram s"o%s a
first order Y+BdBJdecade %ide band3pass filter %"ic" is composed of first3order "ig"3
pass and first order lo%3pass filters ,"e figure belo% s"o%s t"e freHuency response of
t"e %ide band3pass filter
,o realiKe a band3pass response5 "o%ever5 f= must be larger t"an fL ,"e voltage gain
magnitude of t"e band3pass filter is eHual to t"e product of t"e voltage gain magnitude of
t"e "ig"3pass filter and lo%3pass sections
,"e cascade structure of filters cannot be used in t"e narro% band because of t"e
component value variations 8sensitivity< If fL and f= are nearly eHual5 a small c"ange in
eit"er or bot" causes significant error in pass3band ,"erefore narro% band3pass filter is
made using multiple feedback tec"niHue In suc" filter t"ere are t%o feedback pat"s
8"ence t"e name multiple feedback filter< and t"e Op3amp is used in inverting mode
PROCEDURE:
2 Connect capacitors and resistors %"ic" are provided eDternally on t"e trainer to #5
C5 #C5 CC terminals
+ !%itc" on t"e kit
7 !et t"e input voltage 4in to >m4 using function generator
; Connect c"annel 2 of C#O to 4in terminals and c"annel + to output terminals
> By varying t"e input freHuency in regular intervals5 note do%n t"e corresponding
output voltage
? 1lot t"e grap" bet%een gain and freHuency
: 4erify t"e practical and t"eoretical cut3off freHuency
O(SER.ATIO1S CO4UM1:
S.o. Frequency
(Hz)
V
o

(volts)
Gain = V
o
/
V
in
Gain (dB) = 20 log (Vo /
Vin)
+@
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+A
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7B
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;. MO1OSTA(4E A1D ASTA(4E MU4TI.I(RATOR A1D SCHMITT
TRI33ER CIRCUITS USI13 OP)AMP
Aim:
,o design and verify t"e basic )stable5 Monostable Multivibrators and !c"mitt trigger
circuits using an IC op amp
E7$i&m"n% R"7$ir"/ :
IC 9):;2C5 Dual #egulated po%er supply 82>3B2><5 !ignal generator5 C#O5 Decade
capacitance boDes 8t%o<5 #esistors5 !ilicon diodes 8t%o<5 -eneral purpose IC ,rainer
kit
T9"or8:
Multivibrators are a group of circuits t"at are eDtensively used in pulse generation
systems ,"ese circuits may be designed %it" ease5 using IC op amps Multivibrators
are of t"ree types' astable5 monostable5 and bistable
In t"e )stable circuit5 t"e op amp output runs from one Huasi3stable state to anot"er
on its o%n ,"e output is a sHuare %ave5 %"ose freHuency is determined from t"e C#
combination ,"e Monostable circuit "as only one stable state ,"e circuit can be
triggered to t"e ot"er 8Huasi3stable< state by an eDternal agency ,"e circuit returns to
t"e stable state after time period , determined by t"e time constant ,"is circuit is
used as a pulse generator ,"e circuit %it" t%o stable states called bi3stable
multivibrator ,"e circuit can be triggered from one stable state to anot"er by an
eDternal agency
,"e circuit diagram and %aveforms of )stable Multivibrator is s"o%n in t"e fig as
follo%s
72
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,"e feedback resistor #/ and t"e capacitor C provide t"e integrator action and t"e op
amp serves as a regenerative comparator ,"e output of t"e comparator is limited by
t"e saturation levels of t"e op amp 8vo
G
sat and vo
3
sat< ) fraction TI#2J8#2G#+<Z of t"e
out put voltage is fed back to t"e comparator and serves as t"e reference voltage ,"e
comparator compares t"e voltage across t"e capacitor %it" t"is voltage and s%itc"es
to negative saturation limit t"e movement vc becomes grater t"an vo ,"en t"e
capacitor begins to disc"arge t"roug" #/ until vc is eHual to vo t"e output is s%itc"ed
on to t"e positive saturation t"e moment vc becomes less t"an vo t"e output is a
sHuare %ave of time period
,I2JfI+#f C ln82G+#2J#+<
If IB;?+5,I+#/C and fI8+#/C<
32
,"e circuit diagram of a monostable multivibrator is s"o%n in fig In t"e stable state5
t"e amplifier is at positive saturation ) fraction of t"e input voltage 8vo
G
sat< is fed
back to t"e non3inverting input ,"e diode D2 clamps t"e inverting input at t"e O&
voltage of t"e diode If %e apply a sufficiently large negative pulse to t"e non3
inverting input5 it brings do%n t"e potential at B to t"e eart" potential and s%itc"es
t"e op amp on to t"e negative saturation limit ,"is is a Huasi3stable state as t"e
capacitor C disc"arges t"roug" #/ to%ards vo
3
sat 6"en t"e voltage across t"e capacitor
eDceeds vo
3
sat5 t"e amplifier output s%ings back to vo
G
sat
,"e freHuency of t"e output %ave is same as t"at of t"e triggering signal =o%ever
t"e gate %idt" ,- I,25 is determined by t"e time constants #/C t"e gate %idt" ,- is
given by
,- I #f C ln82G#2J#+<
Comparator is also called as !c"mitt rigger ,"e comparator is an amplifier specially
designed for null comparison measurements It is a "ig" gain amplifier
7+
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%it" %ell balanced difference inputs and controlled output limits ,"e circuit
arrangement and t"e transfer function of a simple voltage comparator are s"o%n
in figure ,"e signal voltage is directly applied to t"e inverting input and
reference voltage to t"e Gve input of t"e op amp in t"e open loop Configuration
)s long as t"e signal voltage is less t"an t"e reference voltage 8vi X vr < ,"e out
put %ill be maintained at t"e positive saturation level 8vB
G
sat < )s t"e signal passes
t"roug" a value eHual to vr5 t"e op amp is s%itc"ed on to t"e negative saturation
level as s"o%n in fig Because of t"e "ig" gain of t"e op amp5 a fe% millivolts
differential input is enoug" to s%itc" op amp bet%een t"e saturation limits In
practice comparators5 t"e transfer function "as a finite slope in t"e region vi [vB I
B t"is is due to t"e finite gain of t"e op amp ,"e slope approac"es t"e ideal
8vertical< as t"e comparator gain increases
) comparator circuit %it" positive feedback 8via #+< is s"o%n in fig
6"en t"e input voltage approac"es v2 8t"e voltage at non3inverting input<
feedback s%itc"es t"e op amp output regeneratively bet%een t"e t%o saturation
limits as s"o%n in fig Let us no% evaluate t"e condition under %"ic" t"e
transition takes place %"en vi X v25 t"e output is at vB
G
sat under t"ese conditions
v2 I 8 #+vr J #2G#+<G8 #2 vB
G
sat J #2G#+<I4i
If vi is no% increased t"e out put remains constant at vB
G
sat until vi I v2 at t"is
voltage 5 called t"res"old or triggering voltage t"e output s%itc"es to vB
3
sat and
remains in t"is state as long as vi W v2 ,"e voltage at t"e non3inverting terminal
%"en vi W v2 is given by
v2 I 8 #+vr J #2G#+<G8 #2 vB
3
sat J #2G#+<I4+
Considering an eDample %"ere #+I2BBko"m5 #2I2ko"m5vrI2B45 vB
G
satI2B4 and
vB
3
sat I 32B45%e "ave 42I2B@ and 4+IBAB ,"is indicates t"at t"e transition takes
place for different values of vi depending on %"et"er t"e voltage is increasing or
decreasing to%ards t"e reference voltage ,"us t"e circuit eD"ibits "ysteresis ,"e
amount of "ysteresis 84=I42F4+< is directly proportional to t"e positive feedback
fraction #2 J #2G#+
77
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,"e regenerative comparator is also referred as a !c"mitt trigger It may be used
as a sHuaring circuit
E<&"rim"n%a- &ro+"/$r":
a! A#%a'-" m$-%i,i'ra%or:
6ire t"e circuit as s"o%n in fig .se a decade capacitance boD for C5 if
available Observe t"e output %ave form using a C#O
C"oose #/I#+I2BBko"m
If is c"osen to be B;?+5 #2I@Ako"m ,"en fI2J+#/C
4ary C from BB2 to BBB2/ and measure t"e freHuency at eac" step
Compare t"e observed freHuency %it" t"e calculated one ,abulate t"e results
as s"o%n in table
Decrease t"e value of t"e capacitance furt"er and find out t"e value of C and
t"e corresponding freHuency at %"ic" t"e circuit stops oscillating
/or eac" combination of #/ and C5 measure t"e peak values of t"e output
voltage 8vosat<
and t"e voltage across C8vc< 4erify t"e relation IvoJvc
'!Mono#%a'-" m$-%i,i'ra%or:
6ire t"e circuit of fig .se t"e decade capacitance boD in place of C
C"oose #/I#+I2BBko"m ,"e value of #2is dependent on t"e value of
!ince t"e amplitude of t"e triggering pulse "as to be greater t"an t"e feedback
voltage5 c"oose a small value for 5 say B2 t"en #2 I 2Bko"m
C"oose Cp and #p suc" t"at Cp#p is very muc" less t"an t"e time period of t"e
"ig"est triggering freHuency to be used ,ypically
Cp#p I 2Bs
,"e gate %idt" is given by ,- I#fCln82G#2J#+<
4ary t"e freHuency of t"e sHuare %ave trigger input and measure t"e gate
%idt" at eac" freHuency
Keep t"e trigger freHuency at a particular value and vary #/C by varying C
measure t"e gate %idt" and t"e freHuency of t"e output at eac" step Enter
your results in table Is t"ere an upper limit to t"e gate %idt"N
Keep #/C at a particular value 8say 7Bsec< and vary t"e triggering freHuency
/ind out t"e "ig"est freHuency beyond %"ic" triggering does not take place
C! S+9mi%% Trigg"r Com&ara%or!:)
7;
K!rid"ar #a$u %%engglabsblogspotcom
6ire t"e circuit as s"o%n in fig .se a 2>4 battery for vr t"e inverting input is
fed by a dc supply consisting of a 7B4 dc source and ten turn 2Bko"m
potentiometer ,"is arrangement gives a resolution of 2Bm4
6it" s2 closed and s+ open5 t"e circuit configuration is t"at of a simple voltage
comparator 4ary t"e input to t"e inverting terminal from 2; to 2?4 in steps
of 2 or + m4 and measure t"e output voltage %it" t"e multi meter Dra% t"e
transfer c"aracteristic 6"at is t"e precision %it" %"ic" you can estimate t"e
reference voltageN =o% does t"e transfer function look like %"en vi and vr are
interc"angedN
%it" s+ closed and s2 open5 t"e circuit gets converted into a regenerative
comparator or sc"mitt trigger C"oose #2 and #+ suc" t"at 42 I+B4 and
4+IB:4 84=I274< 4ary t"e input voltage from B> to ++4 in steps of
m4 and record t"e out put voltage ,ake readings %it" t"e input voltage
increasing and also %"en it is decreasing #epresent vB as a function of vi
Compare v= value obtained from t"e grap" %it" t"e calculated one
remove 7B4 battery from t"e circuit /eed t"e !c"mitt trigger %it" t"e sine
%ave and observe output %aveform on t"e C#O Increase t"e amplitude of t"e
input voltage until you observe a sHuare %ave Can you identify t"e upper and
lo%er triggering pointsN
Q$"#%ion#:
2 6"at is a multivibratorN 6"y is it called a binaryN
+ Distinguis" bet%een astable5 bistable and monostable Multivibrators
7 EDplain "o% an op amp may be used as 8i< astable 8ii< bistable and
8iii< monostable multivibrator
; 6"at is t"e effect of sle% rate on t"e %orking of an op amp multivibratorN
> 6"at is a voltage comparatorN EDplain5 %it" t"e necessary circuit diagram5 "o% a
differential amplifier may be used as a comparator
? Dra% t"e transfer c"aracteristics of 8a< an ideal comparator and 8b< a practical
comparator Comment on t"e differences
: 6"at are t"e c"aracteristics of an op amp t"at make it suitable for use as a
comparatorN
@ EDplain %"y t"e upper and lo%er triggering points of a !c"mitt trigger are separatedN
EDplain t"e significance of "ysteresis
A Describe a met"od of clamping t"e output levels of a comparator
2B 6"at is Kero crossing detectorN
7>
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7?
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7. MO1OSTA(4E MU4TI.I(RATOR USI13 ::: TIMER
Aim:
,o measure t"e pulse %idt" of a monostable multivibrator using IC >>> ,imer
A&&ara%$#:
S.1o. EQUIPME1T QUA1TITY
2 Dual ,race Oscilloscope B2
+ C#O 1robes B+
7 77K resistor B2
; B2/ capacitor B+
> 1ulse -enerator B2
? Bread Board B2
: Connecting %ires
CIRCUIT DIA3RAM:
7:
K!rid"ar #a$u %%engglabsblogspotcom
THEORY:
) monostable multivibrator5 often called a one3s"ot multivibrator is a pulse operating
circuit in %"ic" t"e duration of t"e pulse is determined by t"e #C net%ork connected
eDternally to >>> IC ,imer In a stable or !tand3by !tate t"e output of t"e circuit is
approDimately Kero or logic lo% level 6"en an eDternal pulse is applied5 t"e output is
forced to go "ig"84cc< ,"e duration for %"ic" t"e output remains "ig" is determined by
t"e eDternal #C net%ork connected to t"e ,imer IC )t t"e end of timing interval5 t"e
output automatically reverts back to its logic lo% stable state ,"e output remains lo%
until t"e trigger pulse is applied again ,"en t"e cycle repeats ,"e monostable
multivibrator "as only one stable state 8=ere output is lo%< =ence t"e name monostable
&ormally t"e output of t"e monostable multi is lo%
O&"ra%ion:
)ccording to t"e %aveforms initially t"e output lo% ie5 circuit in stable state ,ransistor
Q2 is on and capacitor C is s"orted to ground =o%ever5 upon t"e application of a
negative trigger pulse to pin+ transistor Q2 is turned off %"ic" releases s"ot circuit across
t"e eDternal capacitor C and drives t"e output to "ig" ,"e capacitor C no% starts
c"arging to%ards 4cc t"roug" t"e resistor # =o%ever %"en t"e voltage across t"e
capacitor eHuals to +J7 of 4cc5 output goes lo% and t"e capacitor disc"arges t"roug" t"e
transistor Q2It remains lo% until a trigger pulse is applied across pin+ )s s"o%n in t"e
%aveforms5 t"e pulse %idt" of t"e trigger must be smaller t"an t"e eDpected pulse %idt"
of t"e %aveform )lso t"e trigger pulse amplitude must be a negative going input signal
%it" amplitude larger t"an 2J7 4cc ,"e pulse %idt" of t"e output %aveform is given by
t"e eHuation , I 22 #C
7@
K!rid"ar #a$u %%engglabsblogspotcom
D"#ign an/ Pro+"/$r":
2 Connect t"e circuit a s"o%n in t"e figure %it" # taken as obtained from t"e follo%ing
calculations
1ulse %idt" , I 22#C
-iven ,I B; ms
!ay C I BB2 C
# I ;BB D 2B
3?
J 22 D BB2 D 2B
3?
I 7?7 K
+ )pply a trigger pulse at pin+ %"ere amplitude varies bet%een 2J7 4cc to less t"an +J7
4cc
7 Measure t"e pulse %idt" and record t"e output %aveforms across pin7 and also observe
capacitor voltage at pin? %it" respect to trigger input
5A.E FORMS:
CO1C4USIO1:
Output %aveforms and drop across capacitor are observed and verified %it" t"eoretical
values
7A
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.i,a =.o+" Q$"#%ion#'
2 -ive some applications of
Monostable multivibrator and eDplain t"em
+ -ive t"e design procedure for
monostable multivibrator
7 6"y monostable multi is also called
as one s"ot multivibratorN
; Derive t"e pulse %idt" of a
monostable multivibrator using IC >>> ,imer
;B
K!rid"ar #a$u %%engglabsblogspotcom
>. ASTA(4E MU4TI.I(RATOR USI13 ::: TIMER
AIM: ,o construct and observe t"e %aveforms of a 2 K=K sHuare %ave form generator
using >>> timer for duty cycle 8a< DIB+> 8b< DIB>
APPARATUS:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 Dual ,race Oscilloscope B2
+ C#O probes B+
7 #esistors B+
; Capacitors B+
> Breadboard B2
? Connecting %ires
THEORY:
)n )stable multivibrator often called as free running multivibrator is a rectangular %ave
generating circuit .nlike t"e monostable multivibrator t"e circuit does not reHuire an
eDternal trigger to c"ange t"e state of t"e output =ence t"e name free running5 "o%ever5
t"e time during %"ic" t"e output is eit"er "ig" or lo% is determined by t"e t%o resistors
and a capacitor %"ic" are connected eDternally
OPERATIO1:
,"e figure s"o%s t"e >>> ,imer connected as an )stable Multivibrator Initially5 %"en t"e
output is "ig" capacitor \CC starts c"arging to%ards 4cc t"roug" #) and #B =o%ever as
soon as t"e voltage across t"e resistor eHuals to +J7 4cc5 t"e comparator triggers t"e flip3
flop and t"e output s%itc"es to lo% &o% t"e capacitor \CC starts disc"arging t"roug" #B
and disc"arge terminal 8pin &o: %"ic" is internally connected to t"e collector terminal
of t"e transistor Q2< and %"en t"e voltage across \CC reac"es2J7 4cc 5 t"e second
comparatorCs output triggers t"e flip3flop and t"e output goes "ig" ,"en t"e cycle
repeats ,"e output voltage and t"e capacitor voltage %aveforms are s"o%n in t"e figure
)s s"o%n in t"e figure5 t"e capacitor is periodically c"arges and
disc"arges in bet%een 4cc and 2J7 4cc respectively ,"e time during %"ic" capacitor
c"arges from 2J7 4cc to +J7 4cc5 t"e output goes "ig" and is given by
,c I B?A 8#) G #B<C
;2
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6"ere #) and #B are in o"ms and C is in farads !imilarly5 t"e time during %"ic" t"e
capacitor disc"arges from +J7 4cc to 2J7 4cc5 t"e output is lo% and is given by
,d I B?A #BC
6"ere #B is in o"ms and C in farads
,"us t"e total period t"e output %aveforms is
, I ,C G ,d I B?A 8#) G #B<C
,"is inturns gives t"e freHuency of oscillation as
/o I 2J, I 2;>J8#) G+ #B< C
,"e freHuency is independent of t"e supply voltage 4cc
Often t"e term duty cycle is used in con$unction %it" t"e )stable multivibrator ,"e duty
cycle is t"e ratio of t"e time ,c during %"ic" t"e output is "ig" to t"e total time period ,
it is generally eDpresses as a percentage
] Duty Cycle I ,c J , D 2BB]
I 8#) G #B< J 8 #) G +#B< D 2BB ]
CIRCUIT DIA3RAM:
DESI31 ASPECTS:
;+
K!rid"ar #a$u %%engglabsblogspotcom
8a< )symmetrical !Huare %ave generator'
f I 2K=K and DIB+>
fI2;>J8#) G+#B<C
DI 8#) G #B< J 8 #) G +#B<
)nd select CI B2 9/
!olving for #) and #B5 %e get
#) I 7? KE and #B I >> KE
8b< !ymmetrical !Huare %ave -enerator'
f I 2 K=K and D I B>
f I 2;>J8 #) G +#B<C
DI 8#) G #B< J 8 #) G +#B<
)nd select CI B2 9/
!olving for #) and #B5 %e get
#) I #B I :+> KE
.se a Diode O):A across #B
PROCEDURE:
2 Connect t"e circuit as s"o%n in t"e figure using component values as obtained
in t"e design part 8a<
+ Observe and sketc" t"e capacitor voltage %aveform 81in ?<and t"e output
%aveform at pin 7 Measure t"e freHuency and t"e duty cycle of t"e output
%aveform
7 &eDt5 make t"e circuit from t"e figure using component values as obtained
from design part 8b<
; #epeat step +
CO1C4USIO1:
=ence5 t"e symmetrical and asymmetrical sHuare %ave forms are generated using
>>> IC timer
.I.A .OCE QUESTIO1S:
2 List fe% applications of >>> ,imer
+ Dra% t"e pin diagram of a >>> ,imer
7 6"at is t"e use of #eset ,erminal in t"e ICN
; =o% t"e disc"arge and t"res"old terminals are used 8pins ? & :<N
> 6"at is t"e use of control voltage terminal 8pin ><N
? Derive an eDpression for ,O&5 ,O// and duty cycle of t"e )stable Multivibrator
;7
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: Define Duty Cycle
@ Design an )stable Multivibrator %it" a >>> ,imer %it" a given duty cycle
8ranging from ;B3:B]< and given time period
A Design an )stable Multivibrator using a >>> ,imer by assuming t"e values of t%o
resistors 8#) and #B< and C I BB2 9/
;;
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?. IC RE3U4ATOR
RE3U4ATIO1 USI13 6)TERMI1A4 FI@ED RE3U4ATOR I.C
Aim' ,o find t"e line and load regulation of a 73terminal fiDed regulator IC
A&&ara%$#:
S.1o APPARATUS QUA1TITY
2 4ariable #egulator 1o%er !upply 8B37B4< B2
+ 1ositive /iDed 73terminal #egulator
8IC :@B>5:@2+5:@2><
B2
7 Multimeter B+
T9"or8:
T9r"" %"rmina- fi<"/ &o#i%i," ,o-%ag" r"g$-a%or#:
,"e :@DD series ICs are designed as fiDed positive voltage regulators and %it" adeHuate
"eat sinking can deliver output currents in eDcess of 2) ICs also "ave internal t"ermal
overload protection and internal s"ort circuit limiting /or proper operation of t"ese ICs
reHuire a common ground bet%een input and output In addition t"e difference bet%een
input and output voltage84in34out<5 called drop3out voltage must be typically +4
Capacitor at output is used to improve t"e transient response of t"e regulator
,"e ma$or performance parameters for voltage regulators are line regulation5 load
regulation Line regulation is defined as t"e c"ange in t"e output voltage in t"e c"ange in
t"e input voltage and usually eDpressed in m4 or a percentage of output voltage 4o Load
regulation is t"e c"ange in t"e output voltage for c"ange in load current and also
eDpressed in m4 or percentage of output voltage 4o
,"e :@DD series regulators available in seven voltage options ie5
>48:@B><5?48:@B?<5@48:@B@<52+48:@2+<52>48:@2><52@48:@2@< and +;48:@+;< ,"is
series is available in different packages ,O37 metal can 8for "ig" currents< and ,O3++B
plastic package 8for lo% output currents<
T9r"" %"rmina- fi<"/ n"ga%i," ,o-%ag" r"g$-a%or#:
,"e :ADD series of fiDed negative voltage regulators are complement to t"e :@DD series
devices ,"ese negative regulators are also available in : voltage options as t"e positive
voltage regulators available In addition t%o eDtra voltage options are available in :ADD
series
;>
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CIRCUIT DIA3RAM:
Pro+"/$r":
4oa/ R"g$-a%ion'
2Make t"e connections as per circuit diagram
+)d$ust t"e input voltage source and maintain t"e voltage constant 8above t"e
defined regulated value of #egulator IC<
74ary t"e load ie #Land re%ind t"e values of IL and 4L maintaining 42 constant
;,abulate t"e readings and t"is tabular column indicates t"e load regulation
c"aracteristics
>#epeat t"e above procedure for different values of 42
4in" R"g$-a%ion'
2Maintain t"e same circuit diagram connections of line regulation c"arecteristics
+Maintain t"e Load current IL constant5 no% vary t"e input voltage 4I and note do%n
t"e output voltage 4o values
7#epeat t"e above procedure for different values of load current IL
;?
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4oa/ R"g$-a%ion'
4I I +B4 4II+>4
S.1o .O I4 .O I4
4in" R"g$-a%ion:
IL I B>m) IL I 2m)
S.1o. .I .O .I .O
R"#$-%:
;:
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1A. ARITHMETIC CIRCUITS
AIM:
8a< ,o design & verify t"e =alf3adder and /ull3adder circuits
8i< .sing )&D5 O#5 &O, and ED3O# -ates
;@
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8ii< Only &)&D -ates and verify t"eir operations
8b< ,o design & verify t"e =alf3subtractor and /ull3subtractor circuits using gates
APPARATUS:
DESI31:
=alf )dder'
) =alf )dder
is a
combinational logic circuit t"at adds t%o binary bits It produces t"ereby sum and
carry bits
!"#$S %#$"#$S
& ' ()**' S#+
0 0 0 0
0 , 0 ,
, 0 0 ,
, , , 0
/rom t"e trut" table it is clear t"at logic function reHuired to realiKe t"e sum and carry
bits is as follo%s
!.M I ) 0O# B
C)##* I )B
CIRCUIT DIA3RAM:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 -eneral 1urpose IC ,rainer B2
+ IC :;BB5 IC :;B@5 IC :;7+5
IC :;@?
B2
7 1atc" Cords B2
;A
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FU44 ADDER:
/ull adder is a combinational circuit t"at adds 7 bits %"ic" include t%o present bits and
previous carry "ence generating sum and carry
!"#$S %#$"#$S
& ' - ()**' S#+
0 0 0 0 0
0 0 , 0 ,
0 , 0 0 ,
0 , , , 0
, 0 0 0 ,
, 0 , , 0
, , 0 , 0
, , , , ,
,"e sum and t"e carry output eDpressions can be obtained from 73variable karnaug" map
%"ic" is s"o%n as follo%s'
!.M I 0 80O#< * 80O#< R
C)##* I 0*G*RGR0
>B
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FU44 ADDER USI13 T5O HA4F)ADDERS:
/ull )dder can be implemented by using t%o =alf3)dders and one O# gate %"ic" is
s"o%n in t"e follo%ing figure %"ic" s"o%s t"at it can be implemented using only &)&D
gates
CIRCUIT DIA3RAM:
HA4F
SU(TRACTOR:
) =alf3subtractor is a combinational digital circuit t"at subtracts t%o numbers and
produces a difference and a borro%
!"#$S %#$"#$S
& ' B .
0 0 0 0
0 , , ,
, 0 0 ,
, , 0 0
/rom t"e trut" table it is clear t"at difference function is realiKed by
D I 0 0O# *
>2
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B I 0C*
FU44 SU(TRACTOR:
/ull subtractor is a combinational logic circuit t"at performs subtraction bet%een t%o
input bits taking into account a one bit t"at may "ave been borro%ed by a lo%er
significant bit It consists of t"ree inputs and t%o outputs ,"e trut" table is s"o%n belo%'
!"#$S %#$"#$S
& ' - B .
0 0 0 0 0
0 0 , , ,
0 , 0 , ,
0 , , , 0
, 0 0 0 ,
, 0 , 0 0
, , 0 0 0
, , , , ,
CIRCUIT DIA3RAM:
CO1C4USIO1:
,"e trut" tables for =alf )dder5 /ull )dder5 =alf !ubtractor and /ull !ubtractor are
verified
.I.A .OCE QUESTIO1S:
2 Define =alf3)dder
+ Design a =alf )dder using different types of gates 8&)&D5 0O#5 &O#5
)OI<
7 Define /ull )dder
; Design a /ull )dder using different types of gates
>+
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> Define =alf !ubtractor and /ull !ubtractor
? =o% can /ull )dder and /ull !ubtractor be used as =alf )dder and =alf
!ubtractor respectivelyN
: Dra% t"e block diagram of an n3bit binary adder using /ull )dders
@ 6"at is a ComparatorN
A Mention t"e applications of a Comparator
2B 6"at do you mean by pulse3time modulationN
22 Design 23bit and ;3bit Comparator circuits
>7
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11. DESI31 OF CODE CO1.ERTER
AIM: Design a 73bit Binary to -ray and -ray to Binary code converter
APPARATUS:
S.o. /0#!"+/$ *)G/ 0#)$!$'
,. General 1ur1ose !( $rainer 0230 V 0,
2. 4567 (&%* gate)8 4506 (2
in1ut ). gate)
02
3. "atc9 (ords 0,
THEORY B DESI31:
,"e code converter is a combinational circuit %"ic" converts one form of code to anot"er
form =ere %e are designing a code converter circuit %"ic" converts 73bit binary code to
73bit gray code or 73bit gray code to 73bit binary code =ence to distinguis" one of t"e
>;
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t%o conversions %e "ave one select input to t"e circuit ,"e block diagram and t"e trut"
table of t"e circuit reHuired are as s"o%n belo%'
(4OCC DIA3RAM:

TRUTH TA(4E:
!"#$S %#$"#$S
: & ' - " 0 *
0 0 0 0 0 0 0
0 0 0 , 0 0 ,
0 0 , 0 0 , ,
0 0 , , 0 , 0
0 , 0 0 , , 0
0 , 0 , , , ,
0 , , 0 , 0 ,
0 , , , , 0 0
, 0 0 0 0 0 0
, 0 0 , 0 0 ,
, 0 , 0 0 , 0
, 0 , , 0 , ,
, , 0 0 , 0 0
, , 0 , , 0 ,
, , , 0 , , 0
, , , , , , ,
4O3IC CIRCUIT DIA3RAM:
>>
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PROCEDURE:
2 .sing t"e ,,L ICs connect t"e circuit according to t"e logic diagram
+ -ive t"e reHuired po%er supply
7 4erify t"e outputs %it" t"e trut" table by c"anging t"e input
combinations
/rom t"e trut" table %"en 6IB5 t"e circuit converts binary code to gray code and %"en
6I2 circuit converts gray to binary code
DESI31:
.sing t"e k3maps t"e trut" table can be entered and can be simplified as follo%s'
>?
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CO1C4USIO1:
,"e 73bit binary to gray and gray to binary trut" tables are verified
.I.A QUESTIO1S:
2 6"at are t"e gray code propertiesN
+ Design ;3bit binary to BCD code converter
7 6"at are t"e applications of t"e gray codeN
; Design BCD to seven segment coBde converter using suitable gates
> Design BCD to eDcess37 code converter using suitable gates
? 6"at are t"e advantages of =eDadecimal codeN
: 6"ere is an octal code usedN
>:
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12. DECODER A1D ITS APP4ICATIO1S
AIM:
>@
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8a< ,o verify Decoder operation
8b< ,o implement a /ull3adder circuit using Decoder and &)&D gates
APPARATUS:
S.o. /0#!"+/$ *)G
/
0#)$!$'
,. 45,36
.ecoder
3 ; 6 0,
2. 4500 (t<o
in1ut ).
gate)
0uad 0,
3. General
"ur1ose !(
$rainer
0,
5. "atc9 (ords 0,
THEORY:
8a< Decoder' ) binary code of n bits is capable of representing up to +
n
distinct
elements of coded information ) decoder is a combinational digital circuit t"at
converts binary information from n input lines to a maDimum of +
n
uniHue output
lines If t"e n3bit decoder information "as unused state or donCt care conditions5
t"e decoder %ill "ave less t"an +
n
inputs
)s an eDample5 consider t"at t"e +3to3; line decoder circuit s"o%n in t"e figure ,"e
t%o inputs are decoded into four outputs Eac" output representing one of t"e
minterms of +3input variables ,"e t%o inverters provide t"e compliment of t"e inputs
and eac" of t"e ; )&D gates generate one of t"e minterms ,"e operation of t"e
decoder can be clarified from its input3output relations"ip listed in t"e table
TRUTH TA(4E:
!"#$S %#$"#$S
& ' .
0
.
,
.
2
.
3
0 0 , 0 0 0
0 , 0 , 0 0
, 0 0 0 , 0
, , 0 0 0 ,
>A
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(4OCC DIA3RAM:
1o%":
,"e circuit s"o%n in t"e above figure is t"at of a )ctive "ig" output Decoder )n )ctive
lo% output type Decoder can be constructed %it" &)&D gates instead of )&D gates
Observe t"at t"e output variables are mutually eDclusive because only one output can be
eHual to one at one time ,"e output line %"ose value eHuals to one represents t"e
minterm eHuivalent to t"e binar;y number presently available in t"e input lines
8b< Implementation of /ull adder circuit %it" Decoder and &)&D gates'
TRUTH TA(4E OF FU44 ADDER:
I&1.,! O.,1.,!
0 * R C)##* !.M
B B B B B
B B 2 B 2
B 2 B B 2
B 2 2 2 B
2 B B B 2
2 B 2 2 B
2 2 B 2 B
2 2 2 2 2
/rom t"e trut" table of full adder5 t"e sum function and carry function can be %ritten as
follo%s'
!.M8D5 y5 K< I ^ m 825 +5 ;5 :<
C)##*8D5 y5 K< I ^ m 875 >5 ?5 :<
!ince t"ere are t"ree inputs and a total of eig"t minterms %e need a 73to3@ line decoder
,"e implementation "as been s"o%n in t"e figure ,"e decoder generates t"e eig"t
minterms for D5 y5 K ,"e &)&D gate for output _sum` forms t"e sum of minterms 25 +5 ;
and : ,"e &)&D gate for output _carry` forms t"e sum of minterms 75 >5 ? and :
?B
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CIRCUIT DIA3RAM:
-ive t"e connections as s"o%n in figure and verify t"e trut" table of full adder
APP4ICATIO1S OF DECODER:
2 ) Decoder %it" enable input acts as DemultipleDer
+ It can be used to implement combinational digital circuits
7 It is used for memory address decoding in digital computers
.I.A .OCE QUESTIO1S:
2 Implement any given logic gate using Decoder
+ Implement t"e given Boolean function
7 Implement different combinational digital circuits using decoder
?2
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16. MU4TIP4E@ER A1D ITS APP4ICATIO1S
AIM:
?+
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8a< ,o verify t"e multipleDer operation of ICs :;L!2>2 or :;2>7
8b< Implementation of a Boolean function f8%5 D5 y5 K<Ia m8B525>5:5@52B52><
using multipleDer
APPARATUS:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 -eneral purpose IC ,rainer B37B 4 B2
+ :;2>2 8@ D 2 M.0< or :;2>7 8dual ;
D 2 M.0<
B2
7 1atc" Cords B2
THEORY:
MultipleDer is a combinational digital circuit %"ose function is to select 2 out of +
&
input
data sources and to transmit selected data to a single information c"annel One out of t"e
+
&
input data sources can be selected %it" t"e "elp of & select lines MultipleDer is also
called data selector MultipleDer %it" different data siKes like + to 2 line8+ D 2<5 ; to 2
line8; D 2<5 @ to 2 line 8@ D 2<5 2? to 2 line 82? D 2<etc are available in t"e form of
integrated circuits /ig 2 8a< s"o%s t"e block diagram of ; to 2 line multipleDer and its
trut" table ,"e detailed circuit diagram is s"o%n in figure 2
TRUTH TA(4E:
I&1.,! O.,1.,
E !2 !+ /
B B B IB
B B 2 I2
B 2 B I+
B 2 2 I7
2 0 0 B
?7
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a! OPERATIO1 OF THE CIRCUIT:
)s s"o%n in t"e circuit diagram t"e enable signal E 8%"ic" is active lo%< is used to
activate t"e multipleDer circuit as %ell as eDpansion purpose
6"en EI25 %"atever may be t"e selection inputs 8donCt cares< t"e output of t"e
circuit is al%ays Kero ie5 t"e circuit %ill not function as a multipleDer
If EIB t"e circuit is in enable position and based on t"e selection line5 one of t"e four
inputs is selected and appears as t"e output
APP4ICATIO1S OF MU4TIP4E@ERS:
+ It can be used for t"e implementation of combinational digital circuits
7 /or parallel3to3serial data conversion
; !eHuential data !election
> MultipleDers are used in common bus systems to connect t"e number of registers
to a common bus
'! Im&-"m"n%a%ion of 4),aria'-" (oo-"an F$n+%ion f0D <D 8D E! F G
mAD1D:D7D>D1AD1:! $#ing > < 1 MU@:
DESI31 PROCEDURE:
,"e given function is a four variable function ,o implement four variables function @
D 2 multipleDer is reHuired Connect D5 y5 K variables to t"e selection lines !+5 !25 !B of
t"e @ D 2 multipleDer Consider no% t"e single variable % !ince t"is variable is t"e
"ig"est order position in t"e seHuence of variables5 it %ill be complemented in
minterms B to 8+
;
J+ 32< %"ic" comprise t"e first "alf in t"e list of minterms ,"e
second "alf of t"e minterms %ill "ave t"eir % variable complemented /or a four
variable function %5 D5 y5 K %e "ave siDteen minterms 4ariable % is complemented in
minterms B to : and uncomplemented in minterms @ to 2>
List t"e inputs of t"e multipleDer and under t"em list all t"e minterms in t%o ro%s
,"e first ro% lists all t"ose minterms 6"en % is complemented and t"e second ro%
all t"e minterms %it" % uncomplemented as s"o%n in t"e figure Circle all t"e
minterms of t"e function and inspect eac" column separately
If t"e t%o minterms in a column are not circled apply \BC to t"e corresponding
multipleDer input If t"e t%o minterms in a column are circled apply \2C to t"e
corresponding multipleDer input If t"e top minterm is circled and t"e bottom is not
circled5 apply \%C to t"e input If t"e bottom minterm is circled and top is not circled5
apply \%CC to t"e input
By circling t"e minterms of t"e function and applying t"e rules for finding t"e values
of multipleDer inputs %e obtain t"e implementation as s"o%n in t"e figure
?;
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TRUTH TA(4E FOR THE 3I.E1 (OO4EA1 FU1CTIO1:
% D y K f
B B B B 2
B B B 2 2
B B 2 B B
B B 2 2 B
B 2 B B B
B 2 B 2 2
B 2 2 B B
B 2 2 2 2
2 B B B 2
2 B B 2 B
2 B 2 B 2
2 B 2 2 B
2 2 B B B
2 2 B 2 B
2 2 2 B B
2 2 2 2 2
CIRCUIT DIA3RAM:
?>
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&o% connect t"e circuit as s"o%n in t"e figure and verify t"e trut" table of t"e given
Boolean function
.I.A .OCE QUESTIO1S:
2 6"at is a function of a multipleDerN
+ 6"at are its applicationsN
7 Implement a given Boolean function %it" t"e "elp of a M.0
; Design a /ull subtractor using a ; D 2 M.0
> Design a full adder using ; D 2 M.0
? Design 2? D 2 M.0 using @ D 2 M.0
: 6"at is t"e difference bet%een a M.0 and a DecoderN
@ Define DemultipleDer
A Design BCD to Decimal Decoder
2B #ealiKe a given Boolean function using a Decoder Circuit
22 6"at are t"e applications of a decoderN
2+ 6"y is M.0 called as Data !electorN
27 -ive t"e pin diagrams of ; D 2 and @ D 2 M.0
??
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14. F4IP)F4OP A1D ITS CO1.ERSIO1
AIM:
8a< !tudy of bK /lip3/lop
8b< #ealiKation of Delay /lip3/lop using bK /lip3/lop
APPARATUS REQUIRED:
Digital IC Logic ,rainer Kit5
1atc" cords5
bK flip3flop IC 8 :;L!:?<
&O, gate IC 8:;B;<
a! S%$/8 of F-i&F-o& o&"ra%ion:
THEORY:
,"e logic symbol of an bK /lip3flop is as s"o%n in t"e figure It "as t%o sync"ronous
inputs 8b & K<5 a clock input 8CLK<5 t%o async"ronous inputs 8preset & clear< and t%o
outputs 8Q & QC<
)ccording to t"e inputs ! & #5 t"e output c"anges %"en t"e preset and clear are at logic
lo% and irrespective of t"e inputs ! & #5 preset is used to set t"e output and clear is used
to reset t"e output
Inputs Output
Q
Operation
CLK 1r Cr
2 2 2 QnG2 &ormal /lip3/lop operation
B 2 B B Clear 8or #eset<
B B 2 2 1reset 8or !et<
'! Con,"r#ion of F-i& F-o&'
(4OCC DIA3RAM:
?:
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THEORY:
Operation of D /lip3/lop' ,"e D /lip3/lop "as only one input called Delay input and
t%o outputs Q and QC It can be constructed from !# /lip3/lop by placing an inverter
bet%een ! and # and assigning t"e symbol D to t"e ! input ,"e structure of D /lip3
/lop is s"o%n in t"e figure
,"e present state5 &eDt state ,able for D /lip3/lop can be dra%n as s"o%n in t"e
follo%ing table
Qn 81resent !tate< D81resent Input< QnG2 8&eDt !tate<
B B B
B 2 2
2 B B
2 2 2
.sing t"e EDcitation ,able for !# /lip3/lop given in table +5 t"e neDt sates ie5 ! & #
values can be augmented in t"e above 1! to &! table as s"o%n in t"e table 7
CIRCUIT DIA3RAM:
TRUTH TA(4E OF D F4IP)F4OP:
Operation of D /lip3/lop is as
follo%s'
2 6"en t"e CLK input is lo%5 t"e
input D "as no effect since t"e set and reset inputs of &)&D flip3flop are kept
"ig"
+ 6"en t"e CLK goes "ig"5 t"e Q output %ill take on t"e value of t"e D input
Qn D QnG2 EDcitation Inputs
! #
B B B B 0
B 2 2 2 B
2 B B B 2
2 2 2 D B
CLK I&1., D O.,1., QnG2
2 B B
2 2 2
B D &o C"ange
?@
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DESI31:
One can design t"e neDt state decoder ie5 t"e simplified eDpressions for ! and # from
t"e k3maps as s"o%n in t"e follo%ing tables
/rom t"e above5 !ID and #IDC &o% t"e circuit for delay flip3flop using !# flip3flop
can be dra%n as s"o%n in t"e figure %it" single &O, gate ,"e logic symbol for D /lip3
/lop and t"e trut" table are s"o%n
PROCEDURE:
2 Connect t"e logic circuit as per t"e above diagram
+ 4erify t"e trut" table of D /lip3/lop
RESU4T:
D /lip3/lop trut" table is verified
.I.A .OCE QUESTIO1S:
2 Convert D /lip3/lop to bK /lip3/lop
+ 6"at is race around condition in bK /lip3/lopN =o% to avoid t"isN
7 Convert bK to !# /lip3/lop
; Define Latc"
> Dra% t"e circuit of !# Latc" using &)&D gates and &O# -ates
? Dra% t"e circuit of Bounce3free s%itc" and eDplain its operation
: Distinguis" bet%een sync"ronous and )sync"ronous /lip3/lop
@ Dra% t"e circuit of clocked !# // using IC &)&D gates -ive its trut" table and
eDplain its operation
A In "o% many %ays clocking can be doneN 6"at are t"eyN
?A
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2B Dra% bK flip3flop using clocked !# flip3flop )nd also using IC &)&D gates
eDplain its operation
22 6"at is t"e role of present and clear in bK flip3flop
2+ EDplain t"e operation of Master3!lave bK flip3flop
27 6"at are t"e applications of flip3flopsN
2; #ealiKe D3// and ,3// using bK3// and clocked !#3//
2> #ealiKe ,3// using !#3// %it" , data input and D3// %it" , data input
:B
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1:. SY1CHRO1OUS COU1TER
AIM: ,o design of Mod3> Counter using bK Master3!lave /lip3flops
APPARATUS:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 Digital IC ,rainer Kit B37B4 B2
+ bK Master3!lave // :;:? B+
7 Connecting %ires
THEORY:
)sync"ronous or ripple counter is t"e simplest type of binary counter as it reHuires less
"ard%are but its speed of operation is lo% because t"e propagation delay time of all flip3
flops is cumulative and t"e total settling time is t"e product of t"e total number of flip3
flops and propagation delay of a single flip3flop )not"er problem encountered %it"
ripple counter is t"e glitc"es at t"e decoding gate output ,"e problem can be eliminated
by applying clock pulses to t"e flip3flops simultaneously %"ic" is done in a sync"ronous
counter ,"e speed of operation in a sync"ronous counter is limited by t"e propagation
delay of control gate and a flip3flop
DESI31:
2 /ind t"e number of flip3flops reHuired using t"e follo%ing eHuation
m X +
&
%"ere & I number of flip3flopsc m I Module m counter
> X +
7
c t"ree flip3flops are reHuired to design Mod3> counter
+ 6rite t"e count seHuence in t"e tabular form as s"o%n'

&o% %e prepare t"e K3maps %it" Q+Q2QB as input variables and flip3flop inputs as output
variables
CLK Q+ Q2 QB
B B B B
2 B B 2
+ B 2 B
7 B 2 2
; 2 B B
> B B B
:2
K!rid"ar #a$u %%engglabsblogspotcom
6e t"en minimiKe t"e K3maps and t"e resulting minimiKed eDpressions are
bB I Q+C 5 KB I 2
b2 I Qo 5 K2 I Qo
b+ I Q2QBC 5 K+ I 2
7 Determine t"e flip3flop inputs %"ic" must be present for t"e desired neDt state from t"e
present state in t"e EDcitation ,able
HC E<+i%a%ion Ta'-":
Qn QnG2 b K
B B B 0
B 2 2 0
2 B D 2
2 2 D B
1#E!E&, !,),E &E0, !,),E /LI13/LO1 I&1.,!
Q+ Q2 QB Q+ Q2 QB b+ K+ b2 K2 bB KB
B B B B B 2 B 0 B 0 2 0
B B B B 2 B B 0 2 0 0 2
B 2 B B 2 2 B 0 0 B 2 0
B 2 2 2 B B 2 0 0 2 0 2
2 B B B B B 0 2 B 0 B 0
:+
K!rid"ar #a$u %%engglabsblogspotcom
E<+i%a%ion Ma&#:
,"e count seHuence and t"e reHuired inputs to t"e flip3flops are given in t"e above table
,"e inputs to t"e flip3flops are determined in t"e follo%ing manner >5 ?5 : are unused
states
.sing t"e above eDcitation eHuations5 t"e circuit diagram for t"e Mod3> counter can be
dra%n as s"o%n belo%'
TIMI13 DIA3RAM:
PROCEDURE:
2 Connect t"e circuit as per t"e logic diagram
+ 4erify t"e count of Mod3> counter
RESU4T: Mod3> counter is designed using bK /lip3/lops and t"e Mod3> counter
operation is verified
:7
K!rid"ar #a$u %%engglabsblogspotcom
.I.A .OCE QUESTIO1S:
2 Design Mod3? counter using , /lip3/lops Dra% ,iming diagram for a continuous
clock
+ Design Mod32+ counter using D /lip3/lops Dra% timing diagram for a
continuous clock
7 Contrast and Compare combinational and seHuential digital circuits
; 6"at are t"e differences bet%een )sync"ronous and !ync"ronous CounterN
> If t"e freHuency of counter is 2B M=K5 %"at is t"e output freHuency of Mod32B
counterN
:;
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1;. ASY1CHRO1OUS COU1TER
AIM: to Design a Mod3? async"ronous counter using master3slave bK /lip3/lops
APPARATUS REQUIRED:
!&o EQ.I1ME&, #)&-E Q.)&,I,*
2 Digital IC ,rainer Kit B37B4 B2
+ bK Master3!lave // :;:? B+
7 &)&D gates B2
7 Connecting %ires
THEORY:
,"e async"ronous counter is t"e simplest in terms of logical operations and t"erefore is
t"e simplest to design In t"is counter5 all t"e flip3flops are not under t"e control of a
single clock ,"e clock pulse applied to t"e first flip3flop and t"e successive flip3flops are
triggered by t"e output of t"e previous flip3flops )nd t"us t"e counter "as cumulative
settling time =ence its speed is limited
DESI31:
&umber of flip3flops reHuired is decide by t"e follo%ing eHuation
+
n
d &
6"ere n I &umber of flip3flops reHuired
& I MaDimum number of possible states
+
7
d ? c 7 /lip3flops are reHuired
4O3IC DIA3RAM:
:>
K!rid"ar #a$u %%engglabsblogspotcom
TRUTH TA(4E:

OPERATIO1:
) Mod3? ripple counter s"o%n in t"e figure %it"out &)&D gate functions as a Mod3@
Binary counter5 %"ic" counts from BBB to 222 =o%ever5 t"e presence of t"e &)&D gate
alters t"e seHuence as follo%s'
2 ,"e &)&D gate output is connected to t"e clear inputs of eac" flip3flop )s long as t"e
&)&D gate output is "ig"5 it %ill "ave no effect on t"e counter 6"en t"e &)&D gate
output goes lo%5 it %ill clear all t"e flip3flops and t"e counter immediately goes to t"e
BBB state
+ ,"e outputs of t"e counter Q2 and Q+ are given as inputs to t"e &)&D gate %"ose
output goes lo% %"enever Q2 I QB I2 ,"is condition %ill occur %"en t"e counter goes
from t"e 2B2 state to t"e 22B state ,"e lo% at t"e &)&D gate output %ill clear t"e
counter to t"e BBBstate Once t"e flip3flop "as been cleared5 t"e &)&D gate output goes
back to "ig" since Q2 IQ+ I 2 condition no longer eDists
7 ,"erefore t"e counting seHuence is BBB e BB2 e B2B e B22e 2BBe 2B2e BBBe
ff)lt"oug" t"e counter does go to t"e 22B state5 it remains t"ere only for a fe% nano
seconds before it recycles to BBB 6e can say t"at t"is counter counts from BBB to 2B2
and t"en recycles to BBB It essentially skips 22B and 222 states going t"roug" siD
different states ,"us it is a Mod3? counter
CLOCK 1.L!E Q+ Q2 QB
B B B B
2 B B 2
+ B 2 B
7 B 2 2
; 2 B B
> 2 B 2
? 2 2 B
:?
K!rid"ar #a$u %%engglabsblogspotcom
&ote t"at t"e %aveform at t"e Q2 output contains a spike or glitc" caused by a momentary
occurrence of 22B sate before clearing ,"is glitc" is very narro% and so %ould not
produce any visible indication It s"ould be noted t"at t"e Q+ output "as a freHuency
eHual to 2J? t"e input freHuency
,o construct any Mod3& counter5 t"e follo%ing met"od can be used'
2 /ind t"e number of flip3flops reHuired for t"e desired Mod3& counter using +
n32
d
& d +
n

+ Connect all t"e flip3flops as a ripple counter

7 /ind t"e binary eHuivalent for &
; Connect all t"e flip3flopsC outputs for %"ic" Q I2 %"en t"e count is &5 as inputs
to &)&D gate
> Connect t"e &)&D gate output to t"e clear input of eac" flip3flop
? 6"en t"e counter reac"es &t" state t"e output of t"e &)&D gate goes lo%
resetting all t"e flip3flops to B and so t"e counter counts B t"roug" &32 "aving &
states
PROCEDURE:
2 Connect t"e circuit as per t"e circuit diagram
+ 4erify t"e count seHuence
CO1C4USIO1:
Mod3? counter count seHuence BBB e 2B2 is verified
.I.A .OICE QUESTIO1S:
2 6"at are t"e advantages and disadvantages of async"ronous countersN
+ =o% can t"e errors due to uneHual delays in async"ronous counters be avoidedN
7 EDplain sync"ronous counters
; Design Mod3@ and Mod3> up3do%n async"ronous counter
> Design a t%isted3ring counter using bK and D //s
? Design a ring counter using bK and , //s
: Define Carry propagation delay
@ Dra% t"e circuit of a >3bit sync"ronous counter %it" series carry
::
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A 6"at do you mean by look3a"ead carryN
:@
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17. SHIFT RE3ISTER
AIM: ,o design a ;3bit s"ift #egister using bK /lip3/lops
APPARATUS:
Digital IC Logic ,rainer5 bK /lip3/lopsC IC8:;:?<5 Connecting %ires
THEORY:
) s"ift #egister is a cascade connection of number of single bit storage elements
contained in a single package ,"e storage elements are flip3flops and are arranged so t"at
output of t"e eac" flip3flop is connected to t"e input of t"e neDt flip3flop in cascade
) simple four stage register is s"o%n in t"e above figure Information is moved into t"is
register one bit at a time sync"ronously %it" t"e clock /or t"e first clock pulse5 one bit is
moved into t"e flip3flop //7 /or t"e neDt clock pulse t"e bit stored in t"e flip3flop //7
is stored in //+ and so on do%n t"e cascade5 %"ile t"e bit stored originally lost
:A
K!rid"ar #a$u %%engglabsblogspotcom
) s"ift register can be operated in any of t"e follo%ing modes'
2 !erial3in !erial3out 8!I!O<' In t"is configuration5 data can be moved in and out of t"e
register one bit at a time
+ !erial3in 1arallel3out 8!I1O<' ,"e register is loaded serially one bit at a time and %"en
output is reHuired t"e data stored in all flip3flops can be read simultaneously
7 1arallel3in !erial3out 81I!O<' )ll t"e flip3flops in t"e register are loaded
simultaneously and %"en t"e output is reHuired data is taken from t"e register one bit at a
time under clock control
; 1arallel3in 1arallel3out 81I1O<' )ll t"e flip3flops in t"e register are loaded
simultaneously and %"en an output is reHuired all t"e flip3flops are read simultaneously
APP4ICATIO1S:
2 ,emporary data storage
+ !erial to 1arallel Conversion and vice3versa
7 Counters
; )JD Converters
> !eHuence -enerator
>3bit IC s"ift register'
,"e circuit of >3bit IC !"ift #egister 8:;A?< is s"o%n in t"e figure It consists of > bK
master3slave flip3flops connected to perform parallel to serial or serial to parallel
conversion of binary data 1arallel3in 1arallel3out or serial3in !erial3out operations are
also possible
@B
K!rid"ar #a$u %%engglabsblogspotcom
OPERATIO1:
8a<
2 Clear all t"e flip3flops by programming CL# I B5 CLK I B and preset enable
eHual to B
+ Enable all t"e flip3flops by programming CL# I 2 and preset enable to B
7 )pply t"e least significant bit of data 8)ssume Data I 2B2B2<
; 6"en t"e first clock pulse is applied and data input is 25 //; "as control input b I
25 K I B %"ic" makes Q; I 2
)t t"e same time //7 goes to a state determined by t"e state of
//; prior to t"e application of t"e pulse !imilarly Q+5 Q25 QB are determined by Q75
Q+5 Q2 respectively ,"erefore Q75 Q+5 Q25 QB remain in \BC state ,"e contents of t"e
register at t"e arrival of eac" clock pulse are given in t"e table
6it" t"e second clock pulse %"en t"e data input is \BC Q; becomes \BC and Q7 goes to \2C
state and t"e state of t"e register is B2BBB 6it" t"e arrival of t"e t"ird clock pulse
contents of t"e register become 2B2BB )fter t"e fourt" clock pulse5 B2B2B are t"e
contents of t"e register ,"e contents of t"e register become 2B2B2 after t"e application of
fift" clock pulse and data \2C at t"e serial input ,"is completes t"e operation of entering
t"e data into t"e register %it" t"e first serial bit in QB and t"e fift" bit in Q; ,"e clock
pulses must stop after entering fift" bit 1arallel data is available at t"e output of t"e flip3
flops and can be read simultaneously
!ince t"e data %as applies serially t"is type of register operation is kno%n as !I1O
8b< 1I!O'
2 Clear all t"e flip3flops by setting CL# I B and preset enable to \BC
CLOCK
1.L!E
D),)
I&1.,
CO&,E&,! O/ ,=E #E-I!,E#
Q; Q7 Q+ Q2 QB
B B B B B B B
2 2 2 B B B B
+ B B 2 B B B
7 2 2 B 2 B B
; B B 2 B 2 B
> 2 2 B 2 B 2
@2
K!rid"ar #a$u %%engglabsblogspotcom
+ )fter clearing all t"e flip3flops5 if t"e data lines are connected to parallel inputs 81r;5
1r75 1r+5 1r2 and 1rB< and a \2C is applied at t"e present input ,"e data is %ritten into t"e
register ,"e stored %ord can t"en be read serially at QB by applying five clock pulses
8c<
!I!O' Data as entered into register as in 8a< and read as in 8b<
8d<
1I1O' Data as entered into t"e register as in 8b< and read as in 8a<
RI13 COU1TER:
If QB is connected to D5 a circulating memory is formed If all t"e
flip3flops are cleared and t"en a \2C is entered into one of t"e flip3flops t"roug" preset
enable I 2 %ill make QB I 2 Clock pulses %ill transfer t"e state \2C around t"e ring ,"is
configuration is kno%n as ring counter and t"ere is one output pulse for eac" & clock
pulses %"ere & is t"e number of flip3flops ,"e ring counter %orks as a divide by &
counter
TRUTH TA(4E:
CLOCK 1.L!E Q; Q7 Q+ Q2 QB
B B B B B B
2 2 B B B B
+ B 2 B B B
7 B B 2 B B
; B B B 2 B
> B B B B 2
APP4ICATIO1S:
2 !tepper Motor %"ic" rotates in steps
+ !uccessive )pproDimation ) to D converter
7 Control !tate counters
T0i#%"/ Ring Co$n%"r or Ho9n#on Co$n%"r or Mo"'i$# Co$n%"r:
In t"e t%isted ring counter t"e complemented QB of t"e
least significant flip3flop is fed back to D input of t"e most significant flip3flop ,"e
counter resource is as s"o%n in t"e trut" table In counting seHuence one flip3flop
gives "ig" output5 and t"en t%o flip3flops give "ig" outputs5 t"en t"ree and so on )t
one stage all flip3flops give "ig" outputs )fter t"is one flip3flop gives \BC output and
t"en t%o flip3flops give \BC output t"en t"ree and so on /inally all flip3flops give \BC
output
/ive flip3flops are needed to realiKe Mod32B counter "ence it is also called as divide
by +& 8& I &umber of flip3flops< counter /or & flip3flops t"ere s"ould be +
&
possible states But in bo"nson Counter only +& states are valid and ot"ers are invalid
states
TRUTH TA(4E:
CLOCK Q; Q7 Q+ Q2 QB
@+
K!rid"ar #a$u %%engglabsblogspotcom
1.L!E
B B B B B B
2 2 B B B B
+ 2 2 B B B
7 2 2 2 B B
; 2 2 2 2 B
> 2 2 2 2 2
? B 2 2 2 2
: B B 2 2 2
@ B B B 2 2
A B B B B 2
2B B B B B B
PROCEDURE:
2 Connect t"e circuit as per t"e circuit diagram
+ 4erify t"e operations of s"ift #egister
7 4erify t"e trut" tables of ring counter and t%isted ring counter
CO1C4USIO1:
,"e various modes of operation of a s"ift register are verified
.I.A .OCE QUESTIO1S:
2 Define a s"ift register
+ =o% is it usefulN
7 6"at is a ring counterN
; 6"at is t"e t%isted ring counterN
> Dra% t"e circuit diagram of a serial3input rig"t s"ift register
? Dra% t"e circuit diagram of a parallel3input rig"t s"ift register
: EDplain briefly about serial3in left s"ift operation
@ 6"at do you mean by Modulus of t"e counterN
A =o% %ill you cascade t"e IC :;A> to obtain an @3bit s"ift registerN
2B =o% %ill you see a s"ift register to multiply or divide a binary number by +N
@7
K!rid"ar #a$u %%engglabsblogspotcom
22 !"o% t"at t"e t%isted ring counter is a modulo3+& counter %"ere & is t"e number
of flip3flops
@;
K!rid"ar #a$u %%engglabsblogspotcom
1>. P44 CHARACTERISTICS A1D APP4ICATIO1S
AIM: ,o !tudy t"e 1"ase Lock Loop circuits using IC >?> and to determine
t"e 1LL c"aracteristics

APPARATUS REQUIRED'
S.1O. 1am" of %9" D",i+" Rang"I 1o. QTY
@>
K!rid"ar #a$u %%engglabsblogspotcom
2
+
7
;
>
IC >?>
#esistors
Capacitors
1otentiometers
DC 1o%er !upply

@+B g5
2>K g 5
;: K g5
2B K g5
;: K g
2BBp/5
B2 U /
B 2 U /
;: K g
G J 3 2+ 4
2
2
2
7
7
+
2
;
2
2
2

THEORY:
1"ase Locked Loop 81LL< devices and tec"niHues are %idely used in applications
suc" as automatic freHuency tracking5 freHuency multiplication and freHuency synt"esis
etc ,"ree best kno%n 1LL Ics are t"e ;B;?B CMO! c"ip and &E >?> and &E >?:
devices
1LL is a feedback system and comprises of t"e follo%ing four basic elements
2 1"ase Comparator
+ Lo% 1ass /ilter
7 Error correction )mplifier
; 4oltage Controlled Oscillator
,"e 4CO is a free running multivibrator %"ose centre freHuency is determined by an
eDternal timing capacitor and an eDternal resistor Its centre freHuency can also be s"ifted
to eit"er side by application of a DC control voltage to appropriate terminal of t"e IC
,"e freHuency deviation is directly proportional to t"e DC control voltage and "ence it is
called a h4oltage Controlled Oscillatorh or in s"ort a 4CO ,"e 4CO output is presented
to a 1"ase sensitive detector5 %"ere its 1"ase is compared %it" t"at of t"e incoming
signal ,"e detector produces DC output %"ose magnitude is directly proportional to t"e
p"ase difference ,"is is called _Error !ignal i and is first passed t"roug" a lo% pass filter
to remove components of t"e 4CO and input signal freHuency5 and t"en amplified by a
DC amplifier called iError )mplifieri ,"e DC output of t"e amplifier is fed back to t"e
4CO to complete t"e loop5 and to s"ift t"e 4CO freHuency in a direction t"at approac"es
more closely to t"e freHuency of t"e incoming signal and t"e error signal becomes less
and less Once t"is action starts5 %e say t"at t"e signal is in t"e iCapture #angei ,"e
4CO continuous to c"ange freHuency till its output is eDactly t"e same as t"e input signal
@?
K!rid"ar #a$u %%engglabsblogspotcom
freHuency ,"e circuit is t"en locked )fter locking5 if t"e input signal freHuency c"anges5
t"e 4CO freHuency follo%s it eDactly ,"us t"e loop "as t"ree states' a< free running b<
capture and c<Locked or ,racking /ig 2 s"o%s t"e %aveform of t"e voltage at t"e
output of t"e error correction amplifier )s capture starts5 a small sine %ave appears ,"is
is t"e hbeath freHuency bet%een t"e 4CO and t"e input signal &ote t"at t"e negative "alf
of t"e %aveform is slig"tly longer t"an t"e positive "alf ,"is is t"e dc component of t"e
beat %"ic" drives t"e 4CO to%ards t"e lock
Eac" successive cycle causes t"e 4CO moves closer to t"e input signal ,"e 4CO
finally locks and t"e beat freHuency becomes Kero ,"e lo% pass filter is an important
factor in controlling t"e capture range If t"e 4CO is too far a%ay5 t"e beat freHuency %ill
be too "ig" to pass t"roug" t"e filter and t"e 1LL %ill not respond ,"e signal is t"en said
to be out of t"e capture band
Once t"e lock "as been ac"ieved5 t"e filter no longer restricts t"e 1LL ,"e 4CO
can track t"e signal %ell past t"e capture band limited by t"e gain of t"e amplifier and t"e
output range of t"e 4CO and t"e p"ase comparator ,"us t"e tracking range is muc"
%ider t"an t"e capture range ,"e filter5 "o%ever5 does limit t"e speed at %"ic" t"e 1LL
can track If t"e freHuency c"anges too rapidly5 t"e 1LL can become unlocked ,"e signal
freHuency s"ould again come %it"in t"e capture band for capturing again ,"e rate of
c"ange of p"ase is often eDpressed in hradians per secondh
,"e lo% pass filter5 t"us5 restricts t"e capture band and reduces t"e tracking speed
But it serves one very useful purpose ,"e c"arge on t"e filter capacitor provides t"e 1LL
a s"ort term hmemoryh Even if t"e signal drops into noise for several cycles5 t"e dc
voltage on t"e filter capacitor %ill continue to s"ift t"e 4CO at t"e same rate until it picks
up t"e signal again ,"is produces a "ig" noise immunity and locking stability ,"e
output of 4CO is an eDact replica of incoming signal freHuency minus t"e noise
:;: ) PHASE 4OCCED 4OOP:
,"e >?> 1LL is a self contained adaptable filter and demodulator for t"e
freHuency range from BBB2 =K to >BB K=K ,"e centre freHuency o f t"e 1LL is
@:
K!rid"ar #a$u %%engglabsblogspotcom
determined by t"e free running freHuency of t"e 4CO5 %"ic" can be ad$usted eDternally
%it" a resistor or a capacitor
,"e lo% pass filter 5 %"ic" determines t"e capture c"aracteristics of t"e loop is
formed by an internal resistor and an eDternal capacitor ,"e pin configurations for >?>
are s"o%n in fig belo%
,"e eDternal resistance # s"ould be limited in t"e range +Ko"ms to +B Ko"ms
6it" an optimum value in t"e order of ; K ,"e free running freHuency fo can also be
controlled by applying an eDternal voltage to pin : ,"e effect of DC voltage bet%een
pins 2B and : on t"e freHuency fo and t"e output signal %aveforms of t"e 4CO are s"o%n
in figure hbh ,"e output impedance of sHuare %ave output at pin no ; is lo% and a load
of 2K or "ig"er can be driven directly Only "ig" impedance loads s"ould be connected
to pin A for getting triangle %ave output
) s"ort circuit bet%een pins ; and >
/ig + 1=)!E LOCK LOO1 >?> 1in Configuration
connects t"e 4CO output to t"e 1"ase Detector ,"e input signal can be coupled directly
if t"e dc resistance as seen from t"e connections at pin + and 7 are eHual and t"ere is no
difference bet%een t"e dc voltages at t"ese pins )t pin no ? a dc reference voltage is
obtained %"ic" is close to t"e dc voltage of t"e demodulated output measured at pin no
:
4OCC RA13E:
,"e range of freHuencies in t"e vicinity of fo over %"ic" t"e 4CO once
locked %it" t"e input signa5 %ill remain locked is called t"e hlock rangeh and is given by
fL II @fo J 4co
If a resistance is connected bet%een pin ? and pin : t"e gain of t"e amplifier stage can be
reduced %it" little c"ange in t"e dc voltage level at t"e output ,"is allo%s t"e lock range
to t"e reduced %it" little c"ange in t"e free running freHuency fo In t"is %ay t"e lock
range can be decreased from GJ3 ?B ] to GJ3 +B] of fo at G?4 supply voltage ,"e
@@
K!rid"ar #a$u %%engglabsblogspotcom
dependence of lock range on t"is gain setting resistor is s"o%n in figure >) belo% ,"e
lock range also depends on t"e input signal strengt" and on t"e supply voltage ,"ese
relations"ips are s"o%n in figure >B
CAPTURE RA13E:
,"e range of freHuencies about f o over %"ic" t"e loop %ill acHuire lock
%it" an input signal5 initially starting out of lock is called t"e hCapture rangeh and is given
by t"e follo%ing eDpression
/L I 82 J +V < D Tj 8 + V fL J 7? D 2BBB D C+ < Z
Due to t"e "ig"ly linear 4CO5 t"e >?> 1LL can lock and track an input signal over a very
%ide range by typically GJ3 ?B] %it" "ig" linearity
/ig 7 Block diagram of >?> 1LL
@A
K!rid"ar #a$u %%engglabsblogspotcom
/ig ; Effect of Control of fo and output %aveforms of 4CO in >?> 1LL
/ig >a effect of gain setting fig >b On Lock #ange
#esistance and of input signal
!trengt"
CIRCUIT DIA3RAM:
1LL .!I&- >?>
PROCEDURE:
1. !%itc" on t"e po%er supply to t"e circuit
2. C"eck t"e 4CO output at pin ; of IC >?>
6. ,"e output is a sHuare %aveform ,"e freHuency of t"e %ave form depends on C,
8BB2 U /< and #! 8variable 2B K g potentiometer<
4. !"ort circuit t"e pins ; and pin > and apply any signal of variable freHuency to
observe t"e 4CO output
:. C"ange t"e input freHuency and observe t"e 4CO output on t"e C#O
;. )t some freHuencies5 t"e 4CO output is locked to t"e input signal freHuency ,"is can
be observed by increasing or decreasing t"e freHuency of t"e 4CO output by
c"anging input freHuency
7. ,"e freHuency belo% or above t"e value5 t"e 4CO output is not locked
>. By c"anging t"e potentiometer provided on t"e board5 locking freHuency range can be
c"anged
AB
K!rid"ar #a$u %%engglabsblogspotcom
READI13S:
4CO Output freHuency fB I
Locking range I fL+ F fL2 I
Capture range I fC+ F fC2 I
RESU4T:
.I.A = .OCE Q$"#%ion#:
2 6"at is meant by 4CON
+ List some of t"e applications of 1LL
7 List some IC s %"ic" are used as 1LLs
; 6"at is meant by Capture rangeN
> List t"e basic building blocks of 1LL
? Define capture range5 lock range and pull3in3timle
: 6"ic" is greater h Capture rangeh or hLock rangehN
@ 6"at is t"e ma$or difference bet%een digital and analog 1LLsN
A EDplain "o% 1LL can be used for )M and /M detection
A2
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1?. DI3ITA4 TO A1A4O3 DIA! CO1.ERTER
AIM: ,o Design and verify t"e ;3bit Digital to )nalog Conversion by using
8a< Binary %eig"ted #esistors 8#5 +#5 ;#5 @#< type D)C
8b< #3+# Ladder type D)C
APPARATUS REQUIRED :

!&o EQ.I1ME&, J
COM1O&E&,
#)&-E J
4)L.E
Q.)&,I,*
2 1o%er !upply B37B 4 B7 &os
+ O13)M1 :;2 B2 &o
7 #esistors B+ &os
; Bread Board B2 &o
> Digital 4oltmeter B37B4 B2 &o
CIRCUIT DIA3RAM:
A+
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PROCEDURE:
Connect t"e circuit as s"o%n above Connect po%er supplies and c"oose 4# I >4
.sing t"e voltmeter measure t"e output voltage 4o and obtain t"e tabular column as
s"o%n belo%'
D C B ) Ouput 4oltage 4o
in 4olts
B B B B
B B B 2
B B 2 B
B B 2 2
B 2 B B
B 2 B 2
B 2 2 B
B 2 2 2
2 B B B
2 B B 2
2 B 2 B
2 B 2 2
2 2 B B
2 2 B 2
2 2 2 B
2 2 2 2
4erify t"e above results t"eoretically by t"e eDpression
4o I K 4/! 8D2 +
32
G D+ +
3+
G f G D&+
3&
<
R)2R 4ADDER TYPE:
One %ay to get around t"e problem of a binary %eig"ted resistors5 D)C is to use a ladder
circuit as s"o%n in t"e figure Only t%o resistance values are needed in #3+# Ladder
D)C ,"is eliminates t"e range problem /urt"ermore5 since t"e resistors can be
manufactured on t"e same c"ip t"ey "ave almost identical c"aracteristics
4ADDER PROPERTIES:
)n #3+# ladder does somet"ing interesting to t"e impedance at different points in t"e
circuit ,o begin %it"5 t"e t%o resistors at node D in t"e figure ) are in parallel and may
be reduced to an eHuivalent resistor as s"o%n in /igB &o% to t"e rig"t of &ode C as +#
is in parallel %it" +# t"e circuit reduces to /igC Looking to t"e left of node B in /igC
%e see +# parallel %it" +# ,"erefore t"e figure reduces to /igD )gain +# is in parallel
to +# and t"e circuit reduces to single # as s"o%n in figE /ig2 summariKes ladder
impedance Looking into t"e left side of a kno%n %e al%ays see a resistance #3+# t"is
impedance p"enomenon is t"e key for analyKing a modern DJ) converter because t"ey
use t"e ladder instead of %eig"ted resistors
A7
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PROCEDURE:
2. Connect t"e circuit as s"o%n
+ !%itc" on t"e trainer by connecting t"e po%er card to )C mains
7 Connect t"e output of t"e #3+# ladder net%ork to t"e input of t"e :;2 O1()M1
; Observe and note do%n t"e output voltage 4o of t"e circuit ie t"e output of 9):;2 IC
using a D4M
> Measure 4o for various combinations of inputs as per t"e tabular column as s"o%n
belo% and tabulate it


!&o Digital Input )nalog output
4o in volts
2 BBBB
+ BBB2
7 BB2B
; BB22
> B2BB
? B2B2
: B22B
@ B222
A 2BBB
2B 2BB2
22 2B2B
2+ 2B22
27 22BB
2; 22B2
2> 222B
2? 2222
.I.A .OCE QUESTIO1S:
A;
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2 Classify D)Cs on t"e basis of t"eir outputs
+ 6"at are t"e disadvantages in %eig"ted3#esistor type D)C over #3+# ladder type D)CN
7 6"ic" is t"e fastest )DC and %"yN
; EDplain t"e important specifications of )JD and DJ) convertersN
> -ive t"e sc"ematic representation of D)C
? Derive an eDpression for t"e output voltage for Binary3%eig"ted #esistors D)C and
ladder3type D)C
: 6"at is a multiplying D)CN
@ 6"at are t"e advantages and disadvantages of D)CN
A>