6.

2 Differential Amplifiers
6.2.1 What is a Differential Amplifier?
6.2.2 DC Analysis
6.2.3 AC Analysis
Differential-Mode Input Signals
Common-Mode Input Signals
Common-Mode Rejection Ratio
6.2.4 Half-Circuit Analysis
6.2.5 Biasing with Electronic Current Sources
6.2.6 Generalized Differential Amplifier
Literature:

Jaeger, Blalock, Chapter 15.1, page 968-991

Jaeger, Blalock, Chapter 10.5-10.7, page 544-550

Acknowledgement Oliver Brand for slides

6.2.1 What is a Differential Amplifier

One of the most important building

blocks in analog circuit design
Differential amplifier forms heart of
operational amplifier (see Chapter 7)
Single-stage amplifier consisting of 2
matched BJTs or MOSFETs
Circuit has two input terminals v1
and v2 and differential-mode output
voltage vOD = vC1 vC2 (defined by
voltage between two collectors/drains)
Ideal performance requires matched
transistors, i.e. parameter sets
(IS, 0, VA) or (Kn, VT, ), Q-points and
temperature of both transistors are
identical
DC coupled: No coupling capacitors!!

Bipolar Differential Amplifier

Jaeger, Blalock, Fig. 15.1a

Bipolar and MOS Differential Amplifier

Bipolar Differential Amplifier

MOS Differential Amplifier

Jaeger, Blalock, Fig. 15.1

6.2.2 DC Analysis
Bipolar Differential Amplifier
Find Q-point by setting both
input signal sources to zero,
i.e. both bases are
connected to GND, yielding

VBE1 = VBE2 VBE

If both transistors are
matched, then circuit
symmetry forces

VCE1 = VCE2 VCE

IC1 = IC2 IC
IE1 = IE2 IE
IB1 = IB2 IB

Jaeger, Blalock, Fig. 15.2

DC Analysis
Bipolar Differential Amplifier
KVL at emitter node yields emitter current:
VBE + 2 IE REE VEE = 0

IE =

VEE VBE
2 REE

Transport model equations yield base and collector currents

IC = F IE

and IB = IC / F

and the voltages

"$
# VCE1 = VCE2 = VC2 VE2 = VC1 + VEE 2 IEREE = VC1 + VBE
VE1 = VE2 = VEE + 2 IEREE $%
VEE VBE
(I
,V
)
=
(
,VCC ICRC + VBE )
Resulting Q-Point:
C
CE
F
2 REE
VC1 = VC2 = VCC ICRC

For the symmetrical amplifier, the output voltage becomes

VOD = VC1 VC2 = 0V

6.2.3 AC Analysis
Bipolar Differential Amplifier
AC analysis with input sources
v1 and v2
Input sources broken into
differential mode input vid and
common-mode input vic
v id = v1 v 2 "
$
v1 + v 2 #
v ic =
$
2 %

v id
2
v
v 2 = v ic id
2
v1 = v ic +

Differential-mode output signal vod

and common-mode output signal
voc are defined similarly
v od = v c1 v c 2

and

v oc =

v c1 + v c 2
2

Jaeger, Blalock,
Fig. 15.4

AC Analysis
Bipolar Differential Amplifier
Assuming a (general) linear system, the voltages voc
and vod will be a function of both vid and vic
! v $ 'A
## od && = ) dd
" v oc % )(A dc

A cd * ! v id $
, ## &&
A cc ,+ " v ic %

Add = differential-mode gain

Acd = common-mode conversion gain
Acc = common-mode gain
Adc = differential-mode conversion gain

For an ideal amplifier: Acd = Adc = 0

In case of transistor mismatch, Acd Adc 0

Differential-Mode Gain
Apply purely differential mode
input signal vid (i.e. vic = 0)
Replace BJT with small-signal
models (Hybrid-Pi model) and
neglect r0 for gain analysis
Goal: Find differential mode
gain Add = vod/vid
Note: input source for Q2
has wrong polarity
in Jaeger, Blalock!

Jaeger, Blalock, Fig. 15.5

Differential-Mode Gain
Small-Signal Equivalent Circuit

Summing currents at emitter node:

1
1
1
v 3 + gmv 3 + gmv 4 + v 4 =
ve
r
r
REE
Base-emitter voltages:
v
v3 =

id

ve

Jaeger, Blalock,
Fig. 15.6

and

v4 =

v id
ve
2

Differential-Mode Gain
Small-Signal Equivalent Circuit
Yielding.

"1
%
"1
%
1
+
g
v
+
v
=
2
+
g
v
=
ve
$
' 3
$
' e
m
4
m
REE
# r
&
# r
&

"2
1 %
$ + 2gm +
' ve = 0
REE &
# r

The last equation requires ve = 0, i.e. the emitter node in the

differential amplifier represents a virtual ground for
differential-mode signals
v
v
With ve = 0, we find v 3 = id and v 4 = id
2

and the output voltages

v c1 = gmv 3RC = gmRC

v id
2

and

v c 2 = gmRC

v id
2

Differential-Mode Gain
Small-Signal Equivalent Circuit
And what
about Adc?

yielding the differential-mode output signal

v od = v c1 v c 2 = gmRC v id
and the differential mode gain Add

A dd =

v od
v id

= gmRC
vic =0

If either vc1 or vc2 alone are used as output

(referred to as single-ended output), then
v c1
A dd1 =
v id v

ic =0

gmRC
=
2

and

A dd2

vc2
=
v id

vic =0

gmRC
=
2

The virtual ground at the emitter node causes amplifier to

behave as single-stage common-emitter amplifier with the
differential output providing the full gain of the C-E stage

Differential-Mode Input/Output Resistance

Small-Signal Equivalent Circuit
Differential-Mode Input Resistance Rid
Small signal resistance presented to full-differential mode
input voltage appearing between two bases
Keeping in mind that the emitter node is a virtual ground for
differential mode signals, we find
Rid =

v id
v id
=
= 2 r
ib1 "#(v id / 2) / r $%

Differential-Mode Output Resistance Rod

Set vid = 0 (i.e. gmv3 = gmv4 = 0, or open circuit), yielding
Rod = 2 (RC r0 ) 2 RC

Common-Mode Gain
Apply purely common mode
input signal vic (i.e. vid = 0)
As a result, both sides of
amplifier are completely
symmetrical
Goal: Find common mode
gain Acc = voc/vic
Replace BJT with small-signal
models (Hybrid-Pi model) and
neglect r0 for gain analysis

Jaeger, Blalock, Fig. 15.7

Common-Mode Gain
Small-Signal Equivalent Circuit

IE = (0 +1)IB

Using KVL, we find:

Jaeger, Blalock,
Fig. 15.8

v ic = ibr + v e = ib #$r + 2(0 +1)REE %&

Collector output voltage:

v c1 = v c 2 = 0ibRC =

0RC v ic
r + 2(0 +1)REE

Common-Mode Gain
Small-Signal Equivalent Circuit

Emitter voltage:

v e = 2ieREE = 2(0 +1)ibREE

2(0 +1)REEv ic
=
r + 2(0 +1)REE

2(0 +1)REE r

Resulting in the common-mode gain ACC

v ic
And what
about Acd?

0 1
0RC
R
v oc (v c1 + v c 2 ) / 2 v c1
A cc =
=
=
=
C
v ic
v ic
v ic
r + 2(0 +1)REE
2 REE

Multiplying and dividing ACC by IC yields

ICRC
VCC / 2
VCC / 2
VCC
A cc =

2 ICREE
2 IEREE
(VEE VBE )
2 VEE

Assuming a symmetric power supply VEE = VCC, we find Acc = 0.5

Common-Mode Input/Output Resistance

Small-Signal Equivalent Circuit

Common-Input Resistance Ric

Determined by total signal current 2 ib supplied from common-mode
source

Ric =

v ic r + 2(0 +1)REE r
=
= + (0 +1)REE
2ib
2
2

Characteristics of differential amplifier with common-mode input are

similar to those of common-emitter (common-source) amplifier with
large emitter (source) resistor

Common-Mode Rejection Ratio

Common Mode Rejection Ratio (CMRR) = ability of amplifier to
amplify desired differential-mode input signal and reject
undesired common-mode signal

A dm
CMRR =
A cm
with overall differential-mode gain Adm and overall common
mode gain Acm
For ideal differential amplifier with matched transistors and
a differential output vod, the common-mode gain is zero
(because Acd = 0), i.e. the CMRR is infinite

Common-Mode Rejection Ratio

In case of single-ended output, the CMRR is finite even for
matched transistors

v od
A
= A cc v ic + dd v id
! v $ 'A
2
2
od
&& = ) dd
with ##
v od
A dd
" v oc % )( 0
= v oc
= A cc v ic
v id
2
2

v c1 = v oc +
vc2

common
mode

A dm
CMRR =
A cm

differential
mode

gmRC
A dd 2
=
2 = gmREE
RC
A cc
2 REE

0 * ! v id $
, ## &&
A cc ,+ " v ic %

Common-Mode Rejection Ratio

For mismatched transistors with differential
output, the CMRR is approximated by
1

# g &
CMRR gmREE % (
$ g '

Note the
power to -1
in contrast to
Jaeger/Blalock

where g/g = 2(g1g2)/(g1+g2) is the fractional

mismatch between small-signal device parameters
of the two transistors (e.g. gm)
To improve CMRR: (i) maximize the gm REE product
and (ii) minimize the transistor mismatch

6.2.4 Half-Circuit Analysis

Half-Circuit Analysis: use
symmetry of differential
amplifier to simplify circuit by
splitting into differentialmode and common-mode
half circuits
Note: to achieve full
symmetry, (i) power supplies
have been split and (ii) the
emitter resistor REE has been
separated into two parallel
resistors with resistance
2 REE each

Jaeger, Blalock, Fig. 15.9

Half-Circuit Construction
Differential-Mode Signals
Rule for half-circuit construction for Differential-Mode Signals:
Points on the line of symmetry represent virtual grounds and are
connected to ground for ac analysis

Note: this way, the emitter/source node

automatically becomes a virtual ground!
For Diff-Mode
Analysis

Jaeger, Blalock, Fig. 15.10

Half-Circuit Construction
Common-Mode Signals
Rule for half-circuit construction for Common-Mode Signals:
Points on the line of symmetry are replaced by open circuits
For Q-Point Analysis

For Common-Mode
Analysis

Jaeger, Blalock, Fig. 15.11&12

Half-Circuit Analysis
For Differential-Mode
Analysis

For Q-Point
Analysis

For Common-Mode
Analysis

Analyze these simplified circuits and you should get the known
results of Chapter 6.2, page 4-16!
Lets try with differential mode analysis..

6.2.6 Generalized Differential Amplifier

Differential amplifiers
in general respond
to the difference of
two input signals
Basic differential
amplifier has two
inputs (connected to
sources v+ and v)
and a single output vo,
all referenced to GND;
the amplifier is driven by two DC
power supplies VCC and VEE
(typically VCC=VEE, e.g. 5V, 12V,
or 15V)
Note: A (generalized) differential
amplifier likely not only consists of
the single-stage differential
amplifier discussed so far, but has
multiple stages

Simplified
Symbol

Jaeger, Blalock, Fig. 10.5

Differential Amplifier Model

For signal analysis,
the differential amplifier
can be represented by
its input resistance Rid,
output resistance Ro
and a controlled voltage
source Avid (amplifying
the differential input
signal vid)
Two-port g-parameter
representation of
differential amplifier (with g12 = 0)

Jaeger, Blalock, Fig. 10.16

A = (open-circuit) voltage gain

vid = v+ v = differential input signal voltage
Rid = amplifier input resistance
Ro = amplifier output resistance

Differential Amplifier Model

The output signal is
in phase with the voltage
applied to the + terminal
(noninverting input v+)
and 180 out of phase
with the voltage applied
to the terminal
(inverting input v)
Jaeger, Blalock, Fig. 10.16

Applications:
Electronic feedback and control systems (error amplifiers)
Operational amplifiers (see Chapter 7)

Differential Amplifier Model

Jaeger, Blalock, Fig. 10.17

Assume: Amplifier driven by signal source having Thvenin

equivalent voltage vs and resistance RS and connected to load
resistance RL
What is the overall voltage gain Av = vo/vs?

Differential Amplifier Model

Output voltage:

RL
v o = A v id
Ro + RL

Differential input:

Rid
v id = v s
Rid + RS

Overall amplifier gain:

Av =

vo
Rid
RL
=A
vs
Rid + RS Ro + RL

Ideal differential amplifier: vo = A vid = A vs,

i.e. Av = A (maximum voltage gain available)
Requires Rid = and Ro = 0
or more general Rid Rs and Ro RL

From Differential Amplifiers to

Operational Amplifiers
Chapter 6.2 introduced single-stage, two-transistor differential
amplifiers
One important application of these differential amplifiers is at the
input stage of operational amplifiers to be discussed in
Chapter 7
Differential amplifiers provide desired differential input and
common-mode rejection capabilities, and a ground-referenced
output signal
However, an operational amplifier usually requires a higher gain
than is available from a single differential amplifier stage; thus
most operational amplifiers use two stages of gain and a
third, output stage, providing low output resistance and high
output current capability

Chapter 7 Operational Amplifiers

7.1
7.2
7.3
7.4
7.5

Ideal Operational Amplifier

Circuits Containing Ideal Operational Amplifiers
Design of Basic Operational Amplifiers
Non-Ideal Operational Amplifiers
Frequency Response and Bandwidth of OpAmps

Literature:

Jaeger, Blalock, Chapter 11, page 541-595

Jaeger, Blalock, Chapter 12, page 610-658
Jaeger, Blalock, Chapter 15.2, page 861-874

What is an Operational Amplifier?

The operational amplifier or op

amp is a fundamental building
block of analog circuit design
The op amp is the basic amplifier
chip you buy at Newark, DigiKey
and other distributors of electronic
components
The name operational amplifier
originates from its use in circuits
performing electronic circuit
operations, such as scaling,
summation, and integration in
analog computers
First integrated circuit (IC)
operational amplifiers were
introduced in the mid 1960s
Classic OpAmp: A741 amplifier
design (originally by Fairchild
Semiconductor)

Fairchild Semiconductor
A709 Operational Amplifier
(introduced 1965)
from Jaeger/Blalock, page 541

7.1 Ideal Operational Amplifier

The ideal operational

amplifier is an ideal
differential amplifier
with an additional
property: infinite
voltage gain

Ideal OpAmp characteristics:

Voltage Gain A =
Input Resistance Rid =
Output Resistance Ro = 0

Jaeger, Blalock, Fig. 11.3

Assumptions for circuit analysis:

Assumption 1: If the gain is infinite, the input voltage vid = vo/A must be
zero: vid = 0
Assumption 2: If input resistance is infinite, the two input currents i+ and
i must be zero: i+ = i = 0

Assumptions for Ideal OpAmp Analysis

Primary Assumptions:
Input voltage difference is zero: vid = 0
Input currents are zero: i+ = i = 0
Additional (Implicit) Assumptions:
Infinite common-mode rejection
Infinite power supply rejection
Infinite output voltage range (not limited by VEE vo VCC)
Infinite output current capability
Infinite open-loop bandwidth
Infinite slew rate
Zero output resistance
Zero input-bias currents and offset currents
Zero input-offset voltage

7.2 Analysis of Basic

Ideal OpAmp Circuits
Investigation of classical operational amplifier circuits including
7.2.1 Inverting amplifier circuit
7.2.2 Non-inverting amplifier circuit
7.2.3 Unity-gain buffer (or voltage follower)
7.2.4 Summing amplifier
7.2.5 Difference amplifier
7.2.6 Instrumentation amplifier
7.2.7 Generalized inverting amplifier
7.2.8 Low-pass filter
7.2.9 Integrator
7.2.10 Differentiator

7.2.1 Inverting Amplifier

Inverting Amplifier
Grounding positive (non-inverting) input
Connecting feedback network with resistors R1 and R2
between inverting input and signal source and inverting input
and amplifier output node, respectively
Circuit analysis yields
Voltage gain Av
Input resistance Rin
Output resistance Rout
Av, Rin and Rout are used
for two-port parameters

Jaeger, Blalock, Fig. 11.5

Inverting Amplifier (cont.)

Voltage Gain
v s = isR1 + i2R2 + v o
KVL along loop highlighted with arrow:
KCL at inverting input node (note: i = 0):
is = i2
Current is:

is =

vs v
R1

v s = isR1 + isR2 + v o
v =0
because
v+ =0 and
v+ =v

vs
R1

Eliminate is:
vs
0 = + R2 + v o
R1

vo
R2
Av =
=
vs
R1

Jaeger, Blalock, Fig. 11.6

Inverting Amplifier (cont.)

Voltage Gain
Av =

vo
R
= 2
vs
R1

Voltage gain is negative, i.e. inverting amplifier with 180

phase shift between input and output signal (for dc or
sinusoidal signals)
Magnitude of gain can be 1 for R2 R1 (most common case)
but also 1 for R1 R2
Inverted input terminal is virtual ground
The ideal op-amp adjusts its output to whatever voltage is
needed to force the differential input voltage to zero!

Inverting Amplifier (cont.)

Input/Output Resistance
vs v vs
=
Input resistance Rin directly from is =
R1
R1

vs
Rin =
= R1
is

Output Resistance Rout

Apply test current (or voltage) source to output and determine
voltage (or current); all independent voltage and current sources
are turned off, i.e. vs = 0
Rout =
i1=i2

v x i2R2 + i1R1
=
ix
ix

i1(R2 + R1)
ix

However i1 = 0, because
v = 0, i.e.
Rout = 0

Jaeger, Blalock, Fig. 11.7

7.2.2 Non-Inverting Amplifier

Voltage Gain
Non-Inverting Amplifier
Apply input signal to positive (non-inverting) input
Feedback portion (defined by resistors R1 and R2) of output
signal to the negative (inverting) input terminal
Analyze voltage divider
R1
v1 = v o
R1 + R2
KVL along loop incl. vs, vid, v1
vid =0

v s = v id + v1 = v1
Av =

v o R1 + R2
R
=
= 1+ 2 1
vs
R1
R1

Jaeger, Blalock,
Fig. 11.8

Non-Inverting Amplifier (cont.)

Input/Output Resistance
Input resistance Rin directly from

vs vs
Rin =
=
=
i+
0

Output Resistance Rout

Test Circuit to measure output resistance is identical to that for
inverting amplifier!

Rout = 0

Jaeger, Blalock, Fig. 11.7

7.2.3 Unity-Gain Buffer

Non-inverting amplifier
with R1 = and R2 = 0

R2
A v = 1+
=1
R1

Also called voltage follower,

because output voltage follows
input voltage

Jaeger, Blalock, Fig. 11.9

Why an amplifier with gain 1?

Tremendous impedance-level transformation while maintaining
signal level
Ideal unity-gain buffer does not require any input current and can
drive any desired resistive load without voltage loss
Suitable for transducers with high source impedance (e.g.
thermopiles) that cannot supply significant current to a load

Summary
Inverting/Non-Inverting Amplifier
Inverting
Amplifier
Voltage Gain
Av

R2

R1

Non-Inverting
Amplifier

R2
1+
R1

Input Resistance
Rin

R1

Output Resistance
Rout

7.2.4 Summing Amplifier

Two input sources are connected to inverting input of amplifier
Because inverting input represents virtual ground (vid = 0) and
i = 0, the output signal generated from the individual sources
are additive
R
R
v o = 3 v1 3 v 2
R1
R2
Output voltage sums the
scaled input voltages
Inverting input node is called
summing junction
Any number of inputs can
be connected to the
summing junction; this way,
a simple digital-to-analog
converter can be build

Jaeger, Blalock,
Fig. 11.10

7.2.5 Difference Amplifier

Amplifies difference
between two input
signals
Here, the operational
amplifier is used as
differential amplifier
Circuit analysis yields

vo =

Jaeger, Blalock,
Fig. 11.11

R2
(v1 v 2 )
R1

Input resistance of circuit is limited by resistors R1 and R2

7.2.6 Instrumentation Amplifier

Problem: we need to amplify the

difference of two signals but
cannot use the difference
amplifier because its input
impedance is too low
Solution: combine two noninverting amplifiers with
difference amplifier, forming
an instrumentation amplifier
Rin = for both inputs
Rout = 0 for difference amplifier

" R %
Amplification of OpAmp 3: v o = $ 4 ' (v a v b )
# R3 &

Voltage drop from va to vb: v a v b = i (R2 + 2R1 + R2 )

Voltage drop from v1 to v2: v1 v 2 = i (2R1)

Jaeger, Blalock, Fig. 11.12

R4 " R2 %
v o = $1+ ' (v1 v 2 )
R3 # R1 &

7.2.7 Generalized Inverting Amplifier

General concept: use inverting amplifier with general
impedances Z1(s) and Z2(s) as feedback network (instead R1
and R2)
v (s)
Z (s)
A v (s) = o
= 2
v s (s)
Z1(s)
Resulting in
Low-Pass Filter
Integrator
Differentiator

Jaeger, Blalock, Fig. 11.13

7.2.8 Active Low-Pass Filter

In contrast to passive RC-filter, the op-amp

based filter can have a gain > 1
Use RC element in feedback

Z1(s) = R1
Z 2 (s) = R2 !
A v (s) =

R2
1
=
sC sR2C +1

R2
R
1
1
= 2
R1 1+ sR2C
R1 1+ s / H

Single-Pole low-pass filter with

cut-off frequency (3dB point)

H = 2 fH =

1
R 2C

Cut-off frequency, low-frequency gain

and input resistance Rin = R1 can be chosen
independently with R1, R2 and C

Jaeger, Blalock,
Fig. 11.14

7.2.9 Integrator

Inverting amplifier with feedback

resistor R2 replaced by
capacitor C
Keeping in mind that the
inverting input is a virtual
ground, we find (Q = C V)

is =

vs
R

and ic = C

dv o
dt

With i = 0, we have is = ic and

integrating the above equations
yields
t

t
vs
dv o
d
=

C
0 R
0 dt d
t

1
v o (t) = v o (0)
v ()d
RC 0 s

Jaeger, Blalock,
Fig. 11.15

7.2.10 Differentiator
Compared to integrator
circuit, exchange R and C,
i.e. replace R1 of the
inverting amplifier with a
capacitor C
is = C

dv s
dt

and ic =

vo
R

With i = 0, we have is = ic
and find
v o (t) = RC

dv s
dt

Jaeger, Blalock,
Fig. 11.16

7.3 Design of Basic Operational

Amplifiers
Differential amplifiers are commonly used as input stage of
operational amplifiers providing the desired
Differential input
Common-mode rejection capabilities
Ground-referenced output signal
What about high voltage gain and low output resistance required
for a good operational amplifier?
Add second gain stage to boost voltage gain: commonemitter/source amplifier
Add output stage to provide low-output resistance and high
output current capability: e.g. emitter/source follower

BJT Operational Amplifier Prototype

Current bias for all three
stages
C-C (class A) output stage
often replaced by more
power efficient class-B or
class-AB stage

v2
v3

Jaeger, Blalock,
Fig. 15.26
Input Stage
2nd Gain Stage Output Stage
Differential Amplifier C-E Amplifier C-C Amplifier

A dm

# (04 + 1)RL &

&
v o v 2 v 3 v o # gm2
CC
#
&
=
=
= %
(RC r3 ) ( $ gm3 (ro3 Rin ) ' %
(
v id v id v 2 v 3 $ 2
r
+
(
+
1)R
'
L '
$ 3 04
RinCC = r 4 + (04 + 1)RL

Are you Ready to Understand the

Fairchild A741?
with bias circuitry

Not yet? try ECE 3050!

Jaeger, Blalock,
Fig. 15.92&93

7.4 Non-Ideal Operational Amplifiers

How do the characteristics of the operational amplifier
change if we remove one of the various explicit and
implicit assumptions (see Chapter 7.2)?
Lets explore
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6

Finite Open-Loop Gain

Non-Zero Output Resistance
Finite Input Resistance
Finite Common-Mode Rejection Ratio
DC Error Sources
Output Voltage/Current Limits

See Jaeger/Blalock, Chapter 12, page 610-658

Operational Amplifier
Open-Loop vs. Closed-Loop
Open-Loop Parameters
No external feedback elements
connected to op-amp
Open-loop gain A
Open-loop input resistance Rid
Open-loop output resistance Ro
Closed-Loop Parameters
Op-amp with feedback network
Closed-loop gain Av
Closed-loop input resistance Rin
Closed-loop output resistance Rout

Jaeger, Blalock,
Fig. 11.3

Jaeger, Blalock,
Fig. 12.1

7.4.1 Finite Open-Loop Gain

Example: Non-Inverting Amplifier

Open-Loop Gain:
Jaeger, Blalock,
Ideal op-amp: A =
Fig. 12.1
Real op-amp: A = 80-120 dB
How does a finite open-loop
gain affect the closed-loop
gain of non-inverting and
inverting amplifiers?
Extract closed-loop gain of
non-inverting amplifier (note that i = 0):
v o = A v id = A (v s v1) #
A1
%
vo
R2
A
1
A
=
=
=
=
1+
$
R1
v
v s 1+ A

R1
v1 =
vo = vo
%
R1 + R2
&
with feedback factor = R1 / (R1 + R2) and loop gain A
vs
Note: in case of finite open-loop gain, vid is no longer zero: v id =
1+ A

7.4.2 Non-zero Output Resistance

Output Resistance:
Jaeger, Blalock,
Ideal op-amp: Ro = 0
Fig. 12.3
Real op-amp: Ro,typ = 50
To determine output resistance
of (feedback) amplifier, apply
test source vx (instead of load RL)
and calculate ix (independent
sources are set to zero)
Assume op-amp with Ro 0 and finite gain A
!
ix = io + i2
#
i
1
1+ A
1
A v id + Roio = v x
= x =
+
"
Ro
R1 + R2
# Rout v x
v x = i2R2 + i1R1 = i2 (R2 + R1)$
Ro
R1+R2
1+A
Ro
Ro
Rout =
(R1 + R2 )

1+ A
1+ A
Note: circuit to determine output resistance is identical for inverting and
non-inverting amplifier

7.4.3 Finite Input Resistance

Non-Inverting Amplifier

Input Resistance:
Ideal op-amp: Rid =
Real op-amp: Rid = 1M 1T R1, R2
To determine input
resistance of (feedback)
amplifier, apply test
source vx and calculate ix

Jaeger, Blalock,
Fig. 12.4

(v x v1) = Rid ix
i i2

v1

R1
v = v o = A (v x v1)
R1 + R2 o

Eliminating v1 yields
ix =

vx

A
vx
vx
1+ A
=
Rid
(1+ A )Rid

Rin = Rid (1+ A ) Rid

Non-Ideal Inverting/Non-Inverting
Amplifiers
R1
R1 + R2

Inverting
Amplifier

Non-Inverting
Amplifier

Voltage Gain
Av

R2 # A &
R2
%
(
R1 $1+ A '
R1

R
A
1
= 1+ 2
1+ A
R1

Input Resistance
Rin

!
R2 $
R1 + #Rid
& R1
1+
A
"
%

Rid (1+ A ) Rid A

Output Resistance
Rout

Ro
R
o
1+ A A

Ro
R
o
1+ A A

7.5 Operational Amplifier

Frequency Response and Bandwidth

Most general-purpose op-amps

are low-pass amplifiers
designed to have single-pole
frequency response

A(s) =

A 0B
T
=
s + B s + B

A(j) =

A 0B
2 + B2

A0
2
1+ 2
B

with open-loop bandwidth B

and unity-gain frequency or
gain-bandwidth product T
Note: = 2 f

Jaeger, Blalock, Fig. 12.22

Operational Amplifier
Frequency Response and Bandwidth

At low frequencies B,
the amplifier gain is constant

A( B ) = A 0

At high frequencies B,
the gain decreases by 1 order
of magnitude (20dB) per decade

A( B ) = A 0

B T
=

The gain is 1 for = T

(note: this is where the name
gain-bandwidth product
GBW comes from)

A( = T ) = 1

Jaeger, Blalock, Fig. 12.22

Frequency Response
Non-Inverting Amplifier
Closed-loop gain for non-inverting amplifier:
Av =

A
1+ A

A 0B
s + B
A 0B
A(s)
A v (s) =
=
=
A
1+ A(s)
s + B (1+ A 0)
1+ 0 B
s + B

Dividing by B (1+ A) yields

A0
(1+ A 0)
A v (0)
A v (s) =
=
s
s
+1
+1
B (1+ A 0)
H

with the cutoff frequency

(i.e. amplifier bandwidth)

H = B (1+ A 0) = T

and the dc gain

A 0 A01 1
A v (0) =

(1+ A 0)

(1+ A 0)
T
=
A0
A v (0)
T

Frequency Response
Non-Inverting Amplifier

Note: A v (0) H = T

At low frequencies,
the voltage gain is
reduced by the
feedback network;
at high frequencies,
the gain follows the
gain of the op-amp
(Negative) feedback
reduces gain but
increases bandwidth
GBW remains constant!

Jaeger, Blalock, Fig. 12.23

Inverting/Non-Inverting Amplifiers
Frequency Response
Inverting
Amplifier

DC Voltage Gain

A v (0)

Feedback Factor

Bandwidth

R2
R1

1
1+ A v (0)

fB = fT

Non-Inverting
Amplifier
A v (0) = 1+

R2
R1

1
A v (0)

fB = fT

Large Signal Limitations

Slew Rate
So far, we have assumed that op-amp can respond
instantaneously to input signal changes, i.e. we have neglected
any capacitances in the internal circuit
In real operational amplifiers, the slew-rate (SR) defines the
maximum rate of change of the output voltage
For general-purpose op-amps, the slew-rate is typically in the
range of 0.1 V/s SR 10 V/s (much higher values are
possible in special designs)
The capacitances (finite slew-rate) will result in signal distortion
(reduced gain, phase shift)
The full-power bandwidth fM is the highest frequency at which
full-scale signal can be developed; denoting VFS the full-scale
output signal, one finds
SR
fM

2 VFS

Analog
Devices
AD8055
Supply 4-6 V
A = 71 dB
3-dB BW = 300 MHz
SR = 1.4 kV/s
Rin = 10 M
VOS = 3 mV
Output Voltage
Swing 3.1 V
(@ RL = 150 )
Max. Output
Current 60 mA
Cost: $0.85

(1000-4999 units)

Analog
Devices
AD8552
Supply 1.3-3 V
A = 145 dB
GBP = 1.5 MHz
VOS = 1 V
Max. Output
Current 30 mA
SR = 0.4 V/s

Cost: $1.71

(1000-4999 units)