Hspice Simulation of Nand and Inverter

ASSIGNMENT 1
EE6325
Nidhi Gundigara
UTD ID 2021235294
Date of submission: 03/03/2015
Answer1
I have designed CMOS inverter layout using 0.13um CMOS technology(minimum

L=0.13um)
a)For obtaining inverter sizing for neutral skew, I did the DC analysis. The schematic
for the DC analysis following. DC analysis was done in which Vin was swept from 0
to 1.2V
For determining k=wp/wn the parametric analysis was done in which k was
incremented from 1 to 10 in steps of 1 and Vout was plotted.
By parametric analysis k can be determined between 3 and 4.
For more accurate value of k, parametric analysis was done in which k was
incremented from 3 to 4 in steps of 0.1
Taking k=3.8 and wn = 280nm wp=280*3.88 = 1086nm i.e wp = 1.09u

For the new dimensions Vin vsVout plot is as below
Layout of 1x inverter: The layout passed DRC, LVS and PEX extraction was
done
b) layout of 4x inverter using multi finger technique : The layout
passed DRC, LVS and PEX extraction was done
Layout of driver cell (1x-4x) : The layout passed DRC, LVS and PEX
extraction was done
Layout of load cell(1x-1x) : The layout passed DRC, LVS and PEX
extraction was done
c) For determining tpHL and tpLH for 1x inverter, PEX extraction was done for 1x
inverter driver and load cell. And following hspice file was used
For fanout of 0, the load is commented in following file. To find fanout of 2 and 4
uncomment the line with load connection.
$transistor model
.include "/home/cad/kits/IBM_CMRF8SFLM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
.include test.sp
.include driver.sp
.include load.sp
.option post runlvl=5
vvdd vdd! gnd! 1.2V
vvdd1 vdd1! gnd! 1.2V
Vin in gnd! PULSE 0 1.2 50p 30ps 30ps 1.970ns 4ns
.tran 0.1ns 25ns sweep fanout 1 5 1
$measuring rise time and fall time
.measure tran trise trig v(out2) val=0.12V rise=1 targ v(out2)
val=1.08V rise=1
.measure tran tfall trig v(out2) val=1.08V fall=1 targ v(out2)
val=0.12V fall=1
$measuring tphl and tplh
.measure tran tphl trig v(out1) val=0.6V rise=1 targ v(out2) val=0.6V
fall=1
.measure tran tplh trig v(out1) val=0.6V fall=1 targ v(out2) val=0.6V
rise=1
x1 in out1 vdd! gnd! driver
x2 out1 out2 vdd1! gnd! test
x3 out2 out3 vdd! gnd! load m=fanout
.end
Results
Fanout
0
2
4
Tphl
15.93ps
31.00ps
45.24ps
d) For fanout of 4 we will sweep beta

the hspice file is as folowing
$transistor model
Tplh
13.09ps
25.96ps
38.29ps
.include "/home/cad/kits/IBM_CMRF8SFLM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
.include test.sp
.include driver.sp
.include load.sp
.option post runlvl=5
vvdd vdd! gnd! 1.2V
vvdd1 vdd1! gnd! 1.2V
Vin in gnd! PULSE 0 1.2 50p 30ps 30ps 1.970ns 4ns
$.tran 0.1ns 25ns sweep fanout 1 5 1
.tran 0.005ns 20ns sweep beta 0.1 10 1
.measure tran trise trig v(out2) val=0.12V rise=1 targ v(out2)
val=1.08V rise=1
.measure tran tfall trig v(out2) val=1.08V fall=1 targ v(out2)
val=0.12V fall=1
.measure tran tphl trig v(out1) val=0.6V rise=1 targ v(out2) val=0.6V
fall=1
.measure tran tplh trig v(out1) val=0.6V fall=1 targ v(out2) val=0.6V
rise=1
.measure
.measure
.measure
.measure
x1
x2
x3
x4
x5
x6
tran t_avg param = '(tphl + tplh)/2'

tran charge INTEG I(vvdd1) FROM 0 to 10ns
energy param ='charge*1.2'
EDP param = 'energy*t_avg'
in out1 vdd! gnd! driver

out1 out2 vdd1! gnd! test
out2 out3 vdd! gnd! load
.end
Results
The table below gives values of EDP for different values of beta. We can see that as
beta increases (i.e. inverter becomes more stronger) , the EDP decreases and stays
constant for higher values of beta
Beta
0.1
1.1
2.1
3.1
EDP
115.4e-25
12.6e-25
9.4e-25
8.5e-25
4.1
5.1
6.1
7.1
8.1
9.1
7.7e-25
7.6e-25
7.4e-25
7.1e-25
7.4e-25
7.7e-25
BETA V/S EDP

1.50E-23
1.00E-23
5.00E-24
0.00E+00
0
The mt0 file showing parameter values.
10
Answer2
3 input NAND gate schematic. We will use widths of inverter but for NMOS as length
is increasing 3 times, we will have to increase width also 3 times to keep w/l ratio
same of that of 1x inverter. For PMOS width will be same as 1x inverter PMOS
because only 1 transistor is there for worst case.
Schematic for NAND gate
Layout of NAND gate : The layout passed DRC, LVS and PEX extraction was
done
a) Nanosim was used for generating the output file.

2 files are needed for nanosim
1)nand.sp file is as follow

*
TRANSISTOR CARDS
*
*
.inc /home/cad/vlsi/models/hspice/cmos0.18um.model
.option post=1
.temp=27
.param pvdd=1.2v
*....MOSFETs
MT0 out A
net032
gnd! nfet L=0.12U
W=0.84U
+ AD=0.3192P
AS=0.1596P PD=2.44U
PS=1.22U
MT6 net032
B
net8 gnd! nfet L=0.12U
W=0.84U
+ AD=0.1596P
AS=0.1596P PD=1.22U
PS=1.22U
MT5 net8 C
gnd! gnd! nfet L=0.12U
W=0.84U
+ AD=0.1596P
AS=0.2772P PD=1.22U
PS=2.34U
MT3 out C
vdd! vdd! pfet L=0.12U
W=1.09U
+ AD=0.2071P
AS=0.3597P PD=1.47U
PS=2.84U
MT2 vdd! B
out vdd! pfet L=0.12U
W=1.09U
+ AD=0.2071P
AS=0.2071P PD=1.47U
PS=1.47U
MT1 out A
vdd! vdd! pfet L=0.12U
W=1.09U
+ AD=0.4142P
AS=0.2071P PD=2.94U
PS=1.47U
*
*
*
CAPACITOR CARDS
*
*
C1
vdd! gnd! 2.08609E-16
C2
A
gnd! 5.23719E-16
C3
B
gnd! 5.50805E-16
C4
C
gnd! 4.29496E-16
C5
out gnd! 4.91006E-16
C6
avC9 gnd! 8.76888E-17
C7
net8 gnd! 3.23361E-17
C8
net032
gnd! 2.65526E-17
*============================================================
* Stimulus, Analysis, etc.
*============================================================
VVdd Vdd 0 pvdd
VGND GND 0 0.0v
* Input pattern for A $00101
* Generated by "perl pbit2pwl.pl a,GND ns 0.05 5 00101"

Va A GND PWL 0ns 0 0.05ns 0 5ns 0 5.05ns pvdd 10.05ns pvdd 10.1ns 0
15ns 0 15.05ns pvdd
* Input pattern for B $00011
* Generated by "perl pbit2pwl.pl b,GND ns 0.05 5 00011"
Vb B GND PWL 0ns 0 0.05ns 0 5ns 0 10ns 0 10.05ns pvdd 15ns pvdd
* Input pattern for C $00011
* Generated by "perl pbit2pwl.pl b,GND ns 0.05 5 00011"
Vc C GND PWL 0ns 0 0.05ns 0 5ns 0 10ns 0 10.05ns pvdd 15ns pvdd
.TRANS 0.02ns 40ns
.END
2)nand.cfg file is as follows

print_node_v
print_node_i
report_node_powr
Results
Output waveform
A B C out
Vdd
Vdd
b)Using HSPICE simulation worst case tpHL and tpLH, average power dissipation for
fanout of 0 and 4 is measured. The following code measures the parameters for
fanout of 0. For fanout of 4 uncomment the 4 loads.
Results
Fanout
Tphl
Tplh
0
4
33.07ps
59.95ps
35.55ps
25.35ps
Answer 3
Average power
dissipation
2.72uW
7.52uW

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ASSIGNMENT 1

I have designed CMOS inverter layout using 0.13um CMOS technology(minimum

By parametric analysis k can be determined between 3 and 4.

Taking k=3.8 and wn = 280nm wp=280*3.88 = 1086nm i.e wp = 1.09u

b) layout of 4x inverter using multi finger technique : The layout

passed DRC, LVS and PEX extraction was done

d) For fanout of 4 we will sweep beta

tran t_avg param = '(tphl + tplh)/2'

in out1 vdd! gnd! driver

BETA V/S EDP

The mt0 file showing parameter values.

Schematic for NAND gate

a) Nanosim was used for generating the output file.

1)nand.sp file is as follow

* Generated by "perl pbit2pwl.pl a,GND ns 0.05 5 00101"

2)nand.cfg file is as follows

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