Analog Circuits

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
UNIT 3
Page 45
(A) 125 and 125

(C) 250 and 125
2013
3.1
The ac schematic of an NMOS common-source state is shown in the

figure below, where part of the biasing circuits has been omitted for
simplicity. For the n -channel MOSFET M, the transconductance
gm = 1 mA/V , and body effect and channel length modulation effect
are to be neglected. The lower cutoff frequency in HZ of the circuit
is approximately at
3.4
ANALOG CIRCUITS
ONE MARK
In the circuit shown below what is the output voltage ^Vouth if a

silicon transistor Q and an ideal op-amp are used?
(A) 8
(C) 50
(A) - 15 V
(C) + 0.7 V
3.2
(B) 125 and 250

(D) 250 and 250
(B) - 0.7 V
(D) + 15 V
In the circuit shown below the op-amps are ideal. Then, Vout in Volts
is
3.5
In a voltage-voltage feedback as shown below, which one of the

following statements is TRUE if the gain k is increased?
(B) 32
(D) 200
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(A) The input

es
(B) The input
increases
(C) The input
decreases
(D) The input
es
2013
3.3
impedance increases and output impedance decreas-
(A) 4
(C) 8
impedance increases and output impedance also

3.6
impedance decreases and output impedance also

impedance decreases and output impedance increas-
(B) 6
(D) 10
In the circuit shown below, Q1 has negligible collector-to-emitter

saturation voltage and the diode drops negligible voltage across it
under forward bias. If Vcc is + 5 V , X and Y are digital signals with
0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is
TWO MARKS
In the circuit shown below, the knee current of the ideal Zener
dioide is 10 mA. To maintain 5 V across RL , the minimum value of
RL in W and the minimum power rating of the Zener diode in mW
, respectively, are
(A) XY
(C) XY
3.7
(B) XY
(D) XY
A voltage 1000 sin wt Volts is applied across YZ . Assuming ideal

diodes, the voltage measured across WX in Volts, is
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Page 46
(A) cos (wt) - 1

(C) 1 - cos (wt)
(A) sin wt
(C) ^sin wt - sin wt h /2
3.8
(B) _sin wt + sin wt i /2

(D) 0 for all t
3.12
(B) sin (wt)

(D) 1 - sin (wt)
The impedance looking into nodes 1 and 2 in the given circuit is
In the circuit shown below, the silicon npn transistor Q has a

very high value of b . The required value of R2 in kW to produce
IC = 1 mA is
(A) 50 W
(C) 5 kW
(B) 100 W
(D) 10.1 kW
2012
3.13
(A) 20
(C) 40
3.9
O
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ONE MARK
The current ib through the base of a silicon npn transistor is

o.i
c
.
1 + 0.1 cos (10000pt) mA At 300 K, the rp in the small signal model dia
no
of the transistor is
(A) low pass filter with f3dB =
w.
1
rad/s
(R1 + R2) C
(B) high pass filter with f3dB = 1 rad/s
R1 C
(C) low pass filter with f3dB = 1 rad/s
R1 C
1
(D) high pass filter with f3dB =
rad/s
(R1 + R2) C
ww
(A) 250 W
(C) 25 W
3.10
(B) 27.5 W
(D) 22.5 W
3.14
The voltage gain Av of the circuit shown below is
The i -v characteristics of the diode in the circuit given below are

v - 0.7 A, v $ 0.7 V
i = * 500
0A
v < 0. 7 V
The current in the circuit is

(A) 10 mA
(C) 6.67 mA
3.11
The circuit shown is a
A
I
D
(B) 30
(D) 50
2012
TWO MARKS
(A) Av . 200
(C) Av . 20
(B) 9.3 mA
(D) 6.2 mA
The diodes and capacitors in the circuit shown are ideal. The voltage
v (t) across the diode D1 is
2011
3.15
(B) Av . 100
(D) Av . 10
ONE MARK
In the circuit shown below, capacitors C1 and C2 are very large and
are shorts at the input frequency. vi is a small signal input. The gain
magnitude vo at 10 M rad/s is
vi
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Page 47
3.19
For a BJT, the common base current gain a = 0.98 and the collector
base junction reverse bias saturation current ICO = 0.6 mA . This
BJT is connected in the common emitter mode and operated in the
active region with a base drive current IB = 20 mA . The collector
current IC for this mode of operation is
(A) 0.98 mA
(B) 0.99 mA
(C) 1.0 mA
(D) 1.01 mA
Statement for Linked Answer Questions: 4.6 & 4.7

(A) maximum
(C) unity
3.16
In the circuit shown below, assume that the voltage drop

across a forward biased diode is 0.7 V. The thermal voltage
Vt = kT/q = 25 mV . The small signal input vi = Vp cos ^wt h where
Vp = 100 mV.
(B) minimum
(D) zero
The circuit below implements a filter between the input current ii

and the output voltage vo . Assume that the op-amp is ideal. The
filter implemented is a
3.20
(A) low pass filter

(C) band stop filter
A
I
D
(B) band pass filter

(D) high pass filter
3.21
O
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2011
3.17
The ac output voltage vac is

(A) 0.25 cos ^wt h mV
(C)in2 cos (wt) mV
(B) 1 cos (wt) mV

(D) 22 cos (wt) mV
In the circuit shown below, for the MOS transistors, mn Cox = 100 mA/V 2
.co
a
i
and the threshold voltage VT = 1 V . The voltage Vx at the source of no d
2010
ONE MARK
w.
the upper transistor is
w
w
3.22
The amplifier circuit shown below uses a silicon transistor. The
capacitors CC and CE can be assumed to be short at signal frequency
and effect of output resistance r0 can be ignored. If CE is disconnected
from the circuit, which one of the following statements is true
(A) 1 V
(C) 3 V
3.18
TWO MARKS
The bias current IDC through the diodes is

(A) 1 mA
(B) 1.28 mA
(C) 1.5 mA
(D) 2 mA
(B) 2 V
(D) 3.67 V
For the BJT,

in the circuit shown below,
Q1
b = 3, VBEon = 0.7 V, VCEsat = 0.7 V . The switch is initially closed.
At time t = 0 , the switch is opened. The time t at which Q1 leaves
the active region is
(A) The input resistance Ri increases and magnitude of voltage
gainAV decreases
(B) The input resistance Ri decreases and magnitude of voltage
gain AV increases
(C) Both input resistance Ri and magnitude of voltage gain AV
decreases
(D) Both input resistance Ri and the magnitude of voltage gain
AV increases
3.23
(A) 10 ms
(C) 50 ms
(B) 25 ms
(D) 100 ms
In the silicon BJT circuit shown below, assume that the emitter
area of transistor Q1 is half that of transistor Q2

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Page 48
The value of current Io is approximately

(A) 0.5 mA
(B) 2 mA
(C) 9.3 mA
(D) 15 mA
3.24
Assuming the OP-AMP to be ideal, the voltage gain of the amplifier

shown below is
(A) - R2
R1
R || R 3
(C) - 2
R1
(B) - R 3
R1
(D) -b R2 + R 3 l
R1
2010
Common Data For Q. 4.11 & 4.12 :
A
I
D
2009
TWO MARKS
3.28
O
N
In the circuit below, the diode is ideal. The voltage V is given by
in
Consider the common emitter amplifier shown below with the folco.
.
a
lowing circuit parameters:
di
o
n
b = 100, gm = 0.3861 A/V, r0 = 259 W, RS = 1 kW, RB = 93 kW,
w.
w
w
RC = 250 kW, RL = 1 kW, C1 = 3 and C2 = 4.7 mF
(A) min (Vi, 1)
(C) min (- Vi, 1)
3.29
3.25
3.26
3.27
TWO MARKS
(B) max (Vi, 1)

(D) max (- Vi, 1)
In the following a stable multivibrator circuit, which properties of

v0 (t) depend on R2 ?
The resistance seen by the source vS is

(A) 258 W
(B) 1258 W
(C) 93 kW
(D) 3
The lower cut-off frequency due to C2 is
(A) 33.9 Hz
(B) 27.1 Hz
(C) 13.6 Hz
(D) 16.9 Hz
The transfer characteristic for the precision rectifier circuit shown
below is (assume ideal OP-AMP and practical diodes)
(A) Only the frequency

(B) Only the amplitude
(C) Both the amplitude and the frequency
(D) Neither the amplitude nor the frequency
Statement for Linked Answer Question 4.16 and 4.17

Consider for CMOS circuit shown, where the gate voltage v0 of
the n-MOSFET is increased from zero, while the gate voltage of
the p -MOSFET is kept constant at 3 V. Assume, that, for both
transistors, the magnitude of the threshold voltage is 1 V and the
product of the trans-conductance parameter is 1mA. V - 2

Page 49
2008
In the following limiter circuit, an input voltage Vi = 10 sin 100pt

is applied. Assume that the diode drop is 0.7 V when it is forward
biased. When it is forward biased. The zener breakdown voltage is
6.8 V
The maximum and minimum values of the output voltage respectively are
3.34
3.30
3.31
3.32
For small increase in VG beyond 1V, which of the following gives the
correct description of the region of operation of each MOSFET
(A) Both the MOSFETs are in saturation region
(B) Both the MOSFETs are in triode region
(C) n-MOSFETs is in triode and p -MOSFET is in saturation
region
(D) n- MOSFET is in saturation and p -MOSFET is in triode
region
(A) 6.1 V, - 0.7 V

(C) 7.5 V, - 0.7 V
Estimate the output voltage V0 for VG = 1.5 V. [Hints : Use the

appropriate current-voltage equation for each MOSFET, based on
the answer to Q.4.16]
(A) 4 - 1
(B) 4 + 1
2
2
(C) 4 - 3
(D) 4 + 3
2
2
ONE MARK
(B) 0.7 V, - 7.5 V

(D) 7.5 V, - 7.5 V
2008
For the circuit shown in the following figure, transistor M1 and M2

are identical NMOS transistors. Assume the M2 is in saturation and
the output is unloaded.
3.35
In the circuit shown below, the op-amp is ideal, the transistor has
VBE = 0.6 V and b = 150 . Decide whether the feedback in the circuit
is positive or negative and determine the voltage V at the output of
the op-amp.
TWO MARSK
O
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3.36
The current Ix is related to Ibias as

(A) Ix = Ibias + Is
(B) Ix = Ibias
(C) Ix = Ibias - cVDD - Vout m
(D) Ix = Ibias - Is
RE
Consider the following circuit using an ideal OPAMP. The I-V
V
characteristic of the diode is described by the relation I = I 0 _eV - 1i
where VT = 25 mV, I0 = 1m A and V is the voltage across the diode
(taken as positive for forward bias). For an input voltage Vi =- 1 V
, the output voltage V0 is
t
(A) Positive feedback, V = 10 V

(B) Positive feedback, V = 0 V
(C) Negative feedback, V = 5 V
(D) Negative feedback, V = 2 V
3.33
A small signal source Vi (t) = A cos 20t + B sin 106 t is applied to a

transistor amplifier as shown below. The transistor has b = 150 and
hie = 3W . Which expression best approximate V0 (t)
(A) 0 V
(C) 0.7 V
3.37
(B) 0.1 V
(D) 1.1 V
The OPAMP circuit shown above represents a
(A) V0 (t) =- 1500 (A cos 20t + B sin 106 t)

(B) V0 (t) = - 1500( A cos 20t + B sin 106 t)
(C) V0 (t) =- 1500B sin 106 t
(D) V0 (t) =- 150B sin 106 t
(A) high pass filter

(C) band pass filter
(B) low pass filter

(D) band reject filter

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3.38
3.39
Page 50
Two identical NMOS transistors M1 and M2 are connected as shown

below. Vbias is chosen so that both transistors are in saturation. The
equivalent gm of the pair is defied to be 2Iout at constant Vout
2Vi
The equivalent gm of the pair is
(A) the sum of individual gm ' s of the transistors

(B) the product of individual gm s of the transistors
(C) nearly equal to the gm of M1
g
(D) nearly equal to m of M2
g0
Consider the Schmidt trigger circuit shown below
A triangular wave which goes from -12 to 12 V is applied to the
inverting input of OPMAP. Assume that the output of the OPAMP swings from +15 V to -15 V. The voltage at the non-inverting
input switches between
(A) - 12V to +12 V

(C) -5 V to +5 V
In a transconductance amplifier, it is desirable to have

(A) a large input resistance and a large output resistance
(B) a large input resistance and a small output resistance
(C) a small input resistance and a large output resistance
(D) a small input resistance and a small output resistance
3.43
2007
For the Op-Amp circuit shown in the figure, V0 is
3.44
A
I
D
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N
(B) -7.5 V to 7.5 V

(D) 0 V and 5 V
Statement for Linked Answer Question 3.26 and 3.27:
(A) -2 V
.in -0.5 V
o(C)
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3.45
TWO MARKS
(B) -1 V
(D) 0.5 V
For the BJT circuit shown, assume that the b of the transistor is
very large and VBE = 0.7 V. The mode of operation of the BJT is
In the following transistor circuit, VBE = 0.7 V, r3 = 25 mV/IE , and

b and all the capacitances are very large
(A) cut-off
(C) normal active
3.46
3.40
3.41
The value of DC current IE is

(A) 1 mA
(C) 5 mA
(B) 2 mA
(D) 10 mA
In the Op-Amp circuit shown, assume that the diode current

follows the equation I = Is exp (V/VT ). For Vi = 2V, V0 = V01, and for
Vi = 4V, V0 = V02 .
The relationship between V01 and V02 is
The mid-band voltage gain of the amplifier is approximately

(A) -180
(B) -120
(C) -90
(D) -60
2007
3.42
(B) saturation
(D) reverse active
The correct full wave rectifier circuit is
(A) V02 = 2 Vo1

(C) Vo2 = Vo1 1n2
ONE MARK
3.47
(B) Vo2 = e2 Vo1

(D) Vo1 - Vo2 = VT 1n2
In the CMOS inverter circuit shown, if the trans conductance

parameters of the NMOS and PMOS transistors are
W
kn = kp = mn Cox Wn = mCox p = 40mA/V2
Ln
Lp
and their threshold voltages ae VTHn = VTHp = 1 V the current I is

Page 51
initially uncharged. At t = 0 the switch S is closed. The Vc across

the capacitor at t = 1 millisecond is
In the figure shown above, the OP-AMP is supplied with ! 15V .
(A) 0 A
(C) 45 mA
3.48
(B) 25 mA
(D) 90 mA
For the Zener diode shown in the figure, the Zener voltage at knee is
7 V, the knee current is negligible and the Zener dynamic resistance
is 10 W. If the input voltage (Vi) range is from 10 to 16 V, the output
voltage (V0) ranges from
(A) 0 Volt
(C) 9.45 Volts
For the circuit shown below, assume that the zener diode is ideal
with a breakdown voltage of 6 volts. The waveform observed across
R is
3.54
(A) 7.00 to 7.29 V

(C) 7.14 to 7.43 V
(B) 6.3 Volt

(D) 10 Volts
(B) 7.14 to 7.29 V

(D) 7.29 to 7.43 V
Statement for Linked Answer Questions 4.35 & 4.36:

Consider the Op-Amp circuit shown in the figure.
3.49
3.50
The transfer function V0 (s)/ Vi (s) is

(A) 1 - sRC
(B) 1 + sRC
1 + sRC
1 - sRC
1
1
(C)
(D)
1 - sRC
1 + sRC
3.52
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Common Data For Q. 4.41, 4.42 and 4.43 :

In the transistor amplifier circuit shown in the figure below, the
transistor has the following parameters:
bDC = 60 , VBE = 0.7V, hie " 3
The capacitance CC can be assumed to be infinite.
In the figure above, the ground has been shown by the symbol 4
ONE MARK
The input impedance (Zi) and the output impedance (Z0) of an ideal
trans-conductance (voltage controlled current source) amplifier are
(A) Zi = 0, Z0 = 0
(B) Zi = 0, Z0 = 3
(C) Zi = 3, Z0 = 0
(D) Zi = 3, Z0 = 3
An n-channel depletion MOSFET has following two points on its
ID - VGs curve:
(i) VGS = 0 at ID = 12 mA and
(ii) VGS =- 6 Volts at ID = 0 mA
Which of the following Q point will given the highest trans conductance gain for small signals?
(A) VGS =- 6 Volts
(B) VGS =- 3 Volts
(C) VGS = 0 Volts
(D) VGS = 3 Volts
2006
3.53
O
N
.in
If Vi = V1 sin (wt) and V0 = V2 sin (wt + f), then the minimum and
maximum values of f (in radians) are respectively
(A) - p and p
(B) 0 and p
2
2
2
(C) - p and 0
(D) - p and 0
2
2006
3.51
A
I
D
TWO MARKS
For the circuit shown in the following figure, the capacitor C is
3.55
3.56
Under the DC conditions, the collector-or-emitter voltage drop is

(A) 4.8 Volts
(B) 5.3 Volts
(C) 6.0 Volts
(D) 6.6 Volts
If bDC is increased by 10%, the collector-to-emitter voltage drop
(A) increases by less than or equal to 10%
(B) decreases by less than or equal to 10%
(C) increase by more than 10%

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Page 52
(D) decreases by more than 10%

3.57
(B) increases the common mode gain only.

(C) decreases the differential mode gain only.
(D) decreases the common mode gain only.
The small-signal gain of the amplifier vc is

vs
(A) -10
(B) -5.3
(C) 5.3
(D) 10
3.64
Common Data For Q. 4.44 & 4.45:
For an npn transistor connected as shown in figure VBE = 0.7 volts.

Given that reverse saturation current of the junction at room
temperature 300 K is 10 - 13 A, the emitter current is
A regulated power supply, shown in figure below, has an unregulated input (UR) of 15 Volts and generates a regulated output Vout .
Use the component values shown in the figure.
(A) 30 mA
(C) 49 mA
3.65
3.58
3.59
3.61
3.62
A
I
D
If the unregulated voltage increases by 20%, the power dissipation

across the transistor Q1
(A) increases by 20%
(B) increases by 50%
(C) remains unchanged
(D) decreases by 20%
O
N
ONE MARK
The input resistance Ri of the amplifier shown in the figure is
(A) 30 kW
4
(B) 10 kW
(C) 40 kW
(D) infinite
(A) Bias current of the inverting input only

(B) Bias current of the inverting and non-inverting inputs only
(C) Input offset current only
(D)
in Both the bias currents and the input offset current
co.
.
a
di The Op-amp circuit shown in the figure is filter. The type of filter
3.66
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and its cut. Off frequency are respectively
(A) high pass, 1000 rad/sec.

(C) high pass, 1000 rad/sec
The effect of current shunt feedback in an amplifier is to

(A) increase the input resistance and decrease the output resistance
(B) increases both input and output resistance
(C) decrease both input and output resistance
(D) decrease the input resistance and increase the output resistance
3.67
(B) Low pass, 1000 rad/sec

(D) low pass, 10000 rad/sec
The circuit using a BJT with b = 50 and VBE = 0.7V is shown in

the figure. The base current IB and collector voltage by VC and
respectively
The cascade amplifier is a multistage configuration of

(A) CC - CB
(B) CE - CB
(C) CB - CC
(D) CE - CC
2005
3.63
The voltage e0 is indicated in the figure has been measured by an

ideal voltmeter. Which of the following can be calculated ?
The power dissipation across the transistor Q1 shown in the figure is

(A) 4.8 Watts
(B) 5.0 Watts
(C) 5.4 Watts
(D) 6.0 Watts
2005
3.60
(B) 39 mA
(D) 20 mA
(A) 43 mA and 11.4 Volts

(C) 45 mA and 11 Volts
TWO MARKS
In an ideal differential amplifier shown in the figure, a large value

of (RE ).
(A) increase both the differential and common - mode gains.
3.68
(B) 40 mA and 16 Volts

(D) 50 mA and 10 Volts
The Zener diode in the regulator circuit shown in the figure has a
Zener voltage of 5.8 volts and a zener knee current of 0.5 mA. The
maximum load current drawn from this current ensuring proper

Page 53
functioning over the input voltage range between 20 and 30 volts, is
(A) 23.7 mA
(C) 13.7 mA
3.69
(B) 14.2 mA
(D) 24.2 mA
Both transistors T1 and T2 show in the figure, have a b = 100 ,

threshold voltage of 1 Volts. The device parameters K1 and K2 of
T1 and T2 are, respectively, 36 mA/V2 and 9 mA/V 2 . The output
voltage Vo i s
(A) 1 V
(C) 3 V
(B) 2 V
(D) 4 V
Common Data For Q. 4.58, 4.59 and 4.60 :
A
I
D
2004
Given, rd = 20kW , IDSS = 10 mA, Vp =- 8 V
ONE MARK
An ideal op-amp is an ideal

(A) voltage controlled current source
(B) nvoltage controlled voltage source
o.i current controlled current source
c
(C)
.
dia (D) current controlled voltage source
o
.n
3.74
O
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3.70
3.71
3.72
3.73
Zi and Z0 of the circuit are respectively

(A) 2 MW and 2 kW
(B) 2 MW and 20 kW
11
(C) infinity and 2 MW
(D) infinity and 20 kW
11
ID and VDS under DC conditions are respectively
(A) 5.625 mA and 8.75 V
(B) 1.875 mA and 5.00 V
(C) 4.500 mA and 11.00 V
(D) 6.250 mA and 7.50 V
3.75
3.76
Transconductance in milli-Siemens (mS) and voltage gain of the

amplifier are respectively
(A) 1.875 mS and 3.41
(B) 1.875 ms and -3.41
(C) 3.3 mS and -6
(D) 3.3 mS and 6
Given the ideal operational amplifier circuit shown in the figure
indicate the correct transfer characteristics assuming ideal diodes
with zero cut-in voltage.
Voltage series feedback (also called series-shunt feedback) results in

(A) increase in both input and output impedances
(B) decrease in both input and output impedances
(C) increase in input impedance and decrease in output impedance
(D) decrease in input impedance and increase in output impedance
The circuit in the figure is a
(A) low-pass filter

(C) band-pass filter
(B) high-pass filter

(D) band-reject filter
2004
3.77
TWO MARKS
A bipolar transistor is operating in the active region with a collector

current of 1 mA. Assuming that the b of the transistor is 100 and
the thermal voltage (VT ) is 25 mV, the transconductance (gm) and
the input resistance (rp) of the transistor in the common emitter
configuration, are
(A) gm = 25 mA/V and rp = 15.625 kW
(B) gm = 40 mA/V and rp = 4.0 kW
(C) gm = 25 mA/V and rp = 2.5 k W

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Page 54
(D) gm = 40 mA/V and rp = 2.5 kW

3.78
The value of C required for sinusoidal oscillations of frequency 1

kHz in the circuit of the figure is
(A) IC = 1 mA, VCE = 4.7 V

(C) IC = 1 mA, VCE = 2.5 V
(A) 1 mF
2p
1
mF
(C)
2p 6
3.79
2003
(B) 2p mF
3.83
(D) 2p 6 mF
In the op-amp circuit given in the figure, the load current iL is
3.80
3.81
3.82
(B) Vs
R2
(D) Vs
R1
O
N
The circuit shown in the figure is best described as a
.in
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ia.
od
In the voltage regulator shown in the figure, the load current can.n
ww
vary from 100 mA to 500 mA. Assuming that the Zener diode iswideal
(i.e., the Zener knee current is negligibly small and Zener resistance 3.85
is zero in the breakdown region), the value of R is
(A) 7 W
(B) 70 W
(C) 70 W
(D) 14 W
3
In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc
and peak values of the voltage respectively across a resistive load. If
PIV is the peak inverse voltage of the diode, then the appropriate
relationships for this rectifier are
(A) Vdc = Vm , PIV = 2Vm
(B) Idc = 2 Vm , PIV = 2Vm
p
p
(C) Vdc = 2 Vm , PIV = Vm
(D) Vdc Vm , PIV = Vm
p
p
Assume that the b of transistor is extremely large and VBE = 0.7V, IC
and VCE in the circuit shown in the figure
ONE MARK
Choose the correct match for input resistance of various amplifier

configurations shown below :
Configuration
Input resistance
CB : Common Base
LO : Low
CC : Common Collector
MO : Moderate
CE : Common Emitter
HI : High
(A) CB - LO, CC - MO, CE - HI
(B) CB - LO, CC - HI, CE - MO
(C) CB - MO, CC - HI, CE - LO
(D) CB - HI, CC - LO, CE - MO
A
I
D
3.84
(A) - Vs
R2
(C) - Vs
RL
(B) IC = 0.5 mA, VCE = 3.75 V

(D) IC = 0.5 mA, VCE = 3.9 V
(A) bridge rectifier

(C) frequency discriminator
If the input to the ideal comparators shown in the figure is a

sinusoidal signal of 8 V (peak to peak) without any DC component,
then the output of the comparators has a duty cycle of
(A) 1/2
(C) 1/6
3.86
3.87
(B) 1/3
(D) 1/2
If the differential voltage gain and the common mode voltage gain
of a differential amplifier are 48 dB and 2 dB respectively, then
common mode rejection ratio is
(A) 23 dB
(B) 25 dB
(C) 46 dB
(D) 50 dB
Generally, the gain of a transistor amplifier falls at high frequencies
due to the
(A) internal capacitances of the device
(B) coupling capacitor at the input
(C) skin effect
(D) coupling capacitor at the output
2003
3.88
(B) ring modulator

(D) voltage double
TWO MARKS
An amplifier without feedback has a voltage gain of 50, input

resistance of 1 k W and output resistance of 2.5 kW. The input

Page 55
input resistance of 1 kW and output resistance of 250 W are cascaded.

The opened circuit voltages gain of the combined amplifier is
(A) 49 dB
(B) 51 dB
(C) 98 dB
(D) 102 dB
resistance of the current-shunt negative feedback amplifier using the

above amplifier with a feedback factor of 0.2, is
(B) 1 kW
(A) 1 kW
11
5
(C) 5 kW
3.89
(D) 11 kW
3.94
In the amplifier circuit shown in the figure, the values of R1 and R2

are such that the transistor is operating at VCE = 3 V and IC = 1.5
mA when its b is 150. For a transistor with b of 200, the operating
point (VCE , IC ) is
An ideal sawtooth voltages waveform of frequency of 500 Hz and

amplitude 3 V is generated by charging a capacitor of 2 mF in every
cycle. The charging requires
(A) Constant voltage source of 3 V for 1 ms
(B) Constant voltage source of 3 V for 2 ms
(C) Constant voltage source of 1 mA for 1 ms
(D) Constant voltage source of 3 mA for 2 ms
2002
3.95
(A) (2 V, 2 mA)
(C) (4 V, 2 mA)
3.90
(B) (3 V, 2 mA)
(D) (4 V, 1 mA)
The oscillator circuit shown in the figure has an ideal inverting

amplifier. Its frequency of oscillation (in Hz) is
ONE MARK
In a negative feedback amplifier using voltage-series (i.e. voltagesampling, series mixing) feedback.
(A) Ri decreases and R0 decreases
(B) Ri decreases and R0 increases
(C) Ri increases and R0 decreases
(D) Ri increases and R0 increases
(Ri and R0 denote the input and output resistance respectively)
A 741-type opamp has a gain-bandwidth product of 1 MHz. A noninverting amplifier suing this opamp and having a voltage gain of 20
dB will exhibit a -3 dB bandwidth of
(A) 50 kHz
(B) 100 kHz
(C) 1000 kHz
(D) 1000 kHz
17
7.07
3.97
Three
in identical RC-coupled transistor amplifiers are cascaded. If
.
o
c
of the amplifiers has a frequency response as shown in the
ia. each
d
figure, the overall frequency response is as given in
o
3.96
1
(2p 6 RC)
1
(C)
( 6 RC)
(A)
3.91
(D)
6
(2pRC)
O
N
.
ww
(B) 6 V
(D) 12 V
If the op-amp in the figure is ideal, the output voltage Vout will be
equal to
(A) 1 V
(C) 14 V
3.93
1
(2pRC)
The output voltage of the regulated power supply shown in the

figure is
(A) 3 V
(C) 9 V
3.92
(B)
A
I
D
(B) 6 V
(D) 17 V
2002
Three identical amplifiers with each one having a voltage gain of 50,
3.98
TWO MARKS
The circuit in the figure employs positive feedback and is

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intended to generate sinusoidal oscillation. If at a frequency

V (f) 1
f0, B (f) = 3 f
= +0c, then to sustain oscillation at this frequency
V0 (f)
6
(A) R2 = 5R1
(C) R2 = R1
6
3.99
3.100
3.104
3.105
3.106
A zener diode regulator in the figure is to be designed to meet the

specifications: IL = 10 mA V0 = 10 V and Vin varies from 30 V to 50
V. The zener diode has Vz = 10 V and Izk (knee current) =1 mA. For
satisfactory operation
O
N
(B) 2000W # R # 2200W

(D) R $ 4000W
3.102
The current gain of a BJT is

(A) gm r0
(C) gm rp
3.103
An npn BJT has gm = 38 mA/V, C m = 10-14 F, C p = 4 # 10-13 F,

and DC current gain b0 = 90 . For this transistor fT and fb are
(A) fT = 1.64 # 108 Hz and fb = 1.47 # 1010 Hz
(B) fT = 1.47 # 1010 Hz and fb = 1.64 # 108 Hz
(C) fT = 1.33 # 1012 Hz and fb = 1.47 # 1010 Hz
(D) fT = 1.47 # 1010 Hz and fb = 1.33 # 1012 Hz
The transistor shunt regulator shown in the figure has a regulated
output voltage of 10 V, when the input varies from 20 V to 30 V.
The relevant parameters for the zener diode and the transistor are
: Vz = 9.5 , VBE = 0.3 V, b = 99 , Neglect the current through RB .
Then the maximum power dissipated in the zener diode (Pz ) and the
transistor (PT ) are
.in
no
w.
co
ia.
ww
3.107
(B) -16
(D) -6
2001
TWO MARKS
A
I
D
The voltage gain Av = v0 of the JFET amplifier shown in the figure

vt
is IDSS = 10 mA Vp =- 5 V(Assume C1, C2 and Cs to be very large
(A) +16
(C) +8
Consider the following two statements :

Statement 1 :
A stable multi vibrator can be used for generating square wave.
Statement 2:
Bistable multi vibrator can be used for storing binary information.
(A) Only statement 1 is correct
(B) Only statement 2 is correct
(C) Both the statements 1 and 2 are correct
(D) Both the statements 1 and 2 are incorrect
2001
An amplifier using an opamp with a slew-rate SR = 1 V/m sec has

a gain of 40 dB. If this amplifier has to faithfully amplify sinusoidal
signals from dc to 20 kHz without introducing any slew-rate induced
distortion, then the input signal level must not exceed.
(A) 795 mV
(B) 395 mV
(C) 79.5 mV
(D) 39.5 mV
(A) R # 1800W
(C) 3700W # R # 4000W
3.101
(B) R2 = 6R1
(D) R2 = R1
5
Page 56
(A)
(B)
(C)
(D)
Pz = 75 mW, PT = 7.9 W
Pz = 85 mW, PT = 8.9 W
Pz = 95 mW, PT = 9.9 W
Pz = 115 mW, PT = 11.9 W
The oscillator circuit shown in the figure is
4
(A) Hartely oscillator with foscillation = 79.6 MHz
(B) Colpitts oscillator with foscillation = 50.3 MHz
(C) Hartley oscillator with foscillation = 159.2 MHz
(D) Colpitts oscillator with foscillation = 159.3 MHz
ONE MARK
gm
r
g
(D) m
rp
(B)
3.108
The inverting OP-AMP shown in the figure has an open-loop gain

of 100.
Thee ideal OP-AMP has the following characteristics.

(A) Ri = 3, A = 3, R0 = 0
(B) Ri = 0, A = 3, R0 = 0
(C) Ri = 3, A = 3, R0 = 3
(D) Ri = 0, A = 3, R0 = 3

Page 57
(C) parasitic inductive elements

(D) the Early effect
If the op-amp in the figure, is ideal, then v0 is
3.114
The closed-loop gain V0 is

Vs
(A) - 8
(C) - 10
3.109
(B) - 9
(D) - 11
(A) zero
(C) - (V1 + V2) sin wt
In the figure assume the OP-AMPs to be ideal. The output v0 of

the circuit is
The configuration of the figure is a
3.115
(A) 10 cos (100t)

(C) 10 - 4
(B) 10
#0 cos (100t) dt
#0 cos (100t) dt
(D) 10 - 4 d cos (100t)

dt
2000
3.110
(B) (V1 - V2) sin wt

(D) (V1 + V2) sin wt
A
I
D
ONE MARK
In the differential amplifier of the figure, if the source resistance of

the current source IEE is infinite, then the common-mode gain is
O
N
(A) precision integrator

(B) Hartely oscillator
(C) Butterworth high pass filter (D) Wien-bridge oscillator
Assume that the op-amp of the figure is ideal. If vi is a triangular

wave, then v0 will be
3.116
.in
no
w.
co
ia.
ww
(A) square wave

(C) parabolic wave
3.117
(A) zero
(B) infinite
(D) Vin1 + Vin2
2VT
(C) indeterminate
3.111
In the circuit of the figure, V0 is
(B) triangular wave

(D) sine wave
The most commonly used amplifier is sample and hold circuits is

(A) a unity gain inverting amplifier
(B) a unity gain non-inverting amplifier
(C) an inverting amplifier with a gain of 10
(D) an inverting amplifier with a gain of 100
2000
3.118
(A) -1 V
(C) +1 V
3.112
3.113
(B) 2 V
(D) +15 V
TWO MARKS
In the circuit of figure, assume that the transistor is in the active

region. It has a large b and its base-emitter voltage is 0.7 V. The
value of Ic is
Introducing a resistor in the emitter of a common amplifier stabilizes

the dc operating point against variations in
(A) only the temperature
(B) only the b of the transistor
(C) both temperature and b
(D) none of the above
The current gain of a bipolar transistor drops at high frequencies
because of
(A) transistor capacitances
(B) high current effects in the base
(A) Indeterminate since Rc is not given (B) 1 mA

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(C) 5 mA
3.119
Page 58
(D) 10 mA
type
If the op-amp in the figure has an input offset voltage of 5 mV and

an open-loop voltage gain of 10000, then v0 will be
(A) current series

(C) voltage series
(A) 0 V
(C) + 15 V or -15 V
(B) 5 mV
(D) +50 V or -50 V
1999
3.120
3.121
3.122
3.127
ONE MARK
The first dominant pole encountered in the frequency response of a

compensated op-amp is approximately at
(A) 5 Hz
(B) 10 kHz
(C) 1 MHz
(D) 100 MHz
Negative feedback in an amplifier
(A) reduces gain
(B) increases frequency and phase distortions
(C) reduces bandwidth
(D) increases noise
3.128
3.129
(B) current shunt

(D) voltage shunt
In a differential amplifier, CMRR can be improved by using an

increased
(A) emitter resistance
(B) collector resistance
(C) power supply voltages
(D) source resistance
From a measurement of the rise time of the output pulse of an
amplifier whose is a small amplitude square wave, one can estimate
the following parameter of the amplifier
(A) gain-bandwidth product
(B) slow rate
(C) upper 3dB frequency
(D) lower 3dB frequency
The emitter coupled pair of BJTs given a linear transfer relation
between the differential output voltage and the differential output
voltage and the differential input voltage Vid is less a times the
thermal voltage, where a is
(A) 4
(B) 3
(C) 2
(D) 1
A
I
D
In the cascade amplifier shown in the given figure, if the commonemitter stage (Q1) has a transconductance gm1 , and the common
base stage (Q2) has a transconductance gm2 , then the overall
transconductance g (= i 0 /vi) of the cascade amplifier is
In a shunt-shunt negative feedback amplifier, as compared to the

basic amplifier
(A) both, input and output impedances,decrease
.in input impedance decreases but output impedance increases
o(B)
c
.
dia (C) input impedance increase but output
o
.n
w
(D) both input and output impedances increases.
w
3.130
O
N
w
(A) gm1
g
(C) m1
2
3.123
(B) gm2
g
(D) m2
2
1998
3.131
Crossover distortion behavior is characteristic of

(A) Class A output stage
(B) Class B output stage
(C) Class AB output stage
(D) Common-base output stage
A multistage amplifier has a low-pass response with three real poles

at s =- w1 - w2 and w3 . The approximate overall bandwidth B of the
amplifier will be given by
(B) 1 = 1 + 1 + 1
(A) B = w1 + w2 + w3
w1 w2 w3
B
(C) B = (w1 + w2 + w3) 1/3
1999
3.124
3.125
An amplifier has an open-loop gain of 100, an input impedance of

1 kW,and an output impedance of 100 W. A feedback network with
a feedback factor of 0.99 is connected to the amplifier in a voltage
series feedback mode. The new input and output impedances,
respectively, are
(A) 10 W and 1W
(B) 10 W and 10 kW
(C) 100 kW and 1 W
(D) 100 kW and 1 kW
A dc power supply has a no-load voltage of 30 V, and a full-load
voltage of 25 V at a full-load current of 1 A. Its output resistance
and load regulation, respectively, are
(A) 5 W and 20%
(B) 25 W and 20%
(C) 5 W and 16.7%
(D) 25 W and 16.7%
1998
3.126
TWO MARK
ONE MARK
The circuit of the figure is an example of feedback of the following
3.132
3.133
3.134
TWO MARKS
One input terminal of high gain

ground and a sinusoidal voltage
output of comparator will be
(A) a sinusoid
(C) a half rectified sinusoid
(D) B =
w12 + w22 + w23
comparator circuit is connected to

is applied to the other input. The
(B) a full rectified sinusoid
(D) a square wave
In a series regulated power supply circuit, the voltage gain Av of the

pass transistor satisfies the condition
(A) Av " 3
(B) 1 << Av < 3
(C) Av . 1
(D) Av << 1
For full wave rectification, a four diode bridge rectifier is claimed to
have the following advantages over a two diode circuit :
(A) less expensive transformer,
(B) smaller size transformer, and
(C) suitability for higher voltage application.
Of these,
(A) only (1) and (2) are true

Page 59
1997
(B) only (1) and (3) are true

(C) only (2) and (3) are true
(D) (1), (2) as well as (3) are true
3.135
3.140
In the circuit of in the figure is the current iD through the ideal

diode (zero cut in voltage and forward resistance) equals
In the MOSFET amplifier of the figure is the signal output V1 and

V2 obey the relationship
(A) 0 A
(C) 1 A
3.141
3.136
(A) V1 = V2
2
(B) V1 =-V2
2
(C) V1 = 2V2
(D) V1 =- 2V2
For small signal ac operation, a practical forward biased diode can

be modelled as
(A) a resistance and a capacitance in series
(B) an ideal diode and resistance in parallel
(C) a resistance and an ideal diode in series
(D) a resistance
1997
3.137
TWO MARKS
In the BJT amplifier shown in the figure is the transistor is based in

the forward active region. Putting a capacitor across RE will
The output voltage V0 of the circuit shown in the figure is
(A) - 4 V
(C) 5 V
A
I
D
ONE MARK
O
N
A half wave rectifier uses a diode

voltage is Vm sin wt and the load
is given by
(A) Vm
in 2 RL
.
o
c 2V
ia. (C) pm
d
o
3.142
.
ww
(B) 4 A
(D) None of the above
(B) 6 V
(D) - 5.5 V
with a forward resistance Rf . The
resistance is RL . The DC current
Vm
p (R f + RL)
(D) Vm
RL
(B)
1996
3.143
ONE MARK
In the circuit of the given figure, assume that the diodes are ideal
and the meter is an average indicating ammeter. The ammeter will
read
(A) decrease the voltage gain and decrease the input impedance
(B) increase the voltage gain and decrease the input impedance
(C) decrease the voltage gain and increase the input impedance
(D) increase the voltage gain and increase the input impedance
3.138
3.139
A cascade amplifier stags is equivalent to

(A) a common emitter stage followed by a common base stage
(B) a common base stage followed by an emitter follower
(C) an emitter follower stage followed by a common base stage
(D) a common base stage followed by a common emitter stage
In a common emitter BJT amplifier, the maximum usable supply
voltage is limited by
(A) Avalanche breakdown of Base-Emitter junction
(B) Collector-Base breakdown voltage with emitter open (BVCBO)
(C) Collector-Emitter breakdown voltage with base open (BVCBO)
(D) Zener breakdown voltage of the Emitter-Base junction
(A) 0.4 2 A
(C) 0.8 A
p
3.144
(B) 0.4 A
(D) 0.4 mamp
p
The circuit shown in the figure is that of
(A) a non-inverting amplifier

(C) an oscillator
(B) an inverting amplifier

(D) a Schmitt trigger

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1996
3.145
TWO MARKS
In the circuit shown in the given figure N is a finite gain amplifier

with a gain of k , a very large input impedance, and a very low
output impedance. The input impedance of the feedback amplifier
with the feedback impedance Z connected as shown will be
(A) Z b1 - 1 l
k
Z
(C)
(k - 1)
3.146
(B) Z (1 - k)
(D) Z
(1 - k)
A Darlington stage is shown in the figure. If the transconductance of

c
Q1 is gm1 and Q2 is gm2 , then the overall transconductance gmc ;T i cc E
vbe
is given by
(A) gm1
(C) gm2
3.147
Page 60
A
I
D
(B) 0.5 gm1

(D) 0.5 gm2
O
N
Value of R in the oscillator circuit shown in the given figure, so

chosen that it just oscillates at an angular frequency of w. The value
of w and the required value of R will respectively be
no
w.
.in
co
ia.
ww
(A) 105 rad/ sec, 2 # 10 4 W

(C) 2 # 10 4 rad/ sec, 105 W
3.148
(B) 2 # 10 4 rad/ sec, 2 # 10 4 W

(D) 105 rad/ sec, 105 W
A zener diode in the circuit shown in the figure is has a knee current
of 5 mA, and a maximum allowed power dissipation of 300 mW
. What are the minimum and maximum load currents that can
be drawn safely from the circuit, keeping the output voltage V0
constant at 6 V?
(A) 0 mA, 180 mA

(C) 10 mA, 55 mA
(B) 5 mA, 110 mA

(D) 60 mA, 180 mA
***********

Page 61
SOLUTIONS
3.1
Option (B) is correct.

For the given ideal op-amp, negative terminal will be also ground
(at zero voltage) and so, the collector terminal of the BJT will be
at zero voltage.
i.e.,
VC = 0 volt
The current in 1 kW resistor is given by
I = 5 - 0 = 5 mA
1 kW
This current will flow completely through the BJT since, no current will flow into the ideal op-amp ( I/P resistance of ideal opamp is infinity). So, for BJT we have
VC = 0
VB = 0
IC = 5 mA
i.e.,the base collector junction is reverse biased (zero voltage)
therefore, the collector current (IC ) can have a value only if baseemitter is forward biased. Hence,
VBE = 0.7 volts
&
VB - VE = 0.7
&
0 - Vout = 0.7
or,
Vout =- 0.7 volt
3.2
3.3
O
N
A
I
D
Option (A) is correct.

The i/p voltage of the system is given as
Vin = V1 + Vf
.n3.4o
w
= V1 + k Vout
ww
= V1 + k A 0 V1
^Vout = A 0 V1h
= V1 ^1 + k A 0h
Therefore, if k is increased then input voltage is also increased so,
the input impedance increases. Now, we have
Vout = A 0 V1
Vin
= A0
^1 + k A 0h
A
0 Vin
=
^1 + k A 0h
Since, Vin is independent of k when seen from output mode, the
output voltage decreases with increase in k that leads to the decrease
of output impedance. Thus, input impedance increases and output
impedance decreases.

For the given circuit, we obtain the small signal model as shown in
figure below :
We obtain the node voltage at V1 as

V1 +
V1
+ gm Vi = 0
RD R + 1
L
sC
&
From the circuit, we have

or,
(1)
Since, voltage across zener diode is 5 V so, current through 100 W
resistor is obtained as
Is = 10 - 5 = 0.05 A
100
Therefore, the load current is given by
IL = 5
RL
Since, for proper operation, we must
have
IZ $ Iknes
So, from Eq. (1), we write
0.05 A - 5 $ 10 mA
RL
50 mA - 5 $ 10 mA
RL
40 mA $ 5
RL
-3
40 # 10 $ 5
RL
1
# RL
5
40 # 10-3
5
# RL
40 # 10-3
or,
125 W # RL
Therefore, minimum value of RL = 125 W
Now, we know that power rating of Zener diode is given by
PR = VZ IZ^maxh
IZ^maxh is maximum current through zener diode in reverse bias.
Maximum currrent through zener diode flows when load current is
zero. i.e.,
IZ^maxh = Is = 10 - 5 = 0.05
100
n
i
PR = 5 # 0.05 W
o.
cTherefore,
.
a
= 250 mW
di
Is = I Z + I L
I Z = Is - I L
V1 =
- gm Vi
1 +
1
RD R + 1
L
sC
Therefore, the output voltage V0 is obtained as

V0 = V1 RL
RL + 1
sC
- gm Vi
RL J
=
K 1
1
1
RL +
+
sC KK RD R + 1
L
sC
L
so, the transfer function is
V0 = - RD RL sCgm
Vi
1 + sC ^RD + RL h
1
Then, we have the pole at w =
C ^RD + RL h
N
O
O
O
P
www.nodia.co.in
Z =XY
It gives the lower cutoff frequency of transfer function.

1
i.e.,
w0 =
C ^RD + RL h
1
or,
f0 =
2pC ^RD + RL h
1
=
2p # 10-6 # 20 # 103
= 7.97
. 8 Hz
3.5
Page 62
3.7
Option (D) is correct.

Given, the input voltage
VYZ = 100 sin wt
Option (C) is correct.
For + ve half cycle

VYZ > 0
i.e., VY is a higher voltage than VZ
So, the diode will be in cutoff region. Therefore, there will no voltage difference between X and W node.
i.e.,
VWX = 0
Now, for - ve half cycle all the four diodes will active and so, X
and W terminal is short circuited
i.e.,
VWX = 0
Hence,
VWX = 0 for all t
For the given ideal op-Amps we can assume

V 2- = V 2+ = V2 (ideal)
3.8
V 1+ = V 1- = V1 (ideal)
The equivalent circuit can be shown as
So, by voltage division
V1 = Vout # 1
2
Vout = 2V1
n
and, as the I/P current in Op-amp is always zero therefore, there
o.i
c
.
will be no voltage drop across 1 KW in II op-amp
ia
d
o
i.e.,
V2 = 1 V
.n
w
Therefore,
ww
V
2
^
h
V1 - V2 = 2
VTh = VCC R2
R1 + R 2
1
1
&
V1 - 1 = 1 + 2
= 3R2
R1 + R 2
or,
V1 = 4
and
RTh = R2 R1
Hence,
R 2 + R1
Vout = 2V1 = 8 volt
Since, IC = bIB has b . 3 (very high) so, IB is negative in
comparison to IC . Therefore, we can write the base voltage
For the given circuit, we can make the truth table as below
VB = VTh
X
Y
Z
So,
VTh - 0.7 - IC RE = 0
0
0
0
3R2 - 0.7 - 10-3 500 = 0
0
1
1
or,
^
h^ h
+ R2
R
1
1
0
0
3R2
1
1
0
or,
= 0.7 + 0.5
60 kW + R2
Logic 0 means voltage is v = 0 volt and logic 1 means voltage is
or,
3R2 = ^60 kWh^1.2h + 1.2R2
5 volt
A
I
D
O
N
3.6
For x = 0 , y = 0 , Transistor is at cut off mode and diode is forward

biased. Since, there is no drop across forward biased diode.
So,
Z =Y=0
For x = 0 , y = 1, Again Transistor is in cutoff mode, and diode is
forward biased. with no current flowing through resistor.
So,
Z =Y=1
For x = 1, y = 0 , Transistor is in saturation mode and so, z directly
connected to ground irrespective of any value of Y .
i.e.,
Z = 0 (ground)
Similarly for X = Y = 1
Z = 0 (ground)
Hence, from the obtained truth table, we get
or,
Hence,
3.9
1.8R2 = ^60 kWh # ^1.2h

R2 = 60 # 1.2 = 40 kW
1.8

Given
ib = 1 + 0.1 cos (1000pt) mA
So,
IB = DC component of ib
= 1 mA
In small signal model of the transistor
bVT
rp =
VT " Thermal voltage
IC

3.10
IC = I
= VT = VT
B
IB
b
IC /b
= VT
IB
So,
rp = 25 mV = 25 W
VT = 25 mV, IB = 1 mA
1 mA
Let v > 0.7 V and diode is forward biased. By applying Kirchoffs
voltage law
Page 63
3.13
Vtest + Vtest + 99Vtest = I

test
10 k 100
10 k
100Vtest + Vtest = I
test
10 # 103 100
2Vtest = I
test
100
ZTh = Vtest = 50 W
Itest
First we obtain the transfer function.
10 - i # 1k - v = 0
10 - :v - 0.7 D (1000) - v = 0
500
So,
3.11
10 - (v - 0.7) # 2 - v = 0
10 - 3v + 1.4 = 0
v = 11.4 = 3.8 V > 0.7
3
i = v - 0.7 = 3.8 - 0.7 = 6.2 mA
500
500
(Assumption is true)
0 - Vi (jw) 0 - Vo (jw)
=0
+
1 +R
R2
1
jw C
Vo (jw)
- Vi (jw)
=
1 +R
R2
1
jw C

The circuit composed of a clamper and a peak rectifier as shown.
Vi (jw) R2
R1 - j 1
wC
1 " 3, so V = 0
o
wC
Vo (jw) =-
IA
At w " 0 (Low frequencies),
D
O
Clamper clamps the voltage to zero voltage, as shown
1 " 0, so V (jw) =- R2 V (jw)

o
R1 i
wC
n
The
o.i filter passes high frequencies so it is a high pass filter.
c
.
H (jw) = Vo = - R2
dia
o
Vi
R1 - j 1
.n
wC
w
ww
R
R
2
H (3) =
= 2
R1
R1
At 3 dB frequency, gain will be
6H (3)@
The peak rectifier adds + 1 V to peak voltage, so overall peak voltage

lowers down by - 1 volt.
So,
vo = cos wt - 1
3.12
At w " 3 (higher frequencies)
2 times of maximum gain
H ^ jw0h = 1 H (3)
2
R2
= 1 b R2 l
1
2
2 R1
R1 + 2 2
w0 C
So,

We put a test source between terminal 1, 2 to obtain equivalent
impedance
2R 12 = R 12 +
1
w02 C 2
1
w 2C 2
w0 = 1
R1 C
R 12 =
3.14

DC Analysis :
ZTh = Vtest
Itest
Applying KCL at top right node
Vtest + Vtest - 99I = I
b
test
9 k + 1k 100
Vtest + Vtest - 99I = I
b
test
10 k 100
...(i)
But
Ib =- Vtest =-Vtest
9k + 1k
10k
Using KVL in input loop,

VC - 100IB - 0.7 = 0
Substituting Ib into equation (i), we have

www.nodia.co.in
...(i)
VC = 100IB + 0.7
IC - IE = 13.7 - VC = (b + 1) IB
12k
13.7 - VC = 100I
...(ii)
B
12 # 103
Solving equation (i) and (ii),
Page 64
Gain w = w = gm (ZC RL) = gm (2k 2k) = gm # 103 which is

maximum. Therefore gain is maximum at wr = 10 M rad/ sec .
r
3.16

The given circuit is shown below :
IB = 0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current
source.
From diagram we can write

Ii = Vo + Vo
R1 sL1
This is a shunt-shunt feedback amplifier.
Given parameters,
rp = VT = 25 mV = 2.5 kW
IB
0.01 mA
b
100
= 0.04 s
gm = =
rp 2.5 # 1000
Writing KCL at output node
v0 + g v + v0 - vp = 0
m p
RC
RF
v 0 : 1 + 1 D + v p :gm - 1 D = 0
RC RF
RF
Substituting RC = 12 kW, RF = 100 kW, gm = 0.04 s
v 0 (9.33 # 10-5) + v p (0.04) = 0
v 0 =- 428.72Vp
...(i)
Writing KCL at input node
vi = v p + v p + v p - vo
Rs
Rs rp
RF
vi = v 1 + 1 + 1 - v 0
p:
Rs
Rs rp RF D RF
vi = v (5.1 10-4) - v 0
#
p
Rs
RF
Substituting Vp from equation (i)
Transfer function
or
At w = 0
At w = 3

Given circuit is shown below.
.in
no
w.
ww
For transistor M2 ,
VGS = VG - VS = Vx - 0 = Vx
VDS = VD - VS = Vx - 0 = Vx
Since VGS - VT = Vx - 1 < VDS , thus M2 is in saturation.
By assuming M1 to be in saturation we have
IDS (M ) = IDS (M )
mn C 0x
m C
(4) (5 - Vx - 1) 2 = n 0x 1 (Vx - 1) 2
2
2
1
Rs = 10 kW
or
Taking positive root,
vi
=- 1.116 # 10-5
10 # 103
1
Av = v 0 =
- 8.96
vi
10 # 103 # 1.116 # 10-5
For the parallel RLC circuit resonance frequency is,
1
wr = 1 =
= 10 M rad/s
-6
LC
10 # 10 # 1 # 10-9
Thus given frequency is resonance frequency and parallel RLC
circuit has maximum impedance at resonance frequency
Gain of the amplifier is gm # (ZC RL) where ZC is impedance of
parallel RLC circuit.
At w = wr , ZC = R = 2 kW = ZC max .
Hence at this frequency (wr ), gain is
Hence HPF.
co
ia.
vi = - 5.1 # 10-4 v - v 0
0
428.72
Rs
RF
3.15
H (jw) = 0
H (jw) = R1 = constant .
A
I
D
3.17
O
N
vi
=- 1.16 # 10-6 v 0 - 1 # 10-5 v 0
10 # 103
(source resistance)
H (s) = Vo = sR1 L1
I1 R1 + sL1
jw R 1 L 1
H (jw) =
R 1 + jw L 1
At Vx = 3 V for M1,VGS
is true and Vx = 3 V .
3.18
4 (4 - Vx ) 2 = (Vx - 1) 2
2 (4 - Vx ) = ! (Vx - 1)
8 - 2Vx = Vx - 1
Vx = 3 V
= 5 - 3 = 2 V < VDS . Thus our assumption

We have
a = 0.98
Now
b = a = 4.9
1-a
In active region, for common emitter amplifier,
Substituting ICO
...(1)
IC = bIB + (1 + b) ICO
= 0.6 mA and IB = 20 mA in above eq we have,
IC = 1.01 mA

3.19
Page 65

In active region
VBEon = 0.7 V
Emitter voltage
VE = VB - VBEon =- 5.7 V
V - (- 10) - 5.7 - (- 10)
Emitter Current
IE = E
=
= 1 mA
4.3k
4.3k
Now
IC . IE = 1 mA
Applying KCL at collector
Since
or
i1 = 0.5 mA
i1 = C dVC
dt
VC = 1 # i1 dt = i1 t
C
C
Input impedance
R in = RB || [rp + (b + 1)] RE
Input impedance increases
gm RC
Voltage gain
Voltage gain decreases.
AV =
1 + gm R E
...(1)

Since, emitter area of transistor Q1 is half of transistor Q2 , so current
IE = 1 IE and IB = 1 IB
2
2
3.23
The circuit is as shown below :
with time, the capacitor charges and voltage across collector changes
from 0 towards negative.
When saturation starts,
VCE = 0.7 & VC =+ 5 V (across
capacitor)
Thus from (1) we get,
+ 5 = 0.5 mA T
5 mA
or
3.20
3.21
A
I
D
Collector current
O
N
-6
T = 5 # 5 # 10
= 50 m sec
-3
0.5 # 10
in
co.
a.
di
o
n
w.
The current flows in the circuit if all the diodes are forward biased.
w
In forward biased there will be 0.7 V drop across each diode. w
12.7 - 4 (0.7)
Thus
IDC =
= 1 mA
9900
The forward resistance of each diode is
r = VT = 25 mV = 25 W
IC
1 mA
4 (r)
Thus
Vac = Vi # e
4 (r) + 9900 o
VB =- 10 - (- 0.7) =- 9.3 V
I1 =
0 - (- 9.3)
= 1 mA
(9.3 kW)
b 1 = 700 (high), So IC . IE
Applying KCL at base we have
1 - IE = IB + IB
1 - (b 1 + 1) IB = IB + IB
1
1 = (700 + 1 + 1)
IB
+ IB
2
IB . 2
702
2
I 0 = IC = b 2 : IB = 715 # 2 . 2 mA
702
The circuit is as shown below :
2
3.24
= 100 mV cos (wt) 0.01
= 1 cos (wt) mV
3.22

The equivalent circuit of given amplifier circuit (when CE is
connected, RE is short-circuited)
So,
Input impedance
Ri = RB || r p
Voltage gain
AV = gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
or
3.25
0 - Vi + 0 - Vo = 0
R1
R2
Vo =- R2
Vi
R1

By small signal equivalent circuit analysis

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Page 66
voltage across resistor will be V = 1.V

Diode is off, it must be in reverse biased, therefore
Vi - 1 > 0 " Vi > 1
Thus for Vi > 1 diode is off and V = 1V
Option (B) and (C) doesnt satisfy this condition.
Let Vi < 1. In this case diode will be on and voltage across diode will
be zero and V = Vi
Thus
V = min (Vi, 1)
Input resistance seen by source vs

R in = vs = Rs + Rs || rs
is
3.29
= (1000 W) + (93 kW || 259 W) = 1258 W

3.26

Cut-off frequency due to C2
fo =
3.30
1
2p (RC + RL) C2
fo
1
= 271 Hz
2 # 3.14 # 1250 # 4.7 # 10-6
Lower cut-off frequency
f
fL . o = 271 = 27.1 Hz
10
10
3.31
3.27
3.32

The R2 decide only the frequency.
For small increase in VG beyond 1 V the n - channel MOSFET goes
into saturation as VGS "+ ive and p - MOSFET is always in active
region or triode region.
The circuit is shown in fig below

The circuit is as shown below
A
I
D
O
N
I = 20 - 0 + Vi - 0 = 5 + Vi
4R
R
R
If I > 0, diode D2 conducts
So, for 5 + VI > 0 & VI > - 5, D2 conducts
2
Equivalent circuit is shown below
Current
no
w.
The voltage at non inverting terminal is 5 V because OP AMP is

ideal and inverting terminal is at 5 V.
.in
IC = 10 - 5 = 1 mA
oThus
c
.
5k
a
i
ww
3.33
VE = IE RE = 1m # 1.4k = 1.4V
IE = IC
= 0.6 + 1.4 = 2V
Thus the feedback is negative and output voltage is V = 2V .
The output voltage is
V0 = Ar Vi .-
hfe RC
Vi
hie
Here RC = 3 W and hie = 3 kW

Thus
Output is Vo = 0 . If I < 0 , diode D2 will be off
5 + VI < 0 & V < - 5, D is off
I
2
R
The circuit is shown below
.- 150 (A cos 20t + B sin 106 t)

Since coupling capacitor is large so low frequency signal will be
filtered out, and best approximation is
V0 .- 150B sin 106 t
3.34
0 - Vi + 0 - 20 + 0 - Vo = 0
R
4R
R
3.28
or
Vo =- Vi - 5
At Vi =- 5 V,
At Vi =- 10 V,
Vo = 0
Vo = 5 V

Let diode be OFF. In this case 1 A current will flow in resistor and
V0 . - 150 # 3k Vi
3k
3.35

For the positive half of Vi , the diode D1 is forward bias, D2 is reverse
bias and the zener diode is in breakdown state because Vi > 6.8 .
Thus output voltage is
V0 = 0.7 + 6.8 = 7.5 V
For the negative half of Vi, D2 is forward bias thus
Then
V0 =- 0.7 V
By Current mirror,
^ L h2
Ibias
W
^ L h1
W
Ix =
Since MOSFETs are identical,

Thus
Hence
3.36
Page 67
W
W
b L l =b L l
2
2
KCL at non inverting terminal side we have

15 - V1 + V0 - V1 = V1 - (- 15)
10
10
10
or
V1 = V0
3
Ix = Ibias

The circuit is using ideal OPAMP. The non inverting terminal of
OPAMP is at ground, thus inverting terminal is also at virtual
ground.
If V0 swings from -15 to +15 V then V1 swings between -5 V to +5

V.
For the given DC values the Thevenin equivalent circuit is as follows
3.40
Thus current will flow from -ive terminal (0 Volt) to -1 Volt source.
Thus the current I is
0 - (- 1)
I =
= 1
100k
100k
The Thevenin resistance and voltage are

VTH = 10 # 9 = 3 V
10 + 20
and total
RTH = 10k # 20k = 6.67 kW
10k + 20k
The current through diode is

I = I 0 _eV - 1i
Now VT = 25 mV and I0 = 1 mA
V
Thus
or
Now
V
3.37
V
I = 10-6 8e 25 # 10 - 1B = 1 5
10
V = 0.06 V
V0 = I # 4k + V = 1 # 4k + 0.06 = 0.1
100k
Since b is very large, therefore IB is small and can be ignored

Thus
IE = VTH - VBE = 3 - 0.7 = 1 mA
RE
2.3k
-3

The circuit is using ideal OPAMP. The non inverting terminal of
OPAMP is at ground, thus inverting terminal is also at virtual
ground.
O
N
A
I
D

The small signal model is shown in fig below
3.41
.in
no
w.
co
ia.
ww
gm =
IC
= 1m = 1 A/V
VT
25m
25
Vo =- gm Vp # (3k 3k )
=- 1 Vin (1.5k)
25
or
Thus we can write

vi
=
R1 + sL
or
-v
3.42
R2
sR2 C2 + 1
IC . IE
Vp = Vin
=- 60Vin
Am = Vo =- 60
Vin

The circuit shown in (C) is correct full wave rectifier circuit.
v0 =R2
vi
(R1 + sL)( sR2 C2 + 1)
and from this equation it may be easily seen that this is the standard form of T.F. of low pass filter
K
H (s) =
(R1 + sL)( sR2 C2 + 1)
and form this equation it may be easily seen that this is the standard form of T.F. of low pass filter
H (s) = 2 K
as + bs + b
3.38
3.39
Option ( ) is correct.
The current in both transistor are equal. Thus gm is decide by M1.
Hence (C) is correct option.
3.43
3.44

In the transconductance amplifier it is desirable to have large input
resistance and large output resistance.
We redraw the circuit as shown in fig.

Let the voltage at non inverting terminal be V1, then after applying

www.nodia.co.in
Page 68
We have VZ = 7 volt, VK = 0, RZ = 10W

Circuit can be modeled as shown in fig below
Since Vi is lies between 10 to 16 V, the range of voltage across 200

kW
V200 = Vi - VZ = 3 to 9 volt
The range of current through 200 kW is
3 = 15 mA to 9 = 45 mA
200k
200k
Applying voltage division rule

v+ = 0.5 V
v+ = vv- = 0.5 V
i = 1 - 0.5 = 0.5 mA
1k
i = 0.5 - v0 = 0.5 mA
2k
We know that
Thus
Now
and
v0 = 0.5 - 1 =- 0.5 V
or
3.45
The range of variation in output voltage

15m # RZ = 0.15 V to 45m # RZ = 0.45
Thus the range of output voltage is 7.15 Volt to 7.45 Volt

If we assume b very large, then IB = 0 and IE = IC ; VBE = 0.7 V. We
assume that BJT is in active, so applying KVL in Base-emitter loop
IE = 2 - VBE = 2 - 0.7 = 1.3 mA
1k
RE
Since b is very large, we have IE = IC , thus
IC = 1.3 mA
Now applying KVL in collector-emitter loop
10 - 10IC - VCE - IC = 0
or
VCE =- 4.3 V
Now
VBC = VBE - VCE
= 0.7 - (- 4.3) = 5 V
Since VBC > 0.7 V, thus transistor in saturation.
3.46
V+ =
or
or
O
N
di
or
3.47
3.51
3.48
3.52
3.53
Vo1 - Vo2 = VT 1n 4 - VT 1n 2
Is R
Is R
Vo1 - Vo2 = VT 1n 4 = VT 1n2
2
V0 = H (s) = 1 - sRC
Vi
1 + sRC
1 - jwRC
H (jw) =
1 + jwRC
fmin
fmax
=- 2 tan - 2 wRC
= - p (at w " 3)
= 0( at w = 0)

In the transconductance amplifier it is desirable to have large input
impedance and large output impedance.
The voltage at inverting terminal is
V- = V+ = 10 V
Here note that current through the capacitor is constant and that
is
I = V- = 10 = 10 mA
1k 1k

We have
Vthp = Vthp = 1 V
WP
W
and
= N = 40mA/V2
LP
LN
From figure it may be easily seen that Vas for each NMOS and
PMOS is 2.5 V
mA
Thus
ID = K (Vas - VT ) 2 = 40 2 (2.5 - 1) 2 = 90 m A
V
1
V
1 + sCR i
Minimum value,
Maximum value,
For the first condition
Subtracting above equation
1
V
1 + sCR i
+H (jw) = f =- tan - 1 wRC - tan - 1 wRC
For the first condition
VD = 0 - Vo1 = VT 1n 4
Is R
Vi =
Applying voltage division rule

(V + Vi)
V+ = R1 (V0 + Vi) = o
R1 + R1
2
(Vo + Vi)
1
or
V =
1 + sCR i
2
Vo =- 1 +
2
or
Vi
1 + sRC
V0 = 1 - sRC
n
o.i
c
Vi
1 + sRC
.
a
VD = 0 - Vo1 = VT 1n 2
Is R
R+
1
sC
A
I
D
Vi = I eV /V
s
R
VD = VT 1n Vi
Is R
D
1
sC
V- = V+ =
Now

.no3.50
w
Here the inverting terminal is at virtual ground and the current
ww in
resistor and diode current is equal i.e.
IR = ID

The voltage at non-inverting terminal is
3.49
Thus the voltage across capacitor at t = 1 msec is

1m
1m
VC = 1 Idt = 1 10mdt
C 0
1m 0
Im
= 10 4 dt = 10 V
#0
3.54

In forward bias Zener diode works as normal diode.

Page 69
Thus for negative cycle of input Zener diode is forward biased and
it conducts giving VR = Vin .
For positive cycle of input Zener diode is reversed biased
when 0 < Vin < 6 , Diode is OFF and VR = 0
when Vin > 6 Diode conducts and voltage across diode is 6 V. Thus
voltage across is resistor is
VR = Vin - 6
Only option (B) satisfy this condition.
and IC remain same. There will be change in VCE

Thus,
VCE - 18 - 9 = 9 V
IC = 0.9 A
Power dissipation
P = VCE IC = 9 # 0.9 = 8.1 W
Thus % increase in power is
8.1 - 5.4 # 100 = 50%
5.4
3.55

Since the inverting terminal is at virtual ground, the current flowing
through the voltage source is
Is = Vs
10k
Vs = 10 kW = R
or
in
Is
3.60

The circuit under DC condition is shown in fig below

The effect of current shunt feedback in an amplifier is to decrease
the input resistance and increase the output resistance as :
Rif = Ri
1 + Ab
3.61
Applying KVL we have
3.56
VCC - RC (IC + IB) - VCE = 0

and
VCC - RB IB - VBE = 0
Substituting IC = bIB in (1) we have
...(1)
...(2)
VCC - RC (bIB + IB) - VCE = 0

Solving (2) and (3) we get
VCE = VCC - VCC - VBE
RB
1+
RC (1 + b)
Now substituting values we get
12 - 0.7
VCE = 12 = 5.95 V
53
1+
1 + (1 + 60)
...(3)
ww
b' = 110 # 60 = 66
100
We have
where
3.62
O
N
3.57
3.58
.c
ia
od
3.63
n
w.
= 5.29 - 59.5 # 100 =- 4.3%

5.95

The CE configuration has high voltage gain as well as high
current gain. It performs basic function of amplifications. The CB
configuration has lowest Ri and highest Ro . It is used as last step to
match a very low impedance source and to drain a high impedance
load
n
Thus
o.i cascade amplifier is a multistage configuration of CE-CB
A
I
D
...(4)

Common mode gain
ACM =- RC
2RE
And differential mode gain
Substituting b' = 66 with other values in (iv) in previous solutions

12 - 0.7
VCE = 12 = 5.29 V
53
1+
1 + (1 + 66)
Thus change is
Rof = R0 (1 + Ab)
Ri " Input resistance without feedback
Rif " Input resistance with feedback.
ADM =- gm RC
Thus only common mode gain depends on RE and for large value
of RE it decreases.
3.64
IE = Is `e nV - 1j
VBE
= 10

The Zener diode is in breakdown region, thus
V+ = VZ = 6 V = Vin
R
We know that
Vo = Vin c1 + f m
R1
or
Vout = Vo = 6`1 + 12k j = 9 V
24k
3.65
- 13
0.7
c e1 # 26 # 10 - 1m = 49 mA
-3

The current in 12 kW branch is negligible as comparison to 10 W.

Thus Current
IC . IE . = Vout = 9 = 0.9 A
RL
10
Now
VCE = 15 - 9 = 6 V
The power dissipated in transistor is
P = VCE IC = 6 # 0.9 = 5.4 W
3.59

If the unregulated voltage increase by 20%, them the unregulated
voltage is 18 V, but the VZ = Vin = 6 remain same and hence Vout
Writing equation for I- have

e 0 - V- = I
1M
or
e0 = I- (1M) + VWriting equation for I+ we have
...(1)

www.nodia.co.in
Page 70
0 - V+
= I+
1M
From the figure we have
or
V+ = - I+ (1M)
Since for ideal OPAMP V+ = V- , from (1) and (2) we have
Zin = 2 MW
...(2)
e0 = I- (1M) - I + (1M)
= (I- - I+) (1M) = IOS (1M)
Thus if e0 has been measured, we can calculate input offset current
IOS only.
3.66
3.67
Z0 = rd RD = 20k 2k = 20 kW
11
and

The circuit in DC condition is shown below
3.71

At low frequency capacitor is open circuit and voltage acr s noninverting terminal is zero. At high frequency capacitor act as short
circuit and all input voltage appear at non-inverting terminal. Thus,
this is high pass circuit.
The frequency is given by
1
= 1000
w = 1 =
3
RC
1 # 10 # 1 # 10 - 6
rad/sec
Since the FET has high input resistance, gate current can be neglect
and we get VGS =- 2 V
Since VP < VGS < 0 , FET is operating in active region
2
(- 2) 2
Now
ID = IDSS c1 - VGS m = 10 c1 (- 8) m
VP
= 5.625 mA

The circuit under DC condition is shown in fig below
Now
VDS = VDD - ID RD = 20 - 5.625 m # 2 k
= 8.75 V
The transconductance is
A
I
D
3.72
O
N
Applying KVL we have
VCC - RB IB - VBE - RE IE = 0
or
VCC - RB IB - VBE - RE (b + 1) IB = 0
Since IE = IB + bIB
or
IB = VCC - VBE
RB + (b + 1) RE
20 - 0.7
=
= 40m A
430k + (50 + 1)1 k
Vmax = 30 V i.e.
Vmax - VZ = I + I
L
Z
1k
30 - 5.8 = I = 0.5 m
L
1k
or
3.69
3.70

The maximum load current will be at maximum input voltage i.e.
or
.
ww
n
o.i
.c The gain is
ia
od
3.73
IC = bIB = 50 # 40m = 2 mA
VC = VCC - RC IC = 20 - 2m # 2k = 16 V
Now
3.68
or,
So,
VP
2
ID IDSS
= 2 5.625mA # 10mA = 1.875 mS

8
A =- gm (rd RD)
= 1.875ms # 20 K =- 3.41
11

Only one diode will be in ON conditions
When lower diode is in ON condition, then
Vu = 2k Vsat = 2 10 = 8 V
2.5k
2.5
when upper diode is in ON condition
Vu = 2k Vsat = 2 (- 10) =- 5 V
2.5k
4
3.74
3.75
IL = 24.2 - 0.5 = 23.7 mA

An ideal OPAMP is an ideal voltage controlled voltage source.
In voltage series feed back amplifier, input impedance increases
by factor (1 + Ab) and output impedance decreases by the factor
(1 + Ab).
Rif = Ri (1 + Ab)
Ro
Rof =
(1 + Ab)

The small signal model is as shown below
gm =
3.76
3.77

This is a Low pass filter, because
V0 = 0
At w = 3
Vin
V0 = 1
and at w = 0
Vin
When IC >> ICO

Page 71
IC
= 1mA = 0.04 = 40 mA/V
VT
25mV
b
rp =
= 100 - 3 = 2.5 kW
gm
40 # 10
gm =
3.78
3.79

The given circuit is wein bridge oscillator. The frequency of oscillation
is
2pf = 1
RC
1
or
= 1 m
C = 1 =
3
3
2pRf
2p
2p # 10 # 10
VT =
Since b is large is large, IC . IE , IB . 0 and

IE = VT - VBE = 1 - 0.7 = 3 mA
RE
300


For the different combinations the table is as follows
3.83
We know that for ideal OPAMP

V- = V+
Applying KCL at inverting terminal
V- - Vs + V- - V0 = 0
R1
R1
or
2V+ - Vo + IL R2 = 0
Since V- = V+ , from (1) and (2) we have
Vs + IL R2 = 0
3.80
...(1)
O
N
ww
CE
CC
CB
Ai
High
High
Unity
Av
High
Unity
High
Ri
Medium
High
Low
Ro
Medium
Low
High
A
I
D
Option
in (B) is correct.
.
o
.cIf the input is sinusoidal signal of 8 V (peak to peak) then
3.85
ia
d
.no
...(2)w
CE

This circuit having two diode and capacitor pair in parallel, works
as voltage doubler.
3.84
IL =- Vs
R2
or
VCE = 5 - 2.2kIC - 300IE

= 5 - 2.2k # 1m - 300 # 1m
= 2.5 V
Now
or
2V- - Vo = Vs
Applying KCL at non-inverting terminal
V+
V - Vo
=0
+ IL + +
R2
R2
R1 V = 1
#5 = 1 V
R1 + R2 C
4+1
Vi = 4 sin wt
The output of comparator will be high when input is higher than
Vref = 2 V and will be low when input is lower than Vref = 2 V.
Thus the waveform for input is shown below

If IZ is negligible the load current is
12 - Vz = I
L
R
as per given condition
100 mA # 12 - VZ # 500 mA
R
At IL = 100 mA 12 - 5 = 100 mA
R
VZ = 5 V
R = 70W
or
At IL = 500 mA 12 - 5 = 500 mA
R
From fig, first crossover is at wt1 and second crossover is at wt2

where
VZ = 5 V
4 sin wt1 = 2V
or
R = 14 W
Thus taking minimum we get
Thus
R = 14 W
3.81
3.82

The Thevenin equivalent is shown below
3.86
wt1 = sin - 1 1 = p
2
6
wt2 = p - p = 5p
6
6
5p
p
-6
Duty Cycle = 6
=1
2p
3
Thus the output of comparators has a duty cycle of 1 .

3
CMMR = Ad
Ac

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Page 72
V+ = V- = 8 V
3
20 log CMMR = 20 log Ad - 20 log Ac

= 48 - 2 = 46 dB
Where Ad "Differential Voltage Gain
and AC " Common Mode Voltage Gain
or
3.87
Now applying KCL at inverting terminal we get

V- - 2 + V- - Vo = 0
1
5

The gain of amplifier is
Ai =
- gm
gb + jwC
3.93
Thus the gain of a transistor amplifier falls at high frequencies

due to the internal capacitance that are diffusion capacitance and
transition capacitance.
3.88
3.89

The equivalent circuit of 3 cascade stage is as shown in fig.

We have Ri = 1kW, b = 0.2, A = 50
Ri
Thus,
Rif =
= 1 kW
(1 + Ab)
11
The DC equivalent circuit is shown as below. This is fixed bias
circuit operating in active region.
or
or
A
I
D
or
In first case
20 log AV = 20 log 8000 = 98 dB

If we see th figure we find that the voltage at non-inverting terminal
is 3 V by the zener diode and voltage at inverting terminal will be 3
V. Thus Vo can be get by applying voltage division rule, i.e.
20 V = 3
20 + 40 o
or
3.92
V3 = 40 # 40V1
Vo = 50V3 = 50 # 40 # 40V1
AV = Vo = 50 # 40 # 40 = 8000
V1
3.94
VCC - IC1 R2 - VCE1 = 0
If a constant current is made to flow in a capacitor, the output
or
6 - 1.5mR2 - 3 = 0
voltage is integration of input current and that is sawtooth waveform
n
or
R2 = 2kW
oas.i below :
c
.
t
ia
IB1 = IC1 = 1.5m = 0.01 mA
d
VC = 1 idt
o
b1
150
n
C 0
.
In second case IB2 will we equal to IB1 as there is no in R1. www
The time period of wave form is
Thus
IC2 = b2 IB2 = 200 # 0.01 = 2 mA
T = 1 = 1 = 2 m sec
f
500
VCE2 = VCC - IC2 R2 = 6 - 2m # 2 kW = 2 V
20 # 10
1
Thus
3=
idt
2 # 106 0
The given circuit is a R - C phase shift oscillator and frequency of
or
i (2 # 10 - 3 - 0) = 6 # 10 - 6
its oscillation is
or
i = 3 mA
1
f =
Thus the charging require 3 mA current source for 2 msec.
2p 6 RC
O
N
3.91
1k
50V1 = 40V1
1k + 0.25k
1k
50V2 = 40V2
V3 =
1k + 0.25k
V2 =
Similarly
3.90
Vo = 6V- - 10
= 6 # 8 - 10 = 6 V
3
or
V0 = 9 V
3.95
-3

In voltage-amplifier or voltage-series amplifier, the Ri increase and
Ro decrease because
Rif = Ri (1 + Ab)
Ro
Rof =
(1 + Ab)
3.96


Let x be the gain and it is 20 db, therefore
20 log x = 20
or
x = 10
Since Gain band width product is 106 Hz, thus
So, bandwidth is
6
6
BW = 10 = 10 = 105 Hz = 100 kHz
10
Gain
3.97
V+ =
8 (3) = 8 kW
1+8
3

In multistage amplifier bandwidth decrease and overall gain increase.
From bandwidth point of view only options (A) may be correct
because lower cutoff frequency must be increases and higher must

be decreases. From following calculation we have

We have fL = 20 Hz and fH = 1 kHz
For n stage amplifier the lower cutoff frequency is
fL
20
f =
=
Ln
1
2n
Hz
-1
1
23
-1
Page 73
3.101
3.98
and
Thus
Now
2 2 - 1 = 0.5 kHz

As per Barkhousen criterion for sustained oscillations Ab $ 1 and
phase shift must be or 2pn .
V (f)
Now from circuit
A= O
= 1 + R2
Vf (f)
R1
V (f)
b (f) = 1 +0 = f
6
VO (f)
3.99
3.102
3.103
Slew Rate
or
dVO
= AV Vm w = AV Vm 2pf
c dt m
max
Vm = SR
AV V2pf
1
= -6
10 # 100 # 2p # 20 # 103
or
VM = 79.5 mV
3.100

The circuit is shown as below
I
For satisfactory operations
Vin - V0
R
When Vin = 30 V,
30 - 10
R
20
or
R
or
when Vin = 50 V
3.104
Ri " 3
R0 " 0
A"3

Both statements are correct because
(1) A stable multivibrator can be used for generating square wave,
because of its characteristic
(2) Bi-stable multivibrator can store binary information, and this
multivibrator also give help in all digital kind of storing.
A
I
D

If fT is the frequency at which the short circuit common emitter gain
n
attains
o.i unity magnitude then
c
.
gm
38 # 10 - 3
dia
=
fT =
o
2p (Cm + Cp)
2p # (10 - 14 + 4 # 10 - 13)
.n
w
or
= 1.47 # 1010 Hz
ww
If fB is bandwidth then we have
10
f
fB = T = 1.47 # 10 = 1.64 # 108 Hz
b
90
3.105
O
N
3.106

If we neglect current through RB then it can be open circuit as
shown in fig.
= IZ + IL
> IZ + IL
$ (10 + 1) mA
[IZ + IL = I]
Maximum power will dissipate in Zener diode when current through

it is maximum and it will occur at Vin = 30 V
I = Vin - Vo = 30 - 10 = 1 A
20
20
$ 11 mA
R # 1818 W
or
50 - 10 $ (10 + 1) mA
R
40 $ 11 # 10 - 3
R
or
Thus R # 1818W

The ideal op-amp has following characteristic :
and

Let the gain of OPAMP be AV then we have
20 log AV = 40 dB
or
AV = 100
Let input be Vi = Vm sin wt then we have
Now

The current gain of a BJT is
hfe = gm rp
R2 = 5R1
VO = VV Vi = Vm sin wt
dVO = A V w cos wt
V m
dt
=- 2ms # 3k =- 6
So,
Thus from above equation for sustained oscillation

6 = 1 + R2
R1
or
= 10 mA and VP =- 5 V
=0
= ID RS = 1 # 2.5W = 2.5 V
= VG - VS = 0 - 2.5 =- 2.5 V
gm = 2IDSS 81 - ` - 2.5 jB = 2 mS
VP
-5
AV = V0 =- gm RD
Vi
IDSS
VG
VS
VGS
Now
= 39.2 . 40
The higher cutoff frequency is

fHn = fH

We have
I IC + IZ = bIB + IZ
= bIZ + IZ = (b + 1) IZ
IZ = I = 1 = 0.01 A
b+1
99 + 1
Since IC = bIB
since IB = IZ
Power dissipated in zener diode is

PZ = VZ IZ = 9.5 # 0.01 = 95 mW
IC = bIZ = 99 # 0.1 = 0.99 A
VCE = Vo = 10 V
R # 3636W

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Power dissipated in transistor is
Page 74
3.110
PT = VC IC = 10 # 0.99 = 9.9 W
3.107
3.108

From the it may be easily seen that the tank circuit is having
2-capacitors and one-inductor, so it is colpits oscillator and frequency
is
1
f =
2p LCeq
Ceq = C1 C2 = 2 # 2 = 1 pF
4
C1 + C2
1
f =
2p 10 # 10 - 6 # 10 - 12
9
= 1 # 10 = 50.3 MHz
2p 10

Common mode gain is
AC = aRC
REE
Since source resistance of the current source is infinite REE = 3 ,
common mode gain AC = 0
3.111
3.112

3.113

In positive feed back it is working as OP-AMP in saturation region,
and the input applied voltage is +ve.
So,
V0 =+ Vsat = 15 V
With the addition of RE the DC abis currents and voltages remain
closer to the point where they were set by the circuit when the
outside condition such as temperature and transistor parameter b
change.
At high frequency
gm
+ jw (C)
1
Ai \
Capacitance
1
Ai a
frequency
Ai =or,
Let V- be the voltage of inverting terminal, since non inverting

terminal a at ground, the output voltage is
...(1)
Vo = AOL VNow applying KCL at inverting terminal we have
V- - Vs + V- - V0 = 0
...(2)
R1
R2
and
'
gbc
Thus due to the transistor capacitance current gain of a bipolar

transistor drops.
A
I
D

As OP-AMP is ideal, the inverting terminal at virtual ground due
to ground at non-inverting terminal. Applying KCL at inverting
.in
oterminal
c
.
dia sC (v1 sin wt - 0) + sC (V2 sin wt - 0) + sC (Vo - 0) = 0
o
n
or
Vo =- (V1 + V2) sin wt
w.
O
N
3.109
From (1) and (2) we have

VO = A =
- R2
CL
Vs
R - R2 + R1
ROL
Substituting the values we have
ww
- 10k
=- 1000 . - 11
ACL =
10
k
1
k
89
+
1k 100k
The first OPAMP stage is the differentiator and second OPAMP
stage is integrator. Thus if input is cosine term, output will be also
cosine term. Only option (A) is cosine term. Other are sine term.
However we can calculate as follows. The circuit is shown in fig
3.114
3.115
3.116
3.117
3.118

There is R - C , series connection in parallel with parallel R - C
combination. So, it is a wein bridge oscillator because two resistors
R1 and R2 is also in parallel with them.
The given circuit is a differentiator, so the output of triangular wave
will be square wave.
In sampling and hold circuit the unity gain non-inverting amplifier
is used.
The Thevenin equivalent is shown below
Applying KCL at inverting terminal of first OP AMP we have

V1 = - wjL = - 100 # 10 # 10 - 3 = - 1
R
10
10
VS
- jVS
or
V1 =
= j cos 100t
10
Applying KCL at inverting terminal of second OP AMP we have
VO = - 1/jwC
V1
100
1
== j10
j100 # 10 # 10 - 6 # 100
or
V0 = j10V2 = j10 (- j cos 100t)
V0 = 10 cos 100t
R1 V = 5
# 15 = 5 V
10 + 5
R1 + R2 C
Since b is large is large, IC . IE , IB . 0 and
IE = VT - VBE
RE
4. 3
= 5 - 0.7 =
= 10 mA
0.430kW
0.430KW
VT =

3.119
3.120
3.121
3.122
Page 75
Output resistance = 25 = 25 W
1

The output voltage will be input offset voltage multiplied by open
by open loop gain. Thus
So
V0 = 5mV # 10, 000 = 50 V
But
V0 = ! 15 V in saturation condition
So, it can never be exceeds ! 15 V
So,
V0 = ! Vset = ! 15V

This is a voltage shunt feedback as the feedback samples a portion
of output voltage and convert it to current (shunt).
3.126

In a differential amplifier CMRR is given by
(1 + b) IQ R 0
CMRR = 1 ;1 +
E
2
VT b
So where R 0 is the emitter resistance. So CMRR can be improved
by increasing emitter resistance.
3.127

Negative feedback in amplifier reduces the gain of the system.
By drawing small signal equivalent circuit

We know that rise time (tr ) is
3.128
tr = 0.35
fH
where fH is upper 3 dB frequency. Thus we can obtain upper 3 dB
frequency it rise time is known.
In a BJT differential amplifier for a linear response Vid < VT .
3.129

In a shunt negative feedback amplifier.
Input impedance
Ri
R in =
(1 + bA)
3.130
by applying KCL at E2
gm1 Vp 1
Vp
= gm2 Vp
rp
A
I
D
where
i 0 =- gm2 Vp
at C2
from eq (1) and (2)
i 0 =- i
0
gm2 rp
gm1 Vp +
1
gm1 Vp =- i 0 :1 + 1 D
gm2 rp
1
O
N
.no
gm2 rp = b >> 1
ww
w
so
gm1 Vp =- i 0
i 0 =- g
m1
Vp
i0 = g
a Vp = Vi
m1
Vi
Crossover behavior is characteristic of calss B output stage. Here 2
transistor are operated one for amplifying +ve going portion and
other for -ve going portion.
2
3.123
3.124

In Voltage series feedback mode input impedance is given by
R in = Ri (1 + bv Av)
where
bv = feedback factor ,
Av = openloop gain
and
Ri = Input impedance
So,
R in = 1 # 103 (1 + 0.99 # 100) = 100 kW
Similarly output impedance is given by
R0
ROUT =
R 0 = output impedance
(1 + bv Av)
100
Thus
ROUT =
= 1W
(1 + 0.99 # 100)
3.125
So, n
i Rin < Ri
.
o
a.cSimilarly
di
3.131
R0
(1 + bA)
3.132
3.133
3.134
3.135

Comparator will give an output either equal to + Vsupply or - Vsupply .
So output is a square wave.
In series voltage regulator the pass transistor is in common collector configuration having voltage gain close to unity.
In bridge rectifier we do not need central tap transformer, so its less
expensive and smaller in size and its PIV (Peak inverse voltage)
is also greater than the two diode circuit, so it is also suitable for
higher voltage application.
In the circuit we have
V2 = IS # RD
2
and

Regulation = Vno - load - Vfuel - load
Vfull - load
= 30 - 25 # 100 = 20%
25
ROUT =
ROUT < R 0
Thus input & output impedances decreases.
Ri = input impedance of basic amplifier

b = feedback factor
A = open loop gain
V1 = IS # RD
V2 = 1
2
V1
V1 = 2V2
3.136
3.137

www.nodia.co.in
Page 76
The equivalent circuit of given amplifier circuit (when CE is

connected, RE is short-circuited)
Ib = 0 - 3 + 10 - 3
4
4
10
6
Ib =
= 1 amp
4
so current
3.141

By applying node equation at terminal (2) and (3) of OP -amp
Input impedance
Ri = RB || r p
Voltage gain
AV = gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
Va - Q Va - V0
=0
+
5
10
2Va - 4 + Va - V0 = 0
V0 = 3Va - 4
Va - V0 + Va - 0 = 0
100
10
Input impedance
R in = RB || [rp + (b + 1)] RE
Input impedance increases
gm RC
Voltage gain
Voltage gain decreases.
AV =
1 + gm R E
3.138
3.139

In common emitter stage input impedance is high, so in cascaded
amplifier common emitter stage is followed by common base stage.
A
I
D
So

We know that collect-emitter break down voltage is less than
compare to collector base breakdown voltage.
O
N
Va - V0 + 10Va = 0
11Va = V0
Va = V0
11
V0 = 3V0 - 4
11
8V0 =- 4
11
V0 =- 5.5 Volts
n
BVCEO < BVCBO
o.i
c
.
both avalanche and zener break down. Voltage are higher than 3.142
dia Option (B) is correct.
o
n
Circuit with diode forward resistance looks
BVCEO .So BVCEO limits the power supply.
w.
3.140
ww
So the DC current will

If we assume consider the diode in reverse bias then Vn should be
greater than VP .
VP < Vn
by calculating
IDC =
3.143
VP = 10 # 4 = 5 Volt
4+4
Vm
p (R f + RL)

For the positive half cycle of input diode D1 will conduct & D2 will
be off. In negative half cycle of input D1 will be off & D2 conduct so
output voltage wave from across resistor (10 kW) is
Vn = 2 # 1 = 2 Volt
here VP > Vn (so diode cannot be in reverse bias mode).
apply node equation at node a

Va - 10 + Va + Va = 2
1
4
4
6Va - 10 = 8
Va = 3 Volt
Ammeter will read rms value of current

so
I rms = Vm (half wave rectifier)
pR
4
= 0.4 mA
=
p
(10 kW) p
3.144

In given circuit positive feedback is applied in the op-amp., so it
works as a Schmitt trigger.

3.145
Page 77

Gain with out feedback factor is given by
V0 = kVi
after connecting feedback impedance Z
given input impedance is very large, so after connecting Z we have

Ii = Vi - V0
V0 = kVi
Z
Ii = Vi - kVi
Z
input impedance
Zin = Vi = Z
Ii
(1 - k)
3.146
3.147

For the circuit, In balanced condition It will oscillated at a frequency
w
1 =
1
= 105 rad/ sec
-3
-6
LC
10 # 10 # .01 # 10
In this condition
R1 = R 3
R2
R4
5 =R
100
1
=
R = 20 kW = 2 # 10 W
3.148

V0 kept constant at
so current in 50 W resistor
V0 = 6 volt
I = 9-6
50 W
A
I
D
O
N
no
w.
.in
co
ia.
ww
I = 60 m amp
Maximum allowed power dissipation in zener
PZ = 300 mW
Maximum current allowed in zener
PZ = VZ (IZ ) max = 300 # 10-3
&
= 6 (IZ ) max = 300 # 10-3
&
= (IZ ) max = 50 m amp
Given knee current or minimum current in zener
In given circuit
(IZ ) min
I
IL
(IL) min
(IL) max
= 5 m amp
= IZ + I L
= I - IZ
= I - (IZ ) max
= (60 - 50) m amp = 10 m amp
= I - (IZ ) min
= (60 - 5) = 55 m amp

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

(A) 125 and 125

The ac schematic of an NMOS common-source state is shown in the

In the circuit shown below what is the output voltage ^Vouth if a

(B) 125 and 250

In a voltage-voltage feedback as shown below, which one of the

(A) The input

impedance increases and output impedance decreas-

impedance increases and output impedance also

impedance decreases and output impedance also

In the circuit shown below, Q1 has negligible collector-to-emitter

A voltage 1000 sin wt Volts is applied across YZ . Assuming ideal

GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia

(A) cos (wt) - 1

(B) _sin wt + sin wt i /2

(B) sin (wt)

The impedance looking into nodes 1 and 2 in the given circuit is

In the circuit shown below, the silicon npn transistor Q has a

The current ib through the base of a silicon npn transistor is

The voltage gain Av of the circuit shown below is

The i -v characteristics of the diode in the circuit given below are

The current in the circuit is

The circuit shown is a

GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes)

Statement for Linked Answer Questions: 4.6 & 4.7

In the circuit shown below, assume that the voltage drop

The circuit below implements a filter between the input current ii

(A) low pass filter

(B) band pass filter

The ac output voltage vac is

(B) 1 cos (wt) mV

The bias current IDC through the diodes is

For the BJT,

GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia

The value of current Io is approximately

Assuming the OP-AMP to be ideal, the voltage gain of the amplifier

Common Data For Q. 4.11 & 4.12 :

In the circuit below, the diode is ideal. The voltage V is given by

(B) max (Vi, 1)

In the following a stable multivibrator circuit, which properties of

The resistance seen by the source vS is

(A) Only the frequency

Statement for Linked Answer Question 4.16 and 4.17

GATE Electronics & Communication by RK Kanodia (Now in 3 Volumes)

In the following limiter circuit, an input voltage Vi = 10 sin 100pt

(A) 6.1 V, - 0.7 V

Estimate the output voltage V0 for VG = 1.5 V. [Hints : Use the

(B) 0.7 V, - 7.5 V

For the circuit shown in the following figure, transistor M1 and M2

The current Ix is related to Ibias as

(A) Positive feedback, V = 10 V

A small signal source Vi (t) = A cos 20t + B sin 106 t is applied to a

The OPAMP circuit shown above represents a

(A) V0 (t) =- 1500 (A cos 20t + B sin 106 t)

(A) high pass filter

(B) low pass filter

GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia

Two identical NMOS transistors M1 and M2 are connected as shown

(A) the sum of individual gm ' s of the transistors