An Overview of Pow Er Amplifier Research at Ucsd: Lots of Watts and Plenty of MHZ
An Overview of Pow Er Amplifier Research at Ucsd: Lots of Watts and Plenty of MHZ
An Overview of Pow Er Amplifier Research at Ucsd: Lots of Watts and Plenty of MHZ
An Overview of P ow er Am plifier
Research at UCSD
Peter Asbeck
Don Kimball
Cal IT2
Wireless
systems
High bandwidth
Future: higher frequency
High power
Low interference
n~4
Challenges for
Power
Amplifiers
Efficiency
Bandwidth
Integrability, low cost
Multiband, adaptivity
Low noise / interference
Agenda
Path to high efficiency & bandwidth
in Base-station PAs
Handset PA development
Future technology opportunities
Average power
Efficiency
0.8
Maximum power
EER/ET
0.6
0.4
Class B
0.2
Class A
0
0
0.2
0.4
0.6
0.8
Pout (normalized)
Probability
5.0%
Probability
4.0%
3.0%
2.0%
1.0%
0.0%
-60
-50
-40
-30
-20
-10
10
20
30
P out (dBm)
~8 dB peak to
average
power ratio
Envelope
Detector
DC
Supply
Envelope
Amplifier
Time
RF
Signal
In
RF
Amplifier
RF
Signal Out
Efficiency
Efficiency
For ET system
Vcc3
Vcc4
Vcc5
Vcc2
Vcc1
Pout (dBm)
ET System Maximizes Efficiency Vs Power
By Adjusting Output Bias (Vcc or Vdd)
Drain Modulator
DC/DC
DSP
I
Q
ET/EER and
Predistortion
DC
Envelope
DAC
Upcon
DAC
WCDMA
Downcon
PA
Drivers Final stage
ADC
F= 2.1 GHz
RF
Output
High Power
RF Stage
X1=0
Class F
Class F
Class B
Class F-1
VDC
Envelope
Signal
Voltage Source
High BW
Eff = 50%
Current Source
Low BW
Eff > 90%
VDC
Current
Sense
Switcher
Stage
Linear
Stage
DSP
Main Switcher
isw2
VDC
Current Source
Medium BW
Vsw2
Signal generation
Switcher control
Time alignment
VS
Envelope
Signal
iL2
VDC
L2
L2 < L1
D2
VDC
Current
Sense
Linear
Stage
Voltage Source
High BW
Vsw1
iLN
VR
iR
Aux
Switcher
L1
iL1
D1
Current Source
Low BW
isw1
Efficiency
After DPD
After
Memory
Mitigation*
Probability
PDF
WCDMA
6.6 dB PAPR
Pout=67W
Record
[dBc]
ACPR1
ACPR2
NRMSE
Before DPD
-35.4
-45.5
6.8%
After ML DPD
-45.3
-50.7
2.4%
After Memory
mitigation
-55.5
-60.2
0.7%
CE
Gain
PAE
RF PA
Envelope Amplifier
65.6%
12.3dB
61.7%
82%
80%
DC
Supply
Envelope
Amplifier
Vdd
RF
Power
Amplifier
RF Signal In
(WiMAX, 3GPP LTE)
RF Signal Out
Enough Bandwidth
New envelope: Power spectrum
time
frequency
|Vout| vs |Vin|
No correction
Memoryless correction
Full correction
(with memory effect)
Measurements for
commercial WLAN
amplifier
Agenda
Path to high efficiency & bandwidth in
Base-station PAs
Handset PA development
How to make a CMOS PA
How to make a mostly digital PA
Future technology opportunities
Stacked-FET Structure
Vds, i
Vds3
Vgs3
Vds2
Vgs2
Vds1, V
Vgs1, V
3.0
2.5
2.0
1.5
Vgs, i
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
time, nsec
Cm3
VDD
TL3
TL4
VG4
C4
TL6
m4
Cm4
VG3
C3
TL8
m3
TL7
In
VG2
Cm5
m2
Cm1
C2
Rf
Cf
RL
TL1
TL2
m1
GND
Cm2
VG1
VG2
In
GND
In
GND
In
GND
In
GND
Gate capacitors
VG3
VG4
GND
GND Out GND
Out
GND
Out
GND
Out
GND
4-Stacked CMOS PA
Performance with 1.9GHz WCDMA signal
VDD=6.5V
High power
Good efficiency
Good linearity
c
M6
Linear Stage
M3
M2
Rsen
Env_in
OTA
ia
M4
R1
R2
To PA
id
M1
OP AMP
Switching Stage
Q3
Q4
-60
ACPR
improve
-70
-80
-90
-110
1.9
Q1
PM
-50
-100
Buck
Converter
w/ PWM
DSP
Power/frequency (dB/Hz)
RL
Q2
Switched
Resonator
(res)
Digital PA Techniques
- RF pulse modulation
- Unit-cell switching
- Charge sampling regulator
1.91
1.92
1.93
1.94
1.95 1.96
Frequency (GHz)
1.97
1.98
1.99
100
x2.4
Total Efficiency (%)
AM
Slew Impairment
No Phase Correction
Slew Impairment
Phase PDM Correction
No Slew Impairment
No Phase Correction
-40
10
15dB back-off
0.1
850MHz
0.01
-10
10
20
30
40
Digitally-Modulated CMOS PA
Power controlled by number of
"on" transistors
Amplitude
Control Word
Bin.-to-Therm.
Decoder
1x
Decoder
Vdd
Tunable
Matching
Circuit
Input
Modulated
Signal
Decoder
1x
80
1/2 x
Pout/Pdc [%]
1x
Phase-modulated
Signal
70
60
50
40
30
20
10
1/8 x
3 Binary Cells
0
-20
-10
10
20
30
Input
DA
match
Inter
stage PA
match
Output
match
50
load
(nomi
nal)
Module
Average power
consumption assuming
CDMA power usage
profiles
Average
Performance
High Power
Performance
Urban
600
400
Sub-urban
454
500
371
Power Savings
~ 180mW
269
300
189
200
100
0
Original PA Module
Retuned PA w/ DPD
Agenda
Path to high efficiency & bandwidth
in Base-station PAs
Handset PA development
Future technology opportunities
Adaptive PAs
Broadband PAs
High frequency PAs
Wmax
Ni contact
n-GaN layer
Ti/Au/Pd/Au
n+GaN layer
GaN buffer layer
c-Sapphire
CF
C1
RF
Ranges from 54.4% to
76.6%
Measured Drain Eff.
Simulated Drain Eff.
Simulated Pout
Measured Pout
HRL Laboratories
Lg=40nm
Fmax=400GHz
BV~42V
Digital
Baseband
Modulator
DSP
Digital
Predistorter
LUT
Upcon
DAC verter
Signal Generator
DSP
Adaptation
Vin
Mem
Vout ADC
Mem
amplifier/antenna array
Data in
downconverter
All Si technology
40-60% efficiency
Summary
UCSD has a wide variety of projects for handset and
basestation PAs
multiple technologies, frequencies & power levels
CMOS / HBT / GaN
UCSD has expertise in Digital Predistortion Techniques
along with state-of-the-art test benches
State-of-art research is on-going in Envelope Tracking for
both Basestation and Handset PAs
=> critical to the future of high performance PAs
for signals with high PAR (eg LTE!)