Microprocessor 8085 Viva
Microprocessor 8085 Viva
Microprocessor 8085 Viva
what is microprocessor?
A9 This instruction adds 8 bit immediate data to the contents of accumulator and result is stored
in accumulator.
EX. ADI 20 H
Q.10 what is the function of ACI DATA?
A10: This instruction add the immediate data carry flag and accumulator and stored the result in
the accumulator.
EX. ACI 20 H
Title of the Practical: Multiplication of two 8- bit nos. using repeated Addition
Q.1 what is the function of RAR?
A1: Each binary bit of the accumulator is rotated right by one position through the carry flag .bit
D0 is placed in the carry flag and the bit in the carry flag is placed in the most significant position
D7.
Q.2 what is the function of RRC?
A2: Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the
position of D7 as well as in the carry flag.
Q.3 what is the function of RLC?
A3: Each binary bit of the accumulator is rotated left by one position .Bit D7 is placed in the
position of D0 as well as in the carry flag .
Q.4 what is the function of CALL instruction?
A4: -Call is a three byte instruction used to transfer program control to subroutine the starting
address is specified instruction.
Q.5 what is the function of RETURN instruction?
A5.Return instruction is a 1 byte instruction used to transfer program control back to main
program to implement this transfer is takes back the store contain of PC from stack and next
instruction executed will be from main program
Q.6 what do you mean by CONDITIONAL CALL instruction?
A6: - In conditional call instruction, when condition is true then a call at address is mode .If
condition is false then it will not have a call and will proceed for next instruction after it.
Q.7 what do you mean by UN-CONDITIONAL CALL instruction?
A7: UNCONDITIONAL CALL:- When this instruction is executed the program sequence is
transfer to the address specified in the instruction.
Q.8 what do you mean by UN-CONDITIONAL RETURN instruction?
A8: UNCONDITIONAL RETURN- When this instruction is executed program sequence Is transfer
from the subroutine to calling program. The return address is taken from stack and this address is
loaded in pc and the programmer execution beings at address Taken from stack
Q.9 what do you mean by CONDITIONAL CALL instruction?
A9: CONDITIONAL RETURN- In conditional RETURN instruction when the Condition is true then
only the RET is made at the address given by address if Condition is false it will proceed further
to execute the next instruction after it
Q.10 what is the function of RSTN?
A10: This instruction transfer the program Execution to a location depending on the instruction.
signal?
IO devices. if IO/
operation.
- This is a active low output signal used by the microprocessor to read data from
memory and peripheral device.
- This is a active low output signal used by the micro processor to write a data on
memory device and peripheral device.
Q.7:- what do you mean by addressing mode?
A7: - It is a way to define a data in a program is called addressing mode.
Q.8:- Explain the type of addressing mode?
A8: - There were five type of addressing mode
1. Immediate Addressing mode.
2. Register addressing mode
3. Direct addressing mode
4. Indirect addressing mode
5. Implicit addressing mode
Q.9:- what do you mean by ROM,?
A9: - ROM- The data in this memory can only be read, no writing is allowed. It is used to
permanent program.
A8: -The flow chart is a pictorial representation of various actions and computations that are
taken to perform any task. A flowchart is similar to a block diagram representing the structure of
the program.
Q.9:- what do you mean by Data transfer group instruction?
A9: -This group of instructions copies data from source to destination without modifying the
contents of the source.
Q.10:- what do you mean by Logical group instruction?
A10: - these groups of instructions perform logical operations such as AND, OR, EXOR, Rotate,
Complement etc.
program the function to all 3 input output ports it contains a register called control resister. The
control register gives the signals which are used to define the function of each input output ports
and in which mode they should operate.
Q2 Explain the operating mode of 8255?
A2 It can operate in three modes
1. Mode0- input output mode.
2. Mode1- strobe mode.
3. Mode2- strobe bidirectional
Q3:- What is trap and what is the vectored address of trap?
A3:- It is a non-maskable , edge & level triggered &vectored interrupt s/g used for emergency
purpose like power failure , smoke detector etc. The up doesnt execute any interrupt
acknowledge cycle to read interrupt from interrupting device. When trap signal is activated up
execute RST 4.5 instruction to generate starting address of TRAP. It is the highest priority
interrupt s/g among all interrupt &the memory location for TRAP s/g is 0024H.
Q4:- Differentiate between I/O mapped I/O & memory mapped/O?
8
A4: - In the peripheral mapped I/O all the input and output devices 2 = 256 input &256 output
Device can be connected to 8085 up hence the space range for I/O device is from 00H to FFH
Control signal used for input &output devices are I/O read & I/O write. The execution speed is
10T state. Decoding 8 bits of address is only required so hardware needed is less.
Memory Mapped: - In memory mapped I/O both I/O o/p device &memory device are treated as
memory. The device address is 16 bit hence the address range is 000H to FFFH. Control s/g
used in memory mapped I/O O/P is MEMR, MEMW
Q5:- What is call & return instruction?
A5: - Call: - When this instruction is executed the programme sequence is transfer to the address
Specifies in the instructions. Before transferring the sequence the programme counter contents
are stored on stack. The call instruction is used a sub-routine. Return:- return from subroutine .
When this instruction is executed sequence is transferred from The subroutine to the calling
program .The return address is taken from the stack & the program
execution begins in
address taken from stack.
A1 The 8237 is a programmable direct memory access controller housed in a 40-pin package It
has four independent channels with each channel capable of Transferring 64K bytes.
Q2 Explain the operating mode of 8237?
A2 It can operate in two modes1. Slave Mode- In the slave mode, the DMA controller is treated as a peripheral Using the
following stepsThe MPU selects the DMA controller through Chip Select.
The MPU writes the control words as illustrated in example in channel registers
and command/status registers by using control signals IOW and IOR.
2. Master Mode- After the initialization, the 8237 in master mode keeps Checking for a DMA
request, and the steps in data transfer can be listed As follows1.
2.
1. When the peripheral is ready for data transfer, it sends a high signal to DRQ.
2 In the next cycle, the MPU relinquishes the buses and sends the HLDA Signal to the 8237.
Q3. What do you mean by wait state? What is its need?
A3 A wait state is a delay experienced by P when accessing external memory or another
device that is slow to respond. the vice versa also cone into scenario. Now, to be able to access
slow memory the P must be able to delay the transfer until the memory access is complete. One
way is to increase the P clock period by reducing the clock frequency. Some Ps provide a
special control input called READY to allow the memory to set its own memory cycle time. If after
sending an address out, the P dies not receive a READY input from memory, it enters a wait
state for as long as the READY line is in 0 state. When the memory access is completed the
READY goes high to indicate that the memory is ready for specified transfer.
Q4. What is PSW?
A4 PSW (Program Status Word) represents the contents of the accumulator and the flag
register together considering the accumulator as the high order and flag as the low order
register as if it is the AF register pair. For example POP PSW.
Q5. What is ALE? Explain the functions of ALE in 8085.
A5 It is the acronym for Address Latch Enable (pin number 30) used to demultiplex the
multiplexed lower order address/data bus. During T1 the ALE goes HIGH. When ALE
goes HIGH, the latch is enabled. So the o/p changes according to the i/p data. During T1
the o/p of latch is 05H. When ALE goes LOW, the data byte 05H is latched until the next
ALE. And after the latching operation the o/p of the latch represents the lower order
Q.6:- what do you mean by Branching group instruction?
A6: these groups of instructions changes the path of program execution or sequence of program
execution.
Q7:- what do you mean by Stack and machine control group instruction?
A7: these groups of instructions performs stack and machine control functions such as PUSH,
POP, Halt, and enable/disable interrupt, no operation etc.
Q8:- What is debugging?
A8:-Debugging is a kind of process by which in any program used instructions & content of
Register are checked & error is found.
Q9:- Explain the types of debugging?
A9: - There are two types of debugging:1. Static debugging: - If the length & size of programme is small than static debugging is used.
2. Dynamic debugging: - If programme length & size is large than dynamic debugging is used.
Q10:-What is interrupt?
A10: - Interrupt: - is a data transfer by an external device peripheral can inform the
microprocessor that it is ready for communication & it request as Attention.
A1.The 8253 programmable interval timer is an Ic used to provide accurate time Delay under
software control it will work parallel with microprocessor. After the completing the require delay
time it will interrupt the Microprocessor to give the information above completion of job.
Q2 what is the function of 8251?
A2 8251 Ic is designed by Intel corporation for parallel communication. The Communication
between microprocessor and 8251 is done in parallel.The 8251 will convert the parallel data into
serial bit stream and Transmission serial output lines. At the same time if can receive serial data
on serial input lines converts it into parallel from and then transfer to microprocessor.
Q3 What is the operation of DMA?
A3 If the data is less than microprocessor will not waste its time. Its simply Transferring data
from input output to memory are memory to input output. But if the data is large then the transfer
rate from input output to memory or memory to input output will slow down. Because of
Microprocessor intervention. In such case to speed up the process of transferring the data under
the supervision of a device called DMA controller.
Q4:- Explain the types of interrupt?
A4: - There are two types of interrupt:1. Hardware interrupt
2. Software interrupt
3.
Q5:- Differentiate between software &hardware interrupt.
A5: - Difference between hardware &software interrupt.
1. Hardware interrupt: -
It is asynchronous event.
This interrupt is requested by executing instruction.
PC is incremented.
It cannot be ignored or masked.
It has highest priority among all interrupt.
2. Software interrupt: -
It is a synchronous event.
This interrupt is requested by external device.
PC is not incremented.
It can be masked.
A6. To make a fast data transfer, the MPU releases the control of its buses to DMA. DMA acts as
an external device and the active high input signal HOLD goes HIGH when the DMA is requesting
to the MPU to use its buses. After receiving the HOLD request from DMA, the MPU releases the
buses in the following machine cycle and generates an
active high output signal HLDA indicating the release of buses. Once the DMA gains that
control, it acts in the role of the MPU for data transfer.
A9. There are five flags in 8085.They are sign flag, zero flag, auxiliary carry flag, parity
flag and carry flag.
Q 10. What does memory-mapping mean?
A10 The memory mapping is the process of interfacing memories to microprocessor and
allocating addresses to each memory locations
which is used to hold the data transmitted from the microprocessor to I/O devices and
vice versa.
Q8. What is the need for interrupt controller?
A8 The interrupt controller is employed to expand the interrupt inputs. It can handle the
interrupt request from various devices and allow one by one to the processor.
Q9. What is synchronous data transfer scheme?
A9 For synchronous data transfer scheme, the processor does not check the readiness
of the device after a command have been issued for read/write operation. For this
scheme the processor will request the device to get ready and then read/write to the
device immediately after the request.
Q10. What is asynchronous data transfer scheme?
A10 In asynchronous data transfer scheme, first the processor sends a request to the
device for read/write operation. Then the processor keeps on polling the status of the
device. Once the device is ready, the processor executes a data transfer instruction to
complete the process.
Title of the Practical: Transfer Block of data bytes from one memory location to
another in same order & in reverse order.
Q1. What is IMR(Interrupt mask register)?
A1 IMR stores the masking bits of the interrupt lines to be masked. This register can be
programmed by an operation command word (OCW).
Q2. What is priority resolver?
A2 It determines the priorities of the bits set in the Interrupt request register (IRR).The bit
corresponding to the highest priority interrupt input is set in the ISR during INTA input.
Q3. What is the use of IRR?
A3 The interrupt request register is used to store all the interrupt levels which are
requesting the service. The eight interrupt inputs sets corresponding bits of the Interrupt
Request Register upon the service request.
Q4. What is Interrupt service register(ISR)?
A4 The interrupt service register stores all the levels that are currently being serviced.
Q5. What is the difference between SHLD and LHLD?
A5 SHLD- Store HL register pair in memory. This instruction is used to store the
contents of H and L register directly in to memory. LHLD- Load HL register pair from
memory. This instruction copies the contents of memory location given with in the
instruction in to the L register and the contents of next memory location in to the H
register.
Q6. What is the difference between STAX and LDAX?
A6 STAX rp Store the contents of Accumulator register (A) in memory location whose
address is specified by BC or DE register pair. LDAX rp Load Accumulator register (A)
with the contents of memory location whose address is specified by BC or DE register
pair.
Q7. Write an assembly language program to transfer data from memory block B1
to memory block B2?
A7
MVI C, 0AH;
Initialize counter
LXI H, 2200H;
LXI D, 2300H;
Loop: MOV A, M;
STAX D;
INX H;
INX D;
DCR C;
Decrement counter
JNZ Loop;
counter 0 repeat
HLT
Q8. What are the types of branching instructions?
A8 1. Jump instructions
2. Call and Return instructions
3. Restart instructions
Q9. Write an assembly language program to add 2 BCD numbers?
A9
LXI H,2200H;
Initialize pointer
MOV A,M ;
INX H;
ADD M ;
DAA ;
STA 2300;
HLT
Q10. Explain the instruction LXI rp,data (16)?
A10 LXI rp, data(16) Load 16 bit immediate data to specified register pair or
Stack pointer. The rp is 16 bit register pairs such as BC, DE, HL or stack pointer.
Q2. Write a program to subtract two numbers & exchange the digits using 8051?
A2
MOV A,#9F
MOV R0,#40
SUBB A,R0
SWAP A
Q4. Comparison between full address decoding and Partial address decoding?
A4
A5 This is used to transfer data between slower I/O device and the microprocessor. In
some applns, the speed of I/O systems is not compatible with the microprocessors
timings. So the microprocessor has to confirm whether the peripheral is ready or not. If
READY pin is high, the peripheral is ready otherwise 8085 enters in to wait state.
Q6. What is a Non-maskable interrupt?
A6 It is unaffected by any mask or interrupt enable. Eg: TRAP
Q7. What is a Data pointer register?
A7 The data pointer register (DPTR) consists of a high byte(DPH) and a low byte (DPL)
functions to hold 16 bit address. It may be manipulated as a 16-bit data register or as
independent 8-bit registers. It serves as a base register in indirect jumps, look up table
instructions and external data transfer.
Q8. What are the operating modes of 8279?
A8 1. Input modes : Scanned keyboard, Scanned sensor matrix , Strobe input
2. Display modes: Left entry (Type writer mode) ,Right entry (Calculator mode)
Q9. What are the different functional units in 8279?
A9 CPU interface section
Keyboard section
Display section
Scan section
Q10. What are the priority modes in 8259?
A10 a. Fully nested mode
b. Special fully nested mode
c. Rotating Priority mode
d. Special Masked mode
e. Polled mode
Title of the Practical: Find the sum of positive nos. from an array & store the
result at some memory location (Ignore negative nos.)
Q1. What is opcode fetch cycle?
A1 The opcode fetch cycle is a machine cycle executed to fetch the opcode of an
instruction stored in memory. Each instruction starts with opcode fetch machine cycle.
Q2. What are the instructions used to control the interrupts?
A2 EI
DI
RIM
SIM
Software
Hardware interrupts- The interrupts where the CPU pins are used to receive interrupt
requests , are called hardware interrupts.
Software interrupts This interrupt is caused by the execution of the instruction. These
are special instructions supported by the microprocessor.
Q5. What are the types of hardware interrupts?
A5 TRAP
Q6. Difference between memory mapped I/o and I/O mapped I/o?
A6 Memory mapped I/O
Thus Ao to A7 or A8 to A15
more hardware.
Less hardware.
Q10. Give some examples of port devices used in 8085 microprocessor based
system?
A10 The various port devices used in 8085 are 8212, 8155, 8156,8255,8355,8755.
memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition
interfaces like ADC, DAC is called micro controller.
Q9. List the features of 8051 micro controllers?
A9 Single supply +5v operation using HMOS technology. 4096 bytes program memory
on-chip. 128 data memory on chip. 4 register banks. 2 multiple modes, 16 bit
timer/counter Extensive Boolean processing capabilities.
Q10:- What is debugging?
A10:-Debugging is a kind of process by which in any program used instructions & content of
Register are checked & error is found.