Microprocessor Microcontroller
Microprocessor Microcontroller
MICROCONTROLLER VIVA
QUESTIONS
Engineering Funda YouTube Channel
Prof. Hitesh Dholakiya
SSASIT, Surat
MICROPROCESSOR AND MICROCONTROLLER VIVA QUESTIONS
Q-10 What do you mean by T-state, instruction cycle, and machine cycle?
Ans T-state-each clock period of clock signal is called T- state. Instruction cycle- the
time taken by the microprocessor to read an instruction from memory. It takes 1
to 6 machine cycle to read an instruction from memory.
Machine cycle- the time taken by data/ opcode / oprent from memory/ peripheral
devices to acknowledge the external hardware. It takes 1to6 T-state.
Q-11 What is assembler?
Ans An assembler translates a file of assembly language statements into a file of binary
Machine instructions and binary data.
Q-12 What is a Text segment?
Ans The text segment contains the machine language code for routines in the source
File. These routines may be unexcitable because of unresolved references.
Q-13 What is data segments?
Ans The data segment contains a binary representation of the data in the source file.
The data also may be incomplete because of unresolved references to labels in
other files.
Q-14 What is assembly language?
Ans Assembly language is the symbolic representation of a computer’s binary
Encoding machine language. Assembly language is more readable than machine
language because it uses symbols instead of bits. The symbols in assembly
language Name commonly occurring bit patterns, such as opcode and register
specifies, so people can read and remember them
Q-15 What is the difference between assembly language and high level language?
Ans Assembly language is a programming language. Its principal difference from
high-level languages such as BASIC, Java, and C is that assembly language
provides only a few, simple types of data and control flow. Assembly language
programs do not specify the type of value held in a variable. Instead, a programmer
must apply the appropriate operations (e.g., integer or floating-point addition) to
a value. In addition, in assembly language, programs must implement all control
flow with go tos. Both factors make assembly language programming for any
machine MIPS or 80x86 more difficult and error-prone than writing in a high-
level language.
Q-16 What do you mean by assembler directives?
Ans Assembler directives are the predefine mnemonics that tell the assembler how to
translate a program but do not produce machine instructions.
Q-17 What are the drawback of assembly language?
Ans Assembly language has many disadvantages that strongly argue against its
widespread use. Perhaps its major disadvantage is that programs written in
assembly language are inherently machine-specific and must be totally rewritten
to run on another computer architecture.. An assembly language program remains
tightly bound to its original architecture, even after the computer is eclipsed by
new, faster, and more cost-effective machines.
Q-18 What is linker?
Ans A linker s first task is to ensure that a program contains no undefined labels. The
linker matches the external symbols and unresolved references from a programs
files. An external symbol in one file resolves a reference from another file if both
refer to a label with the same name. Unmatched references mean a symbol was
used, but not defined anywhere in the program.
Ans This instruction add the contents of the specified register pair to the HL pair and
stores the result in HL pair. EX. – DAD B
Q-32 What do you mean by Immediate Addressing mode addressing mode?
Ans Immediate Addressing mode – In immediate addressing mode the data is given in
the instruction. It is a 2 Byte or 3 Byte instructions
Q-33 What do you mean by Direct addressing mode?
Ans Direct addressing mode – In direct addressing mode the address of the data is
given in the instruction. It is a 3 Byte instruction
Q-34 What do you mean by Indirect addressing Mode addressing mode?
Ans Indirect addressing Mode – In indirect addressing mode the address of the data is
not given by the instruction but a memory pointer indicate were the data is present.
Q-35 What do you mean by Resister addressing mode addressing mode?
Ans Resister addressing mode – In this addressing mode the data is present in any
general purpose resister. It is 1 Byte instruction.
Q-36 What do you mean by Implicit/Inherent addressing mode addressing mode?
Ans Implicit/Inherent addressing mode – In this addressing mode the memory location
of data/Operant is not given in the instruction, the instruction define itself in a
program.
Q-37 What do you mean by input device?
Ans The job of input device is to accept input from external world. The input may be
given using keyboardouseoystick, from operator. The input may be in the from of
Image using video camera and scanner.
Q-38 What do you mean by output device?
Ans The job of output device is to make the system user friendly by “displaying” or
“announcing”the required data or message. Most widely used output device is
CRT screen and LCD screen.
Q-39 What do you mean by memory unit?
Ans Memory is a storage device. Data and instruction entered in to a computer system
through input unit have to be stored inside the computer before actual processing
starts.
Q-40 What do you mean by RAM?
Ans RAM- the RAM is also called as Read/Write memory. The RAM is a volatile type
of memory. It allows programmer to read write data.
Q-41 What is the function of SUB R?
Ans This instruction subtracts the contents of the register from the contents of the
register R and result is placed in the accumulator the contents of register R are not
altered.
Q-42 What is the function of SUB M?
Ans This instruction subtract the contents of the memory location whose address is
given by HL from accumulator and result is placed in the accumulator. EX. – SUB
M
Q-43 What is the function of SBB R?
Ans This instruction subtracts register and borrow flag from the accumulator and stores
the result in the accumulator. EX. – SBB C
Q-44 What is the function of SBB M?
Ans This instruction subtracts contents of memory location and the borrow flag from
accumulator and result is placed in accumulator. EX. – A (HL) – BORROW –
ACCUMULATOR
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MICROPROCESSOR AND MICROCONTROLLER VIVA QUESTIONS
Ans Each binary bit of the accumulator is rotated left by one position through the carry
flag .Bit D7 is placed in the bit in the carry flag is placed in the least significant
position D0.
Q-60 What is the function of RAR?
Ans Each binary bit of the accumulator is rotated right by one position through the
carry flag .bit D0 is placed in the carry flag and the bit in the carry flag is placed
in the most significant position D7.
Q-61 What is the function of RRC?
Ans Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed
in the position of D7 as well as in the carry flag.
Q-62 What is the function of RLC?
Ans Each binary bit of the accumulator is rotated left by one position .Bit D7 is placed
in the position of D0 as well as in the carry flag.
Q-63 What is the function of CALL instruction?
Ans Call is a three byte instruction used to transfer program control to subroutine the
starting address is specified instruction.
Q-64 What is the function of RETURN instruction?
Ans Return instruction is a 1 byte instruction used to transfer program control back to
main program to implement this transfer is takes back the store contain of PC from
stack and next instruction executed will be from main program
Q-65 What do you mean by CONDITIONAL CALL instruction?
Ans In conditional call instruction, when condition is true then a call at address is mode
.If condition is false then it will not have a call and will proceed for next instruction
after it.
Q-66 What do you mean by UN-CONDITIONAL CALL instruction?
Ans UNCONDITIONAL CALL: - When this instruction is executed the program
sequence is transfer to the address specified in the instruction.
Q-67 What do you mean by UN-CONDITIONAL RETURN instruction?
Ans UNCONDITIONAL RETURN- When this instruction is executed program
sequence Is transfer from the subroutine to calling program. The return address is
taken from stack and this address is loaded in pc and the programmer execution
beings at address Taken from stack
Q-68 What do you mean by CONDITIONAL CALL instruction?
Ans CONDITIONAL RETURN- In conditional RETURN instruction when the
Condition is true then only the RET is made at the address given by address if
Condition is false it will proceed further to execute the next instruction after it
Q-69 What is the function of RSTN?
Ans This instruction transfer the program Execution to a location depending on the
instruction.
Q-70 What do you mean by the upcode fetch operation?
Ans The operations perform by the microprocessor read up code from program
memory is called up code fetch operation.
Q-71 What do you mean by the memory read operation?
Ans The operations perform by the microprocessor read data from memory that is
called memory read operation.
Q-72 What do you mean by memory write operation?
Ans The operations perform by the microprocessor write a data on memory that is
called memory write operation.
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Q-73 What do you mean by the I/O read and I/O write operation?
Ans I/O read- the operations perform by the microprocessor read data from I/O device.
I/O write- the operation perform by the microprocessor write a data on I/O device.
Q-74 What do you mean by the operant fetch operation?
Ans The operation perform by the microprocessor read operant from program memory.
Q-75 What is the function of I0/M (BAR), WR (BAR), and RD (BAR) signal?
Ans IO/M (BAR) -this is an output signal used by microprocessor to differentiate
memory devices and IO devices.
If IO/M (BAR) = 1 then the IO/M (BAR) related operation and IO/M (BAR) =0
then the memory related operation.
RD (BAR) - This is an active low output signal used by the microprocessor to
read data from memory and peripheral device.
WR (BAR) - This is an active low output signal used by the microprocessor to
write a data on memory device and peripheral device.
Q-76 What do you mean by addressing mode?
Ans It is a way to define a data in a program is called addressing mode.
Q-77 Explain the type of addressing mode?
Ans There were five type of addressing mode –
1. Immediate Addressing mode.
2. Register addressing mode
3. Direct addressing mode
4. Indirect addressing mode
5. Implicit addressing mode
Q-78 What do you mean by ROM?
Ans ROM- The data in this memory can only be read, no writing is allowed. It is used
to permanent program.
Q-79 What do you mean by PROM?
Ans PROM- The basic function is same as that masked ROM. But in PROM, we have
fuse link. Depending up on the bit pattern, fuse can be burnt or kept intact.
Q-80 What do you mean by EPROM?
Ans EPROM- It uses MOS circuitry to store data. They store 1’s and 0’s in form of
charge. The information stored can be erased by exposing the memory to UV light
which erases the data stored in all memory location.
Q-81 What do you mean by STATIC RAM?
Ans STATIC RAM- SRAM consists of flip flop, using either transistor or MOS. For
each bit we require one flip flop. It is fast memory.
Q-82 What do you mean by, DYNAMIC RAM?
Ans DYNAMIC RAM – In this type of memory a data is stored in form of charge in
capacitors. When data is 1, the capacitor will be charge and if data is 0, the
Capacitor will not be charge.
Q-83 What do you mean by processing unit?
Ans CPU is the brain of computer. CPU stands for central processing unit. Control unit
and arithmetic logic unit of a computer system are together known as central
processing unit.
Q-84 What do you mean by a data?
Ans Data are raw facts. Data can be any number name of a person name of place,
weight name of a book, name of store
Ans Call: - When this instruction is executed the programme sequence is transfer to
the address Specifies in the instructions. Before transferring the sequence the
programme counter contents are stored on stack. The call instruction is used a sub-
routine. Return: - return from subroutine. When this instruction is executed
sequence is transferred from The subroutine to the calling program .The return
address is taken from the stack & the program execution begins in address taken
from stack.
Q-95 What do you mean by Maskable interrupt?
Ans Maskable interrupt: - The up can be ignore/delay a maskable interrupt request.
It is used to interface peripherals.
Lower priority.
It mainly vectored or non-vectored.
Response time is high.
This interrupt does not disable non maskable interrupt.
Q-96 What do you mean by Maskable interrupt?
Ans Non-maskable interrupt: - The up cannot be masked/delay or nonmaskable
interrupt request. It is used for emergency purpose like power failure, smoke
detector etc. It has highest priority. It is vectored. The response time is low.
Non-maskable interrupt are used for disable all maskable interrupt. The execution
speed is 137T state for STA, LDA instruction & 7T state for MOVRd Rs
instruction. Since 16 bit address has to be decoded hence more hardware is
required.
Q-97 What do you mean by Vectored interrupt?
Ans Vectored interrupt: - are those interrupts which are automatically vectored to
specific location on memory page 00H without any external hardware. They do
not require INTA s/g or am I? P port. IN 8085 up out of five interrupt four are
vectored. These are TRAP RST7.5, 6.5, 5.5.
Q-98 What do you mean by Non- Vectored interrupt?
Ans Non- vectored interrupt: - non-vectored interrupt are not automatically vectored
to specific location on page 00H. An external hardware is required to transfer it to
a particular location. In 8085 up out of five interrupt only INTR require RSTN
instruction for its working RSTN is nothing but it is an s/w interrupt.
Q-99 What do you mean by jump instruction?
Ans The Jump instruction specifies the memory location explicitly. They are three byte
instruction. One byte for the operation code, followed by a 16 bit memory address.
Q-100 Which type of architecture 8085 has?
Ans 8085 has Von Neumann architecture. It was derived after the name of
mathematician John Von Neumann. It’s having 16 address bus and 8 bit data bus.
It can access 2^16 individual memory location.
Q-101 How many memory locations can be addressed by a microprocessor with 14
address lines?
Ans 2^14=16384
Q-102 8085 is how many bit microprocessor?
Ans 8 bit as its data bus is 8 bit.
Q-103 Why is data bus bi-directional?
Ans As it has to carry data from mp to external device or the reverse.
Q-104 What is the function of accumulator?
Ans This register is used to store 8-bit data and to perform arithmetic and logical
operations. The result of an operation is stored in the accumulator.
Q-105 What are tri-state devices and why they are essential in a bus oriented
system?
Ans Tri state logic devices have three states (0, 1 and high impedance). When the
enable maybe active high or active low) line is activated, the device works. The
disabled enable line makes the device at high impedance state and it is
disconnected from the circuit. For example see the tri stated inverter in the figure
shown. In microcomputer system the peripherals are connected in parallel between
address bus and data bus. Because of tri stated interfacing devices, peripherals do
not load the system buses.
Q-106 Why are program counter and stack pointer 16-bit registers?
Ans Because SP points to the beginning of stack memory (LXI SP 8000H) which is
16-bits. Also PC points to the memory locations (16-bits) of the instructions to be
executed tomaintain the proper sequence of execution of program.
Q-107 What does it mean by embedded system?
Ans A specialized computer system that is part of a larger system or machine.
Typically, an embedded system is housed on a single microprocessor board with
the programs stored in ROM. Virtually all appliances that have a digital interface
like watches, microwaves, VCRs, cars etc utilize embedded systems. Some
embedded systems include an operating system, but many are so specialized that
the entire logic can be implemented as a single program.
Q-108 What are the different addressing modes in 8085?
Ans Register: - Data is provided through the registers. Or operand is only register(s).
Example: MOV Rd, Rs.
Register indirect: - Operand M or register pair. Example: MOV A,M; LDAX B;
STAX D; MVI M,32H (exception for immediate addressing mode).
Direct: - Operand 8-bit port address or 16-bit memory address. Example: IN 84H,
OUT 84H, all CALLs.
Immediate: - Instruction having the letter I. Or immediate data to the destination
provided. Also all jump instructions as the meaning is jump immediately. Example
MVI M, 2H; ADI 47H; LXIH 2050 (exception for direct addressing mode).
Implicit: - No operand. Example: XCHG.
Q-109 What is the function of 8237?
Ans The 8237 is a programmable direct memory access controller housed in a 40-pin
package It has four independent channels with each channel capable of
Transferring 64K bytes.
Q-110 Explain the operating mode of 8237?
Ans It can operate in two modes-
1. Slave Mode- In the slave mode, the DMA controller is treated as a peripheral
Using the following steps-
1. The MPU selects the DMA controller through Chip Select.
2. The MPU writes the control words as illustrated in example in channel
registers and command/status registers by using control signals IOW and IOR.
2. Master Mode- After the initialization, the 8237 in master mode keeps
Checking for a DMA request, and the steps in data transfer can be listed As
follows-
1. When the peripheral is ready for data transfer, it sends a high signal to DRQ.
2 In the next cycle, the MPU relinquishes the buses and sends the HLDA Signal
to the 8237.
Q-111 What do you mean by wait state? What is its need?
Ans A wait state is a delay experienced by ìP when accessing external memory or
another device that is slow to respond. The vice versa also cone into scenario.
Now, to be able to access slow memory the ìP must be able to delay the transfer
until the memory access is complete. One way is to increase the ìP clock period
by reducing the clock frequency. Some ìPs provide a special control input called
READY to allow the memory to set its own memory cycle time. If after sending
an address out, the ìP dies not receive a READY input from memory, it enters a
wait state for as long as the READY line is in 0 state. When the memory access is
completed the READY goes high to indicate that the memory is ready for specified
transfer.
Q-112 What is PSW?
Ans PSW (Program Status Word) represents the contents of the accumulator and the
flag register together considering the accumulator as the high order and flag as the
low order register as if it is the AF register pair. For example POP PSW.
Q-113 What is ALE? Explain the functions of ALE in 8085.
Ans It is the acronym for Address Latch Enable (pin number 30) used to demultiplex
the multiplexed lower order address/data bus. During T1 the ALE goes HIGH.
When ALE goes HIGH, the latch is enabled. So the o/p changes according to the
i/p data. During T1 the o/p of latch is 05H. When ALE goes LOW, the data byte
05H is latched until the next ALE. And after the latching operation the o/p of the
latch represents the lower order
Q-114 What do you mean by Branching group instruction?
Ans These groups of instructions changes the path of program execution or sequence
of program execution.
Q-115 What do you mean by Stack and machine control group instruction?
Ans these groups of instructions performs stack and machine control functions such as
PUSH, POP, Halt, and enable/disable interrupt, no operation etc.
Q-116 What is debugging?
Ans Debugging is a kind of process by which in any program used instructions &
content of Register are checked & error is found.
Q-117 Explain the types of debugging?
Ans There are two types of debugging:-
1. Static debugging: - If the length & size of programme is small than static
debugging is used.
2. Dynamic debugging: - If programme length & size is large than dynamic
debugging is used.
Q-118 What is interrupt?
Ans Interrupt: - is a data transfer by an external device peripheral can inform the
microprocessor that it is ready for communication & it request as Attention.
Q-119 What is the function of 8253?
Ans The 8253 programmable interval timer is an Ic used to provide accurate time Delay
under software control it will work parallel with microprocessor. After the
completing the require delay time it will interrupt the Microprocessor to give the
information above completion of job.
Q-120 What is the function of 8251?
Ans Machine cycle is defined as the time required to complete one operation of
accessing memory input/output, or acknowledging an external request. This cycle
may consists of three to six T-states.
Q-135 Define T-state?
Ans T-state is defined as one subdivision of operation performed in one clock period.
These subdivisions are internal states synchronized with the system clock, and
each Tstate is precisely equal to one clock period.
Q-136 What is an instruction cycle?
Ans The sequence of operations that a processor has to carry out while executing the
instruction is called instruction cycle. Each instruction cycle of processor contains
a number of machine cycles.
Q-137 What is fetch and execute cycle?
Ans The instruction cycle is divided in to fetch and execute cycles. The fetch cycle is
executed to fetch the opcode from memory. The execute cycle is executed to
decode the instruction and to perform the work instructed by the instruction.
Q-138 List the flags of 8085?
Ans There are five flags in 8085.They are sign flag, zero flag, auxiliary carry flag,
parity flag and carry flag.
Q-139 What does memory-mapping mean?
Ans The memory mapping is the process of interfacing memories to microprocessor
and allocating addresses to each memory locations
Q-140 What is a port?
Ans The port is a buffered I/O, which is used to hold the data transmitted from the
microprocessor to I/O devices and vice versa.
Q-141 What is USART?
Ans The device which can be programmed to perform Synchronous or Asynchronous
serial communication is called USART (Universal Synchronous Asynchronous
Receiver Transmitter). Eg: INTEL 8251
Q-142 What is scanning in keyboard and what is scan time?
Ans The process of sending a zero to each row of a keyboard matrix and reading the
columns for key actuation is called scanning. The scan time is the time taken by
the processor to scan all the rows one by one starting from first row and coming
back to the first row again.
Q-143 What is programmable peripheral device?
Ans If the function performed by the peripheral device can be altered or changed by a
program instruction then the peripheral device is called programmable device. It
has control register. The device can be programmed by sending control word in
the prescribed format to the control register
Q-144 What is baud rate?
Ans The baud rate is the rate at which the serial data are transmitted. Baud rate is
defined as (The time for a bit cell). In some systems one bit cell has one data bit,
then the baud rate and bits/sec are same.
Q-145 What are the tasks involved in keyboard interface?
Ans The tasks involved in keyboard interfacing are sensing a key actuation,
Debouncing the key and generating key codes (Decoding the key). These tasks are
performed software if the keyboard is interfaced through ports and they are
performed by hardware if the keyboard is interfaces through 8279.
Q-146 How a keyboard matrix is formed in keyboard interface using 8279?
Ans The return lines, RL0 toRL7 of 8279 are used to form the columns of keyboard
matrix. In decoded scan lines SL0 t0SL3 of 8279 are used to form the rows of
keyboard matrix. In encoded scan mode, the output lines of external decoder are
used as rows of keyboard matrix. Output function in different operating modes
The port is a buffered I/O, which is used to hold the data transmitted from the
microprocessor to I/O devices and vice versa.
Q-147 What is the need for interrupt controller?
Ans The interrupt controller is employed to expand the interrupt inputs. It can handle
the interrupt request from various devices and allow one by one to the processor.
Q-148 What is synchronous data transfer scheme?
Ans For synchronous data transfer scheme, the processor does not check the readiness
of the device after a command have been issued for read/write operation. For this
scheme the processor will request the device to get ready and then read/write to
the device immediately after the request.
Q-149 What is asynchronous data transfer scheme?
Ans In asynchronous data transfer scheme, first the processor sends a request to the
device for read/write operation. Then the processor keeps on polling the status of
the device. Once the device is ready, the processor executes a data transfer
instruction to complete the process.
Q-150 What is IMR(Interrupt mask register)
Ans IMR stores the masking bits of the interrupt lines to be masked. This register can
be programmed by an operation command word (OCW).
Q-151 What is priority resolver?
Ans It determines the priorities of the bits set in the Interrupt request register (IRR).The
bit corresponding to the highest priority interrupt input is set in the ISR during
INTA input.
Q-152 What is the use of IRR?
Ans The interrupt request register is used to store all the interrupt levels which are
requesting the service. The eight interrupt inputs sets corresponding bits of the
Interrupt Request Register upon the service request.
Q-153 What is Interrupt service register (ISR)?
Ans The interrupt service register stores all the levels that are currently being serviced.
Q-154 What is the difference between SHLD and LHLD?
Ans SHLD- Store HL register pair in memory. This instruction is used to store the
contents of H and L register directly in to memory.
LHLD- Load HL register pair from memory. This instruction copies the contents
of memory location given with in the instruction in to the L register and the
contents of next memory location in to the H register.
Q-155 What is the difference between STAX and LDAX?
Ans STAX rp – Store the contents of Accumulator register (A) in memory location
whose address is specified by BC or DE register pair.
LDAX rp – Load Accumulator register (A) with the contents of memory location
whose address is specified by BC or DE register pair.
Q-156 Write an assembly language program to transfer data from memory block
B1 to memory block B2?
Ans MVI C, 0AH; Initialize counter
LXI H, 2200H; Initialize source memory pointer
LXI D, 2300H; Initialize destination memory pointer
Ans This is used to transfer data between slower I/O device and the microprocessor. In
some applns, the speed of I/O systems is not compatible with the microprocessor’s
timings. So the microprocessor has to confirm whether the peripheral is ready or
not. If READY pin is high, the peripheral is ready otherwise 8085 enters in to wait
state.
Q-165 What is a Non-maskable interrupt?
Ans It is unaffected by any mask or interrupt enable. Eg: TRAP
Q-166 What is a Data pointer register?
Ans The data pointer register (DPTR) consists of a high byte (DPH) and a low byte
(DPL) functions to hold 16 bit address. It may be manipulated as a 16-bit data
register or as independent 8-bit registers. It serves as a base register in indirect
jumps, look up table instructions and external data transfer.
Q-167 What are the operating modes of 8279?
Ans 1.Input Modes: Scanned Keyboard, Scanned sensor matrix , Strobe input
2. Display Modes: Left entry (Type writer mode ),Right entry (calculator
mode)
Q-168 What are the different functional units in 8279?
Ans CPU interface section
Keyboard section
Display section
Scan section
Q-169 What are the priority modes in 8259?
Ans a. Fully nested mode
b. Special fully nested mode
c. Rotating Priority mode
d. Special Masked mode
e. Polled mode
Q-170 What is opcode fetch cycle?
Ans The opcode fetch cycle is a machine cycle executed to fetch the opcode of an
instruction stored in memory. Each instruction starts with opcode fetch machine
cycle.
Q-171 What are the instructions used to control the interrupts?
Ans 1.EI
2.DI
3.RIM
4.SIM
Q-172 What is polling?
Ans In polling, the microprocessor’s software simply checks each of the I/O devices
every so often. During this check, the microprocessor tests to see if any device.
Needs servicing.
Q-173 What are the different types of interrupts?
Ans Hardware interrupts- The interrupts where the CPU pins are used to receive
interrupt requests , are called hardware interrupts.
RST 7.5
RST 6.5
RST 5.5
INTR
Q-175 Difference between memory mapped I/o and I/O mapped I/o?
Ans Memory mapped I/O
1. In this device address is 16- bit. Thus Ao to A15 lines are used to Generate
the device address
2. MEMR and MEMW control signals are used to control read and write I/O to
control read and write I/O operations
3. Instructions available are LDA, STA, MOV R,M , ADD M etc.
4. Data transfer is between any register and I/O device.
5. Decoding 16-bit address may require more hardware.
for system designer to select matched peripheral devices like memories, latches,
ports etc from a microprocessor system.
Q-181 What operation is performed during first T-state of every machine cycle in
8085?
Ans In 8085, during the first T-state of every machine cycle the low byte address is
latched into an external latch using ALE signal.
Q-182 What is interrupt acknowledge cycle?
Ans The interrupt acknowledge cycle is a machine cycle executed by 8085 processor
to get the address of the interrupt service routine in order to service the interrupt
device.
Q-183 What is vectored and non-vectored interrupt?
Ans When an interrupt is accepted, if the processor control branches to a specific
address defined by the manufacturer then the interrupt is called vectored interrupt.
In Non-vectored interrupt there is no specific address for storing the interrupt
service routine. Hence the interrupted device should give the address of the
interrupt service routine.
Q-184 List the software and hardware interrupts of 8085?
Ans Software interrupts : RST 0,RST 1,RST 2,RST 3,RST 4,RST 5,RST 6,RST 7
Hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Q-185 What is TRAP?
Ans The TRAP is a non-maskable interrupt of 8085. It is not disabled by processor
reset or after recognition of interrupt.
Q-186 How clock signals are generated in 8085 and what is the frequency of the
internal clock?
Ans The 8085 has the clock generation circuit on the chip but an external quartz crystal
or LC circuit or RC circuit should be connected at the pins X1 andX2. The
maximum internal clock frequency of 8085 is 3.03MHz.
Q-187 Define stack?
Ans Stack is a sequence of RAM memory locations defined by the programmer.
Q-188 What is program counter? How it is useful in program execution?
Ans The program counter keeps track of program execution. To execute a program the
starting address of the program is loaded in program counter. The PC sends out an
address to fetch a byte of instruction from memory and increments its content
automatically.
Q-189 Define opcode and operand?
Ans Opcode (operation code) is the part of an instruction that identifies a specific
operation. Operand is a part of instruction that represents a value on which the
instruction acts.
Q-190 How the 8085 processor differentiates a memory access and I/O access?
Ans The memory access and I/O access is differentiated using IO/M signal. The 8085
processor asserts IO/M low for memory operation and high for I/O operations.
Q-191 When the 8085 processor checks for an interrupt?
Ans In the second T-state of the last machine cycle of every instruction, the 8085
processor checks whether an interrupt request is made or not.
Q-192 Why interfacing is needed for I/O devices?
Ans Generally I/O devices are slow devices. Therefore the speed of I/O devices does
not match with the speed of microprocessor. And so an interface is provided
between system bus and I/O devices.
operation in programming. The sub instruction subtracts the source operand from
the destination operand leaving the result in the destination operand.
Q-212 What is Intel 8051?
Ans The Intel 8051 microcontroller is one of the most popular general purpose
microcontrollers in use today. The success of the Intel 8051 spawned a number of
clones which are collectively referred to as the MCS-51 family of
microcontrollers, which includes chips from vendors such as Atmel, Philips,
Infineon, and Texas Instruments. The Intel 8051 s a Harvard architecture
Q-213 What is Harvard architecture?
Ans The Harvard architecture is a computer architecture with physically separate
storage and signal pathways for instructions and data. The term originated from
the Harvard Mark I relaybased computer, which stored instructions on punched
tape (24 bits wide) and data in electromechanical counters.
Q-214 Enhanced 8051 devices are manufactured by?
Ans Enhanced 8051-compatible devices manufactured by more than 20 independent
manufacturers including Atmel, Infineon Technologies (formerly Siemens AG),
Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP
(formerly Philips Semiconductor), Nuvoton (formerly Winbond), ST
Microelectronics, Silicon Laboratories (formerly Cygnal), Texas Instruments,
Ramtron International, Silicon Storage Technology, and Cypress Semiconductor.
Q-215 What are the functions provide by 8051?
Ans The 8051 architecture provides many functions CPU, RAM, ROM, I/O, interrupt
logic, timer, etc, in a single package
Q-216 What are the features of 8051?
Ans List the features of 8051 micro controllers:-
1) Single supply +5v operation using HMOS technology.
2) 4096 bytes program memory on-chip.
3) 128 data memory on chip
4) 4 register banks
5) 2 multiple modes, 16 bit timer/counter
6) Extensive Boolean processing capabilities
7) 64KB external RAM size.
8) 32 bi-directional I/O lines.
Q-217 What is a particularly useful feature of the 8051?
Ans A particularly useful feature of the 8051 core is the inclusion of a Boolean
processing engine which allows bit-level Boolean logic operations to be carried
out directly and efficiently on internal registers and RAM. This feature helped
cement the 8051s popularity in industrial control applications. Another valued
feature is that it has four separate register sets, which can be used to greatly reduce
interrupt latency compared to the more common method of storing interrupt
context on a stack.
Q-218 What is MCS-51 UARTs?
Ans MCS-51 UARTs make it simple to use the chip as a serial communications
interface. External pins can be configured to connect to internal shift registers in
a variety of ways, and the internal timers can also be used, allowing serial
communications in a number of modes, both synchronous and asynchronous.
Q-219 What is the function of UART and timer?
Ans Once a UART, and a timer if necessary, have been configured, the programmer
needs only to write a simple interrupt routine to refill the send shift register
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whenever the last bit is shifted out by the UART and/or empty the full receive shift
register (copy the data somewhere else). The main program then performs serial
reads and writes simply by reading and writing 8-bit data to stacks.
Q-220 What are the components of MCS-51 based microcontrollers?
Ans MCS-51 based microcontrollers typically include one or two UARTs, two or three
timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-
addressable), up to 128 bytes of I/O, 512 bytes to 64 kB of internal program
memory, and sometimes a quantity of extended data RAM (ERAM) located in the
external data space.
Q-221 In 8051 how many clock cycles per machine cycle?
Ans The original 8051 core ran at 12 clock cycles per machine cycle. With most
instructions executing in one or two machine cycles.
Q-222 What are the features of modern 8051 based microcontrollers?
Ans Common features included in modern 8051 based microcontrollers include built-
in reset timers with brown-out detection, on-chip oscillators, self-programmable
Flash ROM program memory, boot loader code in ROM, EEPROM non-volatile
data storage, I²C, SPI, and USB host interfaces, CAN or LIN bus, PWM
generators, analog comparators, A/D and D/A converters, RTCs, extra counters
and timers, in-circuit debugging facilities, more interrupt sources, and extra power
saving modes.
Q-223 Can you explain Memory Architecture of 8051?
Ans The MCS-51 has four distinct types of memory – internal RAM, special function
registers, program memory, and external data memory.
Q-224 What is Internal RAM (IRAM)?
Ans Internal RAM (IRAM) is located from address 0 to address 0xFF. IRAM from
0x00 to 0x7F can be accessed directly, and the bytes from 0x20 to 0x2F are also
bit-addressable. IRAM from 0x80 to 0xFF must be accessed indirectly, using the
@R0 or @R1 syntax, with the address to access loaded in R0 or R1.
Q-225 What is Special function registers (SFR)?
Ans Special function registers (SFR) are located from address 0x80 to 0xFF, and are
accessed directly using the same instructions as for the lower half of IRAM. Some
of the SFRs are also bit addressable.
Q-226 What is Program memory (PMEM)?
Ans Program memory (PMEM, though less common in usage than IRAM and XRAM)
is located starting at address 0. It may be on- or off-chip, depending on the
particular model of chip being used. Program memory is read-only, though some
variants of the 8051 use on-chip flash memory and provide a method of re-
programming the memory in-system or in-application. Aside from storing code,
program memory can also store tables of constants that can be accessed by MOVC
A, @DPTR, using the 16-bit special function register DPTR.
Q-227 What is External data memory (XRAM)?
Ans External data memory (XRAM) also starts at address 0. It can also be on- or off-
chip; what makes it external is that it must be accessed using the MOVX (Move
eXternal) instruction. Many variants of the 8051 include the standard 256 bytes of
IRAM plus a few KB of XRAM on the chip. If more XRAM is required by an
application, the internal XRAM can be disabled, and all MOVX instructions will
fetch from the external bus.
Q-228 What are the hardware features of 8051?
Ans 8051 has specific hardware features such as the multiple register banks and bit
manipulation instructions. There are many commercial C compilers. SDCC is a
popular open source C compiler. Other high level languages such as Forth,
BASIC, Pascal/Object Pascal, PL/M and Modula-2 are available for the 8051, but
they are less widely used than C and assembly.
Q-229 What are the addressing modes of 8051?
Ans List the addressing modes of 8051:-
Direct addressing
Register addressing
Register indirect addressing
Implicit addressing
Immediate addressing
Index addressing
Bit addressing
Q-230 What type of operations allows any addressing mode?
Ans Many of the operations allow any addressing mode for the source or the
destination, for example, MOV 020h; 03fh will copy the value in memory location
0x3f in the internal RAM to the memory location 0x20, also in internal RAM.
Q-231 Why in the 8051 all arithmetic operations must use the accumulator?
Ans Because the 8051 is an accumulator-based architecture, all arithmetic operations
must use the accumulator, e.g. ADD A, 020h will add the value in memory
location 0x20 in the internal RAM to the accumulator.
Q-232 Define DA A?
Ans This is a decimal adjust instruction It adjusts the 8-bit value in ACC resulting from
operations like ADD or ADDC and produces two 4-bit digits (in packed Binary
Coded Decimal (BCD) format Effectively, this instruction performs the decimal
conversion by adding 00H, 06H, 60H or 66H to the accumulator, depending on
the initial value of ACC and PSW
If ACC bits A3-0 are greater than 9 (xxxx1010-xxxx1111), or if AC=1, then a
value 6 is added to the accumulator to produce a correct BCD digit in the lower
order nibble. If CY=1, because the high order bits A7-4 is now exceeding 9
(1010xxxx-1111xxxx), then these high order bits will be increased by 6 to produce
a correct proper BCD in the high order nibble but not clear the carry.
Q-233 Define Logical EX OR?
Ans This instruction performs the logical XOR (Exclusive OR) operation on the source
and destination operands and stores the result in the destination variable No flags
are affected
Example:XRL A,R0 If ACC=C3H (11000011) and R0=AAH (10101010), then
the instruction results in ACC=69H (01101001)
Q-234 Define CLR A instruction?
Ans CLR A This instruction clears the accumulator (all bits set to 0) No flags are
affected If ACC=C3H, then the instruction results in ACC=00H.
Q-235 Define RRC A instruction?
Ans The instruction rotates the accumulator contents one bit to the right through the
carry flag The original value of carry flag will move into Bit 7 of the accumulator
and Bit 0 rotated into carry flag. No other flags are affected If ACC=C3H
(11000011), and the carry flag is 0, the instruction results in ACC=61H
(01100001) with the carry.
Q-236 Define PUSH Direct?
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Ans This instruction increments the stack pointer (SP) by 1The contents of Direct,
which is an internal memory location or a SFR, are copied into the internal RAM
location addressed by the stack pointer No flags are affected Example: PUSH 22H
PUSH 23H
Initially the SP points to memory location 4FH and the contents of memory
locations 22H and 23H are 11H and 12H respectively. After the above
instructions, SP=51H, and the internal RAM locations 50H and 51H will store
11H and 12H respectively.
Q-237 Define POP instruction?
Ans This instruction reads the contents of the internal RAM location addressed by the
stack pointer (SP) and decrements the stack pointer by 1. The data read is then
transferred to the Direct address which is an internal memory or a SFR. No flags
are affected.
Example:
POP DPH
POP DPL
If SP=51H originally and internal RAM locations 4FH, 50H and 51H contain the
values 30H, 11H and 12H respectively, the instructions above leave SP=4FH and
DPTR=1211H POP SP If the above line of instruction follows, then SP=30H. In
this case, SP is decremented to 4EH before being loaded with the value popped
(30H).
Q-238 Define XCH instruction?
Ans This instruction swaps the contents of ACC with the contents of the indicated data
byte
Example: XCH A,@R0
Suppose R0=2EH, ACC=F3H (11110011) and internal RAM location 2EH=76H
(01110110). The result of the above instruction leaves RAM location 2EH=F3H
and ACC=76H.
Q-239 Define CLR[bit] instruction?
Ans This operation clears (reset to 0) the specified bit indicated in the instruction No
other flags are affected CLR instruction can operate on the carry flag or any
directly addressable .
Q-240 What is the operation performed by SETB[bit]?
Ans This operation sets the specified bit to 1 SETB instruction can operate on the carry
flag or any directly-addressable bit. No other flags are affected
Q-241 Define CPL [bit] instruction?
Ans This operation complements the bit indicated by the operand No other flags are
affected ı CPL instruction can operate on the carry flag or any directly addressable.
Q-242 What is interface?
Ans In the field of computer science, an interface refers to a point of interaction
between components, and is applicable at the level of both hardware and software.
This allows a component, whether a piece of hardware such as a graphics card or
a piece of software such as an internet browser, to function independently while
using interfaces to communicate with other components via an input/output
system and an associated protocol.
Q-243 What is hardware and software interface?
Ans In addition to hardware and software interfaces, a computing interface may refer
to the means of communication between the computer and the user by means of
peripheral devices such a monitor or a keyboard, an interface with the internet via
Internet Protocol, and any other point of communication involving a computer.
Q-244 Explain software interface?
Ans Software interface may refer to a range of different types of interface at different
levels: an operating system may interface with pieces of hardware, applications or
programs running on the operating system may need to interact via streams, and
in object oriented programs, objects within an application may need to interact via
methods.
Q-245 What is constants?
Ans In computer programming, a constant is a special kind of variable whose value
cannot typically be altered by the program during its execution (though in some
cases this can be circumvented, e.g. using self-modifying code). Many
programming languages make an explicit syntactic distinction between constant
and variable symbols.
Q-246 What is programming against software interface?
Ans The use of interfaces allows implementation of a programming style called
programming against interfaces. The idea behind this is to base the logic one
develops on the sole interface definition of the objects one uses and not to make
the code depend on the internal details. This allows the programmer the ability to
later change the behaviour of the system by simply swapping the object used with
another implementing the same interface. Pushing this idea to the limit one can
introduce the inversion of control which means leaving the context to inject the
code with the specific implementations of the interface that will be used to perform
the work.
Q-247 Explain hardware interface?
Ans Hardware interfaces exist in computing systems between many of the components
such as the various buses, storage devices, other Input/output devices, etc. A
hardware interface is described by the mechanical, electrical and logical signals at
the interface and the protocol for sequencing them (sometimes called signaling).
A standard interface, such as SCSI, decouples the design and introduction of
computing hardware, such as I/O devices, from the design and introduction of
other components of a computing system, thereby allowing users and
manufacturers great flexibility in the implementation of computing systems.
Q-248 What is protocol?
Ans The protocol is a description of 1the messages that are understood by the object,2
the arguments that these messages may be supplied with, and3 the types of results
that these messages return.4the invariants that are preserved despite modifications
to the state of an object5the exceptional situations that will be required to be
handled by clients to the object.
Q-249 What is display device?
Ans A display device is an output device for presentation of information for visual,
tactile or auditive reception, acquired, stored, or transmitted in various forms.
When the input information is supplied as an electrical signal, the display is called
electronic display.
Q-250 What is dot matrix display?
Ans A dot matrix display is a display device used to display information on machines,
clocks, railway departure indicators and many and other devices requiring a simple
display device of limited resolution. The display consists of a matrix of lights or
mechanical indicators arranged in a rectangular configuration (other shapes are
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also possible, although not common) such that by switching on or off selected
lights, text or graphics can be displayed. A dot matrix controller converts
instructions from a processor into signals which turns on or off lights in the matrix
so that the required display is produced.
Q-251 What are the common size of dot matrix display?
Ans Common sizes of dot matrix displays:
(1)128×16 (Two lined),
(2)128×32 (Four lined)
(3) 192×64 (Eight lined)
Q-252 What are the applications of 8051 chip?
Ans 8051 chips are used in a wide variety of control systems, telecom applications, and
robotics as well as in the automotive industry.
Q-253 Can you explain PIN 9 for 8051?
Ans PIN 9: PIN 9 is the reset pin which is used reset the microcontroller’s internal
registers and ports upon starting up. (Pin should be held high for 2 machine
cycles.)
Q-254 What are the function of PIN 40 and 20?
Ans PIN 40 and 20: Pins 40 and 20 are VCC and ground respectively. The 8051 chip
needs +5V 500mA to function properly, although there are lower powered
versions like the Atmel 2051 which is a scaled down version of the 8051 which
runs on +3V.
Q-255 What is the program start address of 8051?
Ans The 8051 starts executing program instructions from address 0x00 in the program
memory.
Q-256 What is meant by micro controller?
Ans A device which contains the microprocessor with integrated peripherals like
memory, serial ports, parallel ports, timer/counter, interrupt controller, data
acquisition interfaces like ADC, DAC is called micro controller
Q-257 Explain the operating mode 0 of 8051 serial port?
Ans In this mode serial data enters and exists through RXD, TXD outputs the shift
clock. 8-bits are transmitted or received: 8-data bits (LSB first). The baud rate is
fixed at 1/12 the oscillator frequency.
Q-258 Explain the mode 3 of 8051 serial port?
Ans In this mode, 11 bits are transmitted (through TXD) or (received (through RXD):
a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit
(1).It is same as mode 2 except the baud rate. The baud rate in mode 3 is variable.
Q-259 Explain the interrupts of 8051 micro controller?
Ans External interrupt 0 (IE0) – Highest priority
Timers interrupt 0 (TF0)
External interrupt 1 (IE1)
Timers interrupt 1 (TF1)
Serial port Interrupt
Receive interrupt (RI) - lowest priority
Transmit interrupt (TI)
Q-260 How many bytes of internal RAM and ROM supported by 8051 micro
controller?
Ans 128 bytes of internal RAM and 4 bytes of ROM.
Q-261 What are addressing modes of 8051 microcontroller?
Ans The MCS-51 instruction set offers several addressing modes, including
1.direct register, using ACC (the accumulator) and R0-R7
2.direct memory, which access the internal RAM or the SFRs, depending on the
address
3. Indirect memory, using R0, R1, or DPTR to hold the memory address. The
instruction used may vary to access internal RAM, external RAM, or program
memory.
4individual bits of a range of IRAM and some of the SFRs
Q-262 Define ADD instruction for 8051 microcontroller?
Ans Description: ADD and ADDC both add the value operand to the value of the
Accumulator, leaving the resulting value in the Accumulator. The value operand
is not affected. ADD and ADDC function identically except that ADDC adds the
value of operand as well as the value of the Carry flag whereas ADD does not add
the Carry flag to the result.
The Carry bit [C] is set if there is a carry-out of bit 7. In other words, if the
unsigned summed value of the Accumulator, operand and (in the case of ADDC)
the Carry flag exceeds 255 Carry is set. Otherwise, the Carry bit is cleared.
The Auxiliary Carry (AC) bit is set if there is a carry-out of bit 3. In other words,
if the unsigned summed value of the low nibble of the Accumulator, operand and
(in the case of ADDC) the Carry flag exceeds 15 the Auxiliary Carry flag is set.
Otherwise, the Auxiliary Carry flag is cleared. The Overflow (OV) bit is set if
there is a carry-out of bit 6 or out of bit 7, but not both. In other words, if the
addition of the Accumulator, operand and (in the case of ADDC) the Carry flag
treated as signed values results in a value that is out of the range of a signed byte
(-128 through +127) the Overflow flag is set. Otherwise, the Overflow flag is
cleared.
Q-263 Define AJMP instruction in 8051 microcontroller?
Ans AJMP unconditionally jumps to the indicated code address. The new value for the
Program Counter is calculated by replacing the least-significant-byte of the
Program Counter with the second byte of the AJMP instruction, and replacing bits
0-2 of the most-significant-byte of the Program Counter with 3 bits that indicate
the page of the byte following the AJMP instruction. Bits 3-7 of the most-
significant-byte of the Program Counter remain unchaged. Since only 11 bits of
the Program Counter are affected by AJMP, jumps may only be made to code
located within the same 2k block as the first byte that follows AJMP.
Q-264 Define ANL instruction in 8051 microcontroller?
Ans ANL does a bitwise [AND] operation between operand1 and operand2, leaving
the resulting value in operand1. The value of operand2 is not affected. A logical
[AND] compares the bits of each operand and sets the corresponding bit in the
resulting byte only if the bit was set in both of the original operands, otherwise the
resulting bit is cleared.
Q-265 Define CLR instruction?
Ans CLR clears (sets to 0) all the bit(s) of the indicated register. If the register is a bit
(including the carry bit), only the specified bit is affected. Clearing the
Accumulator sets the Accumulators value to 0.
Q-266 Define CPL instruction?
Ans CPL complements operand, leaving the result in operand. If operand is a single bit
then the state of the bit will be reversed. If operand is the Accumulator then all the
Ans This mode allows you to specify the operand by giving its actual memory address
(typically specified in hexadecimal format) or by giving its abbreviated name (e.g.
P3) Used for SFR accesses
Example:
MOV A, P3 ;Transfer the contents of ;Port 3 to the accumulator
MOV A, 020H; Transfer the contents of RAM; location 20H to the accumulator.
Q-274 Define indirect addressing mode?
Ans This mode uses a pointer to hold the effective address of the operand Only
registers R0, R1 and DPTR can be used as the pointer registers The R0 and R1
registers can hold an 8-bit address, whereas DPTR can hold a 16-bit address Used
for the upper data memory area
Examples:
1. MOV @R0, A; Store the content of; accumulator into the memory; location
pointed to by the contents; of register R0. R0 could have an; 8-bit address,
such as 60H.
2 MOVX A, @DPTR; Transfer the contents from; the memory location; pointed
to by DPTR into the; accumulator. DPTR could have a; 16-bit address, such
as1234H.
Q-275 Define immediate constrant addressing mode?
Ans This mode of addressing uses either an 8- or 16-bit constant value as the source
operand This constant is specified in the instruction, rather than in a register or a
memory location The destination register should hold the same data size which is
specified by the source operand
Examples:
ADD A,#030H ;Add 8-bit value of 30H to ;the accumulator register ;(which is an
8-bit register).MOV DPTR,#0FE00H ;Move 16-bit data constant ;FE00H into the
16-bit Data ;Pointer Register.
Q-276 Define ACALL Instruction?
Ans ACALL unconditionally calls a subroutine located at the indicated address. The
instruction increments the PC twice to obtain the address of the following
instruction, then pushes the 16-bit result onto the stack (low-order byte first) and
increments the stack pointer twice. The destination address is obtained by
successively concatenating the five high-order bits of the incremented PC, op code
bits 7-5, and the second byte of the instruction. The subroutine called must
therefore start within the same 2K block of program memory as the first byte of
the instruction following ACALL. No flags are affected.
Operation: ACAL L
(PC) ¬ (PC) + 2
(SP) ¬ (SP) + 1
((SP)) ¬ (PC7-0)
(SP) ¬ (SP) + 1
((SP)) ¬ (PC15-8)
(PC10-0) ¬ page address
Q-277 What are different instruction types?
Ans The C8051 instructions are divided into five functional groups:
1 Arithmetic operations
2 Logical operations
3 Data transfer operations
4 Boolean variable operations
Ans The interrupts including mAP are recognized only if the HOLD is not valid, hence
TRAP has lower priority than HOLD.
Q-318 What is masking and why it is required?
Ans Masking is preventing the interrupt from disturbing the current program
execution. When the processor is performing an important job (process) and if the
process should not be interrupted then all the interrupts should be masked or
disabled.
In processor with multiple interrupts, the lower priority interrupt can be masked
so as to prevent it from interrupting, the execution of interrupt service routine of
higher priority interrupt.
Q-319 When the 8085 processor accept hardware interrupt?
Ans The processor keeps on checking the interrupt pins at the second T -state of last
Machine cycle of every instruction. If the processor finds a valid interrupt signal
and if the interrupt is unmasked and enabled then the processor accepts the
interrupt. The acceptance of the interrupt is acknowledged by sending an OOA
signal to the interrupted device.
Q-320 When the 8085 processor will disable the interrupt system?
Ans The interrupts of 8085 except TRAP are disabled after anyone of the following
operations
1. Executing El instruction.
2. System or processor reset.
3. After reorganization (acceptance) of an interrupt.
Q-321 What is the function performed by Dl instruction?
Ans The function of Dl instruction is to enable the disabled interrupt system.
Q-322 What is the function performed by El instruction?
Ans The El instruction can be used to enable the interrupts after disabling.
Q-323 How the vector address is generated for the INTR interrupt of 8085?
Ans For the interrupt INTR, the interrupting device has to place either RST opcode or
CALL opcode followed by l6-bit address. I~RST opcode is placed then the
corresponding vector address is generated by the processor. In case of CALL
opcode the given l6-bit address will be the vector address.
Q-324 What happens to the 8085 processor when it is resetted?
Ans When the 8085 processor is resetted it execute the first instruction at the OOOOH
location. The 8085 resets (clears) instruction register, interrupt mask bits and other
registers.
Q-325 What are the operations performed by ALU of 8085?
Ans The operations performed by ALU of 8085 are Addition, Subtraction, Logical
AND, OR, Exclusive OR, Compare Complement, Increment, Decrement and Left
I Right shift
Q-326 What is a flag?
Ans Flag is a flip flop used to store the information about the status of the processor
and the status of the instruction executed most recently.
Q-327 Which interrupt has highest priority in 8085? What is the priority of other
interrupts?
Ans The TRAP has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and
INTR.
Q-328 What is an ALE?
Ans The ALE (Address Latch Enable) is a signal used to demultiplex the address and
data lines, using an external latch. It is used to enable the external latch.
Q-329 Explain the function of IO/M in 8085.
Ans The IO/M is used to differentiate memory access and I/O access. For IN and OUT
instruction it is high. For memory reference instructions it is low.
Q-330 What is HOLD and HLDA and how it is used?
Ans Hold and hold acknowledge signals are used for the Direct Memory Access
(DMA) type of data transfer. The DMA controller place a high on HOLD pin in
order to take control of the system bus. The HOLD request is acknowledged by
the 8085 by driving all its tristated pins to high impedance state and asserting
HLDA signal high.
Q-331 What is Polling?
Ans Polling is a scheme or an algorithm to identify the devices interrupting the
processor. Polling is employed when multiple devices interrupt the processor
through one interrupt pin of the processor.
Q-332 What are the different types of Polling?
Ans The polling can be classified into software and hardware polling. In software
polling the entire polling process is govern by a prograrn.1n hardware polling, the
hardware takes care of checking the status of interrupting devices and allowing
one by one to the processor.
Q-333 What are the operating modes of 8212?
Ans The 8212 can be hardwired to work either as a latch or tri-state buffer. If mode
(MD) pin is tied HIGH then it will work as a latch and so it can be used as output
port. If mode (MD) pin is tied LOW then it work as tri- state buffer and so it can
be used as input port.
Q-334 Explain the working of a handshake output port
Ans In handshake output operation, the processor will load a data to port. When the
port receives the data, it will inform the output device to collect the data. Once the
output device accepts the data, the port will inform the processor that it is empty.
Now the processor can load another data to port and the above process is repeated.
Q-335 What are the internal devices of 8255?
Ans The internal devices of 8255 are port-A, port-B and port-C. The ports can be
programmed for either input or output function in different operating modes.
Q-336 What are the functions performed by INTEL 8251A?
Ans The INTEL 825lA is used for converting parallel data to serial or vice versa. The
data transmission or reception can be either asynchronously or synchronously. The
8251A can be used to interface MODEM and establish serial communication
through MODEM over telephone lines.
Q-337 What is an Interrupt?
Ans Interrupt is a signal send by an external device to the processor so as to request the
processor to perform a particular task or work.
Q-338 What are the control words of 8251A and what are its functions?
Ans The control words of 8251A are Mode word and Command word. The mode word
informs 8251 about the baud rate, character length, parity and stop bits. The
command word can be send to enable the data transmission and reception.
Q-339 What are the information that can be obtained from the status word of 8251?
Ans The status word can be read by the CPU to check the readiness of the transmitter
or receiver and to check the character synchronization in synchronous reception.
It also provides information regarding various errors in the data received. The
various error conditions that can be checked from the status word are parity error,
overrun error and framing error.
Q-340 Give some examples of input devices to microprocessor-based system.
Ans The input devices used in the microprocessor-based system are Keyboards, DIP
switches, ADC, Floppy disc, etc.
Q-341 What is scanning in display and what is the scan time?
Ans In display devices, the process of sending display codes to 7 -segment LEDs to
display the LEDs one by one is called scanning (or multiplexed display). The scan
time is the time taken to display all the 7-segment LEDs one by one, starting from
first LED and coming back to the first LED again.
Q-342 What are the internal devices of a typical DAC?
Ans The internal devices of a DAC are R/2R resistive network, an internal latch and
current to voltage converting amplifier
Q-343 What is settling or conversion time in DAC?
Ans The time taken by the DAC to convert a given digital data to corresponding analog
signal is called conversion time.
Q-344 What are the different types of ADC?
Ans The different types of ADC are successive approximation ADC, counter type
ADC flash type ADC, integrator converters and voltage-to-frequency converters.
Q-345 How the microprocessor is synchronized with peripherals?
Ans The timing and control unit synchronizes all the microprocessor operations with
clock and generates control signals necessary for communication between the
microprocessor and peripherals.
Q-346 What is a minimum system and how it is formed in 8085?
Ans A minimum system is one which is formed using minimum number of IC chips,
The 8085 based minimum system is formed using 8155, 8355 and 8755.
Q-347 List the features of 8051 microcontroller?
Ans The features are
*single supply +5 volt operation using HMOS technology.
*4096 bytes program memory on chip(not on 8031)
*128 data memory on chip.
*Four register banks.
*Two multiple mode, 16-bit timer/counter.
*Extensive Boolean processing capabilities.
*64 KB external RAM size
*32 bidirectional individually addressible I/O lines.
*8 bit CPU optimized for control applications.
Q-348 Explain the operating mode2 of 8051 serial ports?
Ans In this mode 11 bits are transmitted(through TXD)or received (through RXD):a
start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON
transmit the 9th data bit (TB* in SCON)can be assigned the value of 0 or 1.Or for
eg:, the parity bit(P, in the PSW)could be moved into TB8.On receive the 9th data
bit go in to the RB8 in Special Function Register SCON, while the stop bit is
ignored. The baud rate is programmable to either 1/32or1/64 the oscillator
frequency
Q-349 Explain the mode3 of 8051 serial ports?
- Present state
- Overflow State
- Overrun State
Q-384 What is the Use of timer devices?
Ans - Real Time clock ticks.
- Initiating an event after a present delay time.
- Capturing the count vale at the timer.
- Scheduling of various tasks.
Q-385 Define I²C Bus.
Ans The two IC’s are mutually network through a common bus I s known as I²c bus.
It has two lines for carry signals. One line is for clock and one is for data. bi-
directional
Q-386 Define CAN Bus.
Ans The number of devices are networked and controlled through a network bus. It is
mainly used in automotive electronics.
Q-387 What is USB Bus?
Ans The Universal Serial Bus (USB) is a bus between a host system and a number of
interconnected peripherals. The serial devices are scanner, keyboard, printer,
etc….
Q-388 Give some example for Advanced Serial High Speed Buses.
Ans - IEEE 802.3
- XAUI
- XBI
- SONET OC-48
- SONET OC-192
Q-389 Define ISA Bus.
Ans It is a standard bus based on IBM standard architecture.
Q-390 What are PCI and PCI/X Bus?
Ans - PCI – A standard bus used as Peripheral Component Interconnect bus
- PCI/X – A standard bus used as PCI Extended Bus
Q-391 Define Master Slave Communication.
Ans A communication between two processors when one processor guides the
transmission of the bits to a slave after receiving acknowledgement from the
address slave.
Q-392 Handshaking signals.
Ans The signals before storing the bits at the port buffer or before accepting the bits
from the port buffer.
Q-393 What are the protocols used in Advanced Parallel High Speed Buses?
Ans - GMII
- XGMI
- CSIX-1
- RapidIO
Q-394 Explain the characteristics of parallel port devices.
Ans - A port device may have multi-byte data input buffer.
- A port may have a data Direction register (DDR).
- It is bidirectional.
Q-395 What are the advantages of assembly language coding?
Ans - It gives a precise control of the processor.
ENGINEERING FUNDA YOUTUBE CHANNEL PROF. HITESH DHOLAKIYA
MICROPROCESSOR AND MICROCONTROLLER VIVA QUESTIONS
Ans A function that calls itself is known as recursive function. It may be reentrant also.
Q-408 Define Queue.
Ans It is a data structure with a series of element with the first element waiting for an
operation. An operation can be done only in the first in first out (FIFO) mode.
Q-409 What are the steps involved in function calls?
Ans - Declaring a function.
- Defining statements in the function.
- Call to a function.
Q-410 Define Reentrant function.
Ans Reentrant function is usable by several tasks and routines synchronously (at the
same time). This is because all its argument values are retrievable from the stack.
Q-411 What are the 5 flags used in queue?
Ans - Qerrorflag
- hearderFlag
- trailingFlag
- CirQuflag
- PolyQuFlag
Q-412 How an object is characterized?
Ans - An identity (a reference to a memory block)
- A state ( its data, property, fields and attributes)
- A behavior (method or methods)
Q-413 Types of methods.
Ans - Method overloading
- Method overriding
Q-414 Define Method overloading.
Ans Methods can have same name in the inherited class. This is called as method
overloading.
Q-415 Define Method Overriding.
Ans Methods can have same name as well as same number of types of arguments in
the inherited class.
Q-416 What are the disadvantage of C++?
Ans - Template.
- Multiple Inheritance.
- Exceptional handling.
- Virtual base classes.
Q-417 Define Cross-compiler.
Ans The cross compiler runs on a host, but develops the machine codes for the targeted
system.
Q-418 What are the special functions of port 0 of 8051?
Ans Port 0 is used as a multiplexed low order address/data bus during the external
memory access. When ALE is enabled, the address on port 0 pins are latched and
bus is ready to act as a data bus when ALE is low.