PIC Microcontrollers

PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip
microcontrollers. These devices have been very successful in 8-bit microcontrollers. The main reason is that
Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the
microcontroller to suit customers' requirements. The development tools such as assembler and simulator are freely
available on the internet at www.microchip.com .
The architectures of various PIC microcontrollers can be divided as follows.
Low - end PIC Architectures :

Microchip PIC microcontrollers are available in various types. When PIC microcontroller MCU was first available from
General Instruments in early 1980's, the microcontroller consisted of a simple processor executing 12-bit wide
instructions with basic I/O functions. These devices are known as low-end architectures. They have limited program
memory and are meant for applications requiring simple interface functions and small program & data memories.
Some of the low-end device numbers are
12C5XX
16C5X
16C505
Mid range PIC Architectures

Mid range PIC architectures are built by upgrading low-end architectures with more number of peripherals, more
number of registers and more data/program memory. Some of the mid-range devices are
16C6X
16C7X
16F87X
Program memory type is indicated by an alphabet.
C = EPROM
F = Flash
RC = Mask ROM
Popularity of the PIC microcontrollers is due to the following factors.
1.

Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock cycles.

2.

Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed to 111 instructions
for 8051).

3.

Power-on-reset and brown-out reset. Brown-out-reset means when the power supply goes below a specified
voltage
(say
4V),
it
causes
PIC
to
reset;
hence
malfunction
is
avoided.
A watch dog timer (user programmable) resets the processor if the software/program ever malfunctions and
deviates from its normal operation.

4.

PIC microcontroller has four optional clock sources.

o

Low power crystal

Mid range crystal

High range crystal

RC oscillator (low cost).

5.

Programmable timers and on-chip ADC.

6.

Up to 12 independent interrupt sources.

7.

Powerful output pin control (25 mA (max.) current sourcing capability per pin.)

8.

EPROM/OTP/ROM/Flash memory option.

9.

I/O port expansion capability.

10. Free assembler and simulator support from Microchip at www.microchip.com

CPU Architecture:
The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates
instruction fetch and the operation on data/accessing of variables simultaneously.

Fig 16.1 CPU Architecture of PIC microcontroller

PIC Memory Organisation:

PIC microcontroller has 13 bits of program memory address. Hence it can address up to 8k of program memory. The
program counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or 4k. While addressing 2k of program
memory, only 11- bits are required. Hence two most significant bits of the program counter are ignored. Similarly,
while addressing 4k of memory, 12 bits are required. Hence the MSb of the program counter is ignored.

Fig 16.2 Program Memory map

The
program
memory
map
of
PIC16C74A
is
shown
in
Fig
16.2.
On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes
the processor to the mainline program.
When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the
interrupt service routine (ISR) is written at 004H.
Data memory (Register Files):
Data Memory is also known as Register File. Register File consists of two components.
1.

General purpose register file (same as RAM).

2.

Special purpose register file (similar to SFR in 8051).

Fig 16.3 Data Memory map

The special purpose register file consists of input/output ports and control registers. Addressing from 00H to FFH
requires 8 bits of address. However, the instructions that use direct addressing modes in PIC to address these
register files use 7 bits of instruction only. Therefore the register bank select (RP0) bit in the STATUS register is used
to select one of the register banks.
In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the data memory.

Specifications of some popular PIC microcontrollers are as follows:

Device

Program
Data RAM (bytes)
Memory (14bits)

I/O Pins ADC

Timers 8/16 CCP (PWM) USART SPI /

bits
I2C

16C74A

4K EPROM

192

33

8 bits x
8 channels

2/1

USART SPI /
I2C

16F877

8K Flash

368 (RAM)
256 (EEPROM)

33

10 bits x
8 channels

2/1

USART SPI /
I2C

Device

Interrupt Sources

Instruction Set

16C74A

12

35

16F877

15

35

PIC Microcontroller Clock

Most of the PIC microcontrollers can operate upto 20MHz. One instructions cycle (machine cycle) consists of four clock cycles.

Fig 17.1 Relation between instruction cycles and clock cycles for PIC microcontrollers
Instructions that do not require modification of program counter content get executed in one instruction cycle.
Although the architectures of various midrange 8 - bit PIC microcontroller are not the same, the variation is mostly interns of
addition of memory and peripherals. We will discuss here the architecture of a standard mid-range PIC microcontroller, 16C74A.
Unless mentioned otherwise, the information given here is for a PIC 16C74A microcontroller Chip.
Architecture of PIC16C74A

Fig 17.2 Basic Architecture of PIC 16C74A

The basic architecture of PIC16C74A is shown in fig 17.2. The architecture consists of Program memory, file registers and RAM,
ALU and CPU registers. It should be noted that the program Counter is 13 - bit and the program memory is organised as 14 - bit
word. Hence the program Memory capacity is 8k x 14 bit. Each instruction of PIC 16C74A is 14 - bit long. The various CPU
registers are discussed here.
CPU registers (registers commonly used by the CPU)
W, the working register, is used by many instructions as the source of an operand. This is similar to accumulator in 8051. It may
also serve as the destination for the result of the instruction execution. It is an 8 - bit register.

Fig 17.3

W register

STATUS Register

The STATUS register is a 8-bit register that stores the status of the processor. This also stores carry, zero and digit carry bits.
STATUS - address 03H, 83H

Fig 17.4 STATUS register

C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode.
FSR Register

(File Selection Register, address = 04H, 84H)

FSR is an 8-bit register used as data memory address pointer. This is used in indirect addressing mode.
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register. Accessing INDF access is the location pointed to by FSR in indirect addressing mode.
PCL Register

(Program Counter Low Byte, address = 02H, 82H)

PCL is actually the lower 8-bits of the 13-bit program counter. This is a both readable and writable register.
PCLATH Register

(Program Counter Latch, address = 0AH, 8AH)

PCLATH is a 8-bit register which can be used to decide the upper 5bits of the program counter. PCLATH is not the upper 5bits of
the program counter. PCLATH can be read from or written to without affecting the program counter. The upper 3bits of PCLATH
remain zero and they serve no purpose. When PCL is written to, the lower 5bits of PCLATH are automatically loaded to the upper
5bits of the program counter, as shown in the figure.

Fig 17.5 Schematic of how PCL is loaded from PCLATH

Program Counter Stack

An independent 8-level stack is used for the program counter. As the program counter is 13bit, the stack is organized as 8x13bit
registers. When an interrupt occurs, the program counter is pushed onto the stack. When the interrupt is being serviced, other
interrupts remain disabled. Hence, other 7 registers of the stack can be used for subroutine calls within an interrupt service
routine or within the mainline program.
Register File Map

Fig 17.6 Register File Map

It can be noted that some of the special purpose registers are available both in Bank-0 and Bank-1. These registers have the
same value in both banks. Changing the register content in one bank automatically changes its content in the other bank.
Port Structure and Pin Configuration of PIC 16C74A
As mentioned earlier, there is a large variety of PIC microcontrollers. However, the midrange architectures are widely used. Our
discussion will mainly confine to PIC16C74A whose architecture has most of the required features of a mid-range PIC
microcontroller. Study of any other mid-range PIC microcontroller will not cause much variation from the basic architecture of PIC

16C74A ..
PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port. In addition, they have the following alternate functions.

In addition to I/O pins, there is a Master clear pin (MCLR) which is equivalent to reset in 8051. However, unlike 8051, MCLR
should be pulled low to reset the micro controller. Since PIC16C74Ahas inherent power-on reset, no special connection is
required with MCLR pin to reset the micro controller on power-on.
There are two VDD pins and two VSS pins. There are two pins (OSC1 and OSC2) for connecting the crystal oscillator/ RC oscillator.
Hence the total number of pins with a 16C74A is 33+7=40. This IC is commonly available in a dual-in-pin (DIP) package.

Fig 17.7 Pin configuration of PIC 16C74A

Guidelines from Microchip Technology

For writing assembly language program Microchip Technology has suggested the following guidelines.

1.

Write instruction mnemonics in lower case. (e.g., movwf)

2.

Write the special register names, RAM variable names and bit names in upper case. (e.g., PCL, RP0, etc.)

3. Write instructions and subroutine labels in mixed case. (e.g., Mainline, LoopTime)
Instruction Set:

The instruction set for PIC16C74A consists of only 35 instructions. Some of these instructions are byte oriented

instructions and some are bit oriented instructions.

The byte oriented instructions that require two parameters (For example, movf f, F(W)) expect the f to be replaced
by the name of a special purpose register (e.g., PORTA) or the name of a RAM variable (e.g., NUM1), which serves
as the source of the operand. 'f' stands for file register. The F(W) parameter is the destination of the result of the
operation. It should be replaced by:
F, if the destination is to be the source register.
W, if the destination is to be the working register (i.e., Accumulator or W register).
The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to be replaced by the name of a
special purpose register or the name of a RAM variable. The 'b' parameter is to be replaced by a bit number ranging
from 0 to 7.
For example:
Z equ 2
btfsc STATUS, Z
Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS register and will skip the next
instruction if Z bit is clear.
The literal instructions require an operand having a known value (e.g., 0AH) or a label that represents a known
value.
For example:

NUM equ 0AH ;

movlw NUM ;

Assigns 0AH to the label NUM ( a constant )

will move 0AH to the W register.

Every instruction fits in a single 14-bit word. In addition, every instruction also executes in a single cycle, unless it
changes the content of the Program Counter. These features are due to the fact that PIC micro controller has been
designed on the principles of RISC (Reduced Instruction Set Computer) architecture.
Instruction set:

Description

Mnemonics

Instruction
Cycles

bcf f, b

Clear bit b of register f

bsf f, b

Set bit b of register f

clrw

Clear working register W

clrf f

Clear f

movlw k

Move literal 'k' to W

movwf f

Move W to f

movf f, F(W)

Move f to F or W

swapf f, F(W)

Swap nibbles of f, putting result in F or W

andlw k

And literal value into W

andwf f, F(W)

And W with F and put the result in W or F

andwf f, F(W)

And W with F and put the result in W or F

iorlw k

inclusive-OR literal value into W

iorwf f, F(W)

inclusive-OR W with f and put the result in F or W

xorlw k

Exclusive-OR literal value into W

xorwf f, F(W)

Exclusive-OR W with f and put the result in F or W

addlw k

Add the literal value to W and store the result in W

addwf f, F(W)

Add W to f and store the result in F or W

sublw k

Subtract the literal value from W and store the result in W

subwf f, F(W)

Subtract f from W and store the result in F or W

rlf f, F(W)

Copy f into F or W; rotate F or W left through the carry bit

rrf f, F(W)

Copy f into F or W; rotate F or W right through the carry bit

btfsc f, b

Test 'b' bit of the register f and skip the next instruction if bit is clear

1/2

btfss f, b

Test 'b' bit of the register f and skip the next instruction if bit is set

1/2

decfsz f, F(W)

Decrement f and copy the result to F or W; skip the next instruction if

the result is zero

1/2

incfcz f, F(W)

Increment f and copy the result to F or W; skip the next instruction if

the result is zero

1/2

goto label

Go to the instruction with the label "label"

call label

Go to the subroutine "label", push the Program Counter in the stack

retrun

Return from the subroutine, POP the Program Counter from the stack

retlw k

Retrun from the subroutine, POP the Program Counter from the
stack; put k in W

retie

Return from Interrupt Service Routine and re-enable interrupt

clrwdt

Clear Watch Dog Timer

sleep

Go into sleep/ stand by mode

nop

No operation

Encoding of instruction:

As has been discussed, each instruction is of 14-bit long. These 14-bits contain both op-code and the operand. Some
examples of instruction encoding are shown here.
Example-1:

bcf f, b
Operands:
Encoding:

Clear 'b' bit of register 'f'

0 f 127
0b7

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The activities in various clock cycles are as
follows.

Example-2:

goto K
Operand:
Operation:

Go to label 'k' instruction

0 K 2047 (11-bit address is specified)
K
PC <10:0>
PCLATH <4:3>

PC <12:11>

Encoding:

Since this instruction requires modification of program Counter, it takes two instruction cycles for execution.
Q-Cycle activities are shown as follows.

Discussion on I/O ports of PIC16C74A:

PIC16C74A has five I/O ports. Port-B, Port-C and Port-D have 8 pins each. Port-A and Port-E have 6 and 3 pins
respectively. Each port has bidirectional digital I/O capability. In addition, these I/O ports are multiplexed with alternate
functions for the peripheral devices on the microcontroller. In general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin. Each port latch has a corresponding TRIS (Tri-state Enable) register for
configuring the port either as an input or as an output. The port pins are designated by the alphabet R, followed by the
respective port (viz. A, B, C, D or E) and the pin number. For example, Port-A pins are named as RA0, RA1, etc.
Port-A

Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternate function) as analog inputs to the analog-to-

digital converter.

Fig 19.1 RA0-RA3 and RA5 pin of Port-A

The structure of Port-A pins RA0-RA3 and RA5 is shown in the figure. TRISA register decides whether the port-pin is
configured as an input or as an output (digital) pin. Setting a TRISA register bit puts the corresponding output driver in
high impedance mode. In this mode, the pin can be used as a digital or analog input. Clearing a bit in the TRISA
register puts the contents of the data latch on the selected pins, i.e., the pin functions as a digital output. Pins RA0-RA
and RA5 have current sourcing capability of 25mA.
The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin is an open drain pin and hence requires
external pull-up when configured as output pin. It is shown in the following figure.

Fig 19.2 RA4 pin Configuration

Configuration of Port-A pins
Example :

Set RA0-RA3 as outputs and RA4 - RA5 as inputs.

bcf STATUS, RP0 ;

clrf PORTA ;
bsf STATUS, RP0 ;
movlw 30H ;
movwf TRISA ;
Port-B

Select Bank-0
Clears the data latch
Select Bank-1
W
03H ( data direction )
Set RA0-RA3 as outputs, RA4-RA5 as inputs

Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is controlled by TRISB register. Setting a bit in
TRISB register puts the corresponding output in high impedance input mode. When a bit in TRISB is made zero, the
corresponding pin in Port-B outputs the content of the latch (output mode).
Each port pin has a weak internal pull-up that can be enabled by clearing bit
of OPTION register (bit-7). When
a pin is configured in the output mode, the weak pull-up is automatically turned off. Internal pull-up is used so that we
can directly drive a device from the pins.

Fig 19.3 Pins RB0-RB3 of Port-B

Configuration of Port-B pins
Example :

Set RB0-RB3 as outputs, RB4-RB5 as inputs, RB7 as output.

bcf STATUS, RP0

clrf PORTB
bsf STATUS, RP0
movlw 70H
movwf TRISB

Overview of Timer Modules :

PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0 and Timer-2 are 8-bit timers. Timer-1 is a
16-bit timer. Each timer module can generate an interrupt on timer overflow.
Timer-0 Overview:
The timer-0 module is a simple 8-bit UP counter. The clock source can be either the internal clock (f osc /4) or an external
clock. When the clock source is external, the Timer-0 module can be programmed to increment on either the rising or
falling clock edge. Timer-0 module has a programmable pre-scaler option. This pre-scaler can be assigned either to
Timer-0 or the Watch dog timer, but not to both.
The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it overflows and can cause an interrupt at that time
if that interrupt source has been enabled, (T0IE = 1), i.e., timer-0 interrupt enable bit = 1.

OPTION Register Configuration :

Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock source. The following OPTION register
configuration is for clock source = fosc /4 and no Watchdog timer.

Timer-0 use without pre-scalar

Internal clock source of f osc /4. (External clock source, if selected, can be applied at RA4/TOCKI input at PORTA).
The following diagram shows the timer use without the prescaler.

Fig 20.1 Timer - 0 operation without prescaler

Timer-0 use with pre-scalar:

The pre-scalar can be used either with the Timer-0 module or with the Watchdog timer. The pre-scalar is available for
Timer-0 if the pre-scalar assignment bit PSA in the OPTION register is 0. Pre-scalar is a programmable divide by n
counter that divides the available clock by a pre-specified number before applying to the Timer-0 counter.

Fig 20.2 Timer - 0 with prescaler

Timer - 1 Module
Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and
writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000H to FFFFH and rolls over to 0000H. The
TMR1 interrupt, if enabled, is generated on overflow, which sets the interrupt flag bit TMR1IF (bit-0 of PIR1 register).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1 register).
The operating and control modes of Timer1 are determined by the special purpose register T1CON.
Various bits of T1CON register are given as follows:-

Fig 21.1 T1CON Register

ON
:
Timer1
0 = stops Timer 1;
1 = Enables Timer 1
:
Timer
1
Clock
1
=
External

TMR1
TMR1CS

0 = Internal Clock (
:

Timer

1
(Valid
1

ON
source
Clock

bit

Select
Bit
(RCO/T1OSO/T1CKI)

)
External
if
-

Clock

Input
TMR1CS

Do

Synchronization
Bit
=
1)
not
synchronize

0 - Synchronize
T1OSCEN:

Oscillator
1
0 = Oscillator is shut off

Timer 1 Input Clock Prescaler

Select bits

Prescaler Value

enable
Oscillator

control
is

bit
enabled

T1CKPS1 T1CKPS0

1:8

1:4

1:2

1:1

Fig 21.2

Operation of Timer 1

Timer 1 can operate in one of the two modes

As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in every instruction cycle. The timer 1 clock
source is
. Since the internal clock is selected, the timer is always synchronized and there is no further
need of synchronization.

As a counter (TMR1CS = 1). In the counter mode, external clock input from the pin RCO/T1CKI is selected.
Reading and writing Timer 1

Reading TMR1H and TMR1L from Timer 1, when it is running from an external clock source, have to be done with care.
Reading TMR1H or TMR1L for independent 8 - bit values does not pose any problem. When the 16-bit value of the
Timer is required, the high byte (TMR1H) is read first followed by the low byte (THR1lL). It should be ensured that
TMR1L does not overflow (that is goes from FFH to 00H) since THR1H was read. This condition is verified by reading

TMR1H once again and comparing with previous value of TMR1H.

Example Program
Reading 16bit of free running Timer 1
movf TMR1H
;
read high byte
movwf TMPH
;
store in TMPH
movf TMR1L
;
read low byte
movwf TMPL
;
store in TMPL
movf TMR1H, W
;
read high byte in W
subwf TMPH, W
;
subtract 1 st read with 2 nd read
btfsc STATUS, Z
;
and check for equality
goto next ;
; if the high bytes differ, then there is an overflow
; read the high byte again followed by the low byte
movf TMR1H, W
;
read high byte
movwf TMPH
movf TMR1L, W
;
read low byte
movwf TMPL
next : nop
Timer 2 Overview

Fig 21.3 Schematic diagram showing operation of Timer 2

Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used as the PWM time base for PWM mode of
capture compare PWM (CCP) modules. The TMR2 register is readable and writable and is cleared on device reset.

The input clock (

register respectively.

) has a pre-scaler option of 1:1, 1:4 or 1:16 which is selected by bit 0 and bit 1 of T2CON

The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is equal to PR2 and then
resets to 00H on the next clock cycle. PR2 is a readable and writable register. PR2 is initailised to FFH on reset.

The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to generate a TMR2 interrupt by setting TMR2IF.

Fig 21.4 The T2CON Register

Interrupt Logic in PIC 16C74A

PIC 16C74A microcontroller has one vectored interrupt location (i.e., 0004H) but has 12 interrupt sources. There is no
interrupt priority. Only one interrupt is served at a time. However interrupts can be masked. The interrupt logic is shown
below :

Fig 21.5 Schematic diagram showing the interrupt logic for PIC

Capture / Compare /PWM (CCP) Modules:

PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register (two 8-bit registers) and can operate in
one of the three modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The details
of the two modules (CCP1 and CCp2) are given as follows.

CCP1 Module:
CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1 Module.
CCP2 Module:

CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H (high byte). The CCP1CON
register controls the operation of CCP2 Module.
Both CCP1 and CCP2 modules are identical in operation with the exception of the operation of special event trigger.
The following table shows the timer resources for the CCP Mode.
CCP Mode

Timer Used

Capture

Timer 1

Compare

Timer 1

PWM

Timer 2

CCP1CON Register (Address 17H )

CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register address is 1DH. CCP1CON controls
CCP module1 where as CCP2CON controls CCP Module2.

Bit 5-4:
CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture mode. In PWM Mode, these bits are the
two Lsbs of the PWM duty cycle. The eight Msbs are found in CCPR1L. Thus the PWM mode operates in 10-bit mode.
Bit 3-0:
CCP1M3:CCP1MO (CCP1 Mode select bits)
0000=Capture/Compare/PWM Mode off
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4 th rising edge
0111=Capture mode, every 16 th rising edge
1000=Compare mode, set output on match (CCP1IF bit is set)
1001=Compare mode, clear output on match (CCP1IF bit is set)
1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin unaffected)
1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets Tmr1; CCP2 resets TMR1 and starts A/D
conversion if A/D module is Enabled)
11XX=PWM mode.
Capture Mode (CCP1):

Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register pair in response to an event occurring
on RC2/CCP1 pin. Capture Mode for CCP2 is exactly similar to that of CCP1.
An event on RC2/CCP1 pin is defined as follows:

Every falling edge

Every rising edge.

Every 4 th rising edge.

Every 16 th rising edge.

As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register.

Schematic diagram for capture mode of operation

Fig 22.1 Capture operation

Required condition for capture mode:

1.

RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2).

2.

Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or in synchronized counter mode.

Compare Mode (CCP1)

Compare mode for CCP2 is similar to that of CCP1, except that in special event trigger mode, CCP1 resets TMR1 only,
whereas CCP2 resets TMR1 and starts A/D conversion if A/D module is enabled.
In compare mode, the 16-bit CCPR1 register value is compared against TMR1 register pair (TMR1H and TMR1L)
value. When a match occurs, the RC2/CCP1 pin is driven high or driven low or remains unchanged as decided by
CCP1CON<3:0> bits.

Fig 22.2 Compare Operation

Required conditions for compare mode

1.

RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit.

2.

Timer-1 should be operated in timer mode (i.e., internal clock source of fosc/4) or in synchronized counter
mode.
In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected.
As shown in the figure, in special event trigger mode, both CCP1 and CCP2 intiates an A/D conversion.
PWM mode (CCP1)
Both CCP1 and CCP2 have similar operation in PWM mode. Here we will discuss PWM with respect to CCP1.
In PWM mode, the CCP1 pin produces upto a 10-bit resolution Pulse Width Modulation (PWM) output. RC2/CCP1 pin
should
be
configured
in
the
uotput
mode
by
clearing
TRISC<2>
bit.
The schematic block diagram of CCP1 module in PWM mode is shown in the figure.

Fig 22.3 PWM Operation

It can be noted that PR2 (Period Register, 8 bit) decides the PWM period where CCPR1L (8-bits) and CCP1CON
<5:4> (2-bits) decide the PWM duty cycle. When TMR2 equals PR2, the SR latch is set and RC2/CCP1 pin is pulled
high. In the same time, TMR2 is cleared and the duty cycle value available in CCPR1L is latched to CCPR1H.
CCPR1H, CCP1CON <5:4> decide the duty cycle and when this 10-bit ewquals the TMR2+2 prescaler or Q-bits, the
SR latch is set and RC2/CCP1 pin is driven low.

A PWM output as shown has a time period. The time for which the output stays high is called duty cycle.
PWM Period
The PWM period is specified by writing to PR2 register. The PWM period can be calculated using the following formula:
PWM
period
=
PWM frequency = 1/ PWM period

[( PR 2)

1] 4 T osc (TMR2

prescale

value)

When TMR2 is equal to PR2, the following events occur on the next increment cycle.

TMR2 is cleared

the CCP1 pin is set (if PWM duty cycle is 0

The PWM duty cycle is latched from CCPR1L into CCPR1H

PWM duty cycle

The PWM duty cycle is specified by writing to the CCPR1L register and to CCP1CON < 5 : 4 >
bits. Up to 10-bit resolution is available where CCPR1L contains the eight MSBs and CCP1CON < 5 : 4 > contains the
two LSB's. The 10-bit value is represented by CCPR1L : CCP1CON < 5 : 4 >.
The PWM duty cycle is given by
PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc . (TMR2 prescale value)
To understand the 10-bit counter configuration from Timer-2, let us first see the counting mechanism of Timer-2, as
shown in Fig 22.4.

Fig 22.4 Counting mechanism in Timer - 2

If the prescaler is 1, the 10-bit counter is configured as follows

Fig 22.5 Prescaler set to divide by one

If the prescaler is 4, the 10-bit counter is configured as follows.

Fig 22.6 Prescaler programed to divide by four

If the prescaler is 16, the 10-bit counter is realized as follows.

Fig 22.7 Prescaler programed to divide by 16

Although CCPR1L and CCP1CON < 5 : 4 > can be written to at anytime, the duty cycle value is not latched into
CCPR1H until a match between PR2 and TMR2 occurs. In PWM mode, CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is
essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal
2-bit Q clock or 2-bits of prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM
frequency can be calculated as

If the PWM duty cycle is longer than the PWM period, then the CCP1 pin will not be cleared.

PWM Period and duty cycle calculation

Example:
Desired PWM frequency = 78.125 kHz
f osc = 20MHz
TMR2 Prescalar = 1

Find the maximum resolution of duty cycle that can be used with a 78.124 kHz frequency and 20 MHz oscillator.

256 = 2PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and 20 MHz oscillator
ie, 0 CCPR1L : CCP1CON <5 : 4> 255 .
Any value greater than 255 will result in a 100 % duty cycle. The following table gives the PWM frequency fPWM if fosc =
20MHz
Duty cycle resolution

10-Bit counter scale

PR2 value

Prescaler 1

Prescaler 4

Prescaler 16

10 bit

1024

255

19.53 KHz

4.88 kHz

1.22 kHz

10 bit

1000

249

20kHz

5kHz

1.25kHz

8 bit

256

63

78.125kHz

19.53kHz

4.88kHz

6 bit

64

15

312.5kHz

78.125kHz

19.53kHz

I2C Bus for Peripherals Chip Access

I2C Communication in PIC Microcontroller
I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bi-directional interface for connecting
one or more master processors with one or more slave devices, such as an EEPROM, ADC, RAM, LCD display,
DAC, etc. I 2C interface requires two open drain I/O pins, viz. SDA (Serial Data) and SCL (Serial Clock).
The reason for open drain connection is that the data transfer is bi-directional and any of the devices connected
to the I 2C bus can drive the data line (SDA). The serial clock line (SCL) is usually driven by the master. Since
SDA and SCL pins are open drain pins, external pull-up resistances are required for operation of I 2C bus.
A typical I2C bus showing the connection of multi-master and multi-slave configuration is shown in the following
figure.

Fig 26.1 Multimaster Multislave Connection

Some conventions are followed in I2C communication. Let us assume that there is one master and one slave
and 8-data bits are sent. We will initially assume that the master is the transmitter and the slave is the receiver.
The clock is driven by the master. On receiving 8-bits, an acknowledgement bit is driven by the receiver on SDA
line. The acknowledgement bit is usually Low (0). The following diagram shows the data communication pattern
having 8 data bits and one acknowledgement bit.

Fig 26.2 Timing diagram for data transfer

The following features are to be noted 1.

SDA line transmits/ receives data bits. MSB is sent first.

2.

Data in SDA line is stable during clock (SCL) high. A new bit is initiated at the negative clock transition
after a specified hold time.

3.

Serial clock (SCL) is driven by the master.

4.

An acknowledgement bit (0) is driven by the receiver after the end of reception. If the receiver does not
acknowledge, SDA line remains high (1).

I2C bus transfer consists of a number of byte transfers within a START condition and either another START
condition or a STOP condition. During the idle state when no data transfer is taking place, both SDA and SCL
lines are released by all the devices and remains high. When a master wants to initiate a data transfer, it pulls
SDA low followed by SCL being pulled low. This is called START condition. Similarly, when the processor wants
to terminate the data transfer it first releases SCL (SCL becomes high) and then SDA. This is called a STOP

condition. START and STOP conditions are shown in the diagram as follows.

Fig 26.3 Timing diagram for START and STOP Conditions

START and STOP conditions are unique and they never happen within a data transfer.
Data Communication Protocol:
In I2C communication both 7-bit and 10-bit slave addressing are possible. In 7-bit addressing mode 128 slaves
can be interfaced with a single master. Similarly, in 10-bit addressing mode, 1024 slaves can be interfaced with
the master. We will discuss here 7-bit addressing mode only. 10-bit addressing mode is similar to 7-bit
addressing except from the fact that the number of address bits is more.
Following a 'start' condition, the master sends a 7-bit address of the slave on SDA line. The MSB is sent first.
After sending 7-bit address of the slave peripheral, a R/

(8th bit) bit is sent by the master. If R/

bit is '0', the

following byte (after the acknowledgement bit) is written by the master to the addressed slave peripheral. If R/
=1, the following byte (after the acknowledgement bit) has to be read from the slave by the master.
After sending the 7-bit address of the slave, the master sends the address (usually 8 bit) of the internal register
of the slave wherefrom the data has to be read or written to. The subsequent access is automatically directed to
the next address of the internal register.
The following diagrams give the general format to write and read from several peripheral internal registers.

Fig 26.4 Data transfer protocol for writing to a slave device

R/

(Read / Write) bit indicates whether the data is to be written by the master or read by the master. If R/

is

1, the subsequent data are to be read by the master. If R/

= 0, the subsequent data are to be written by the
master to the addressed slave. It has to be noted that the slave address is sent first, following a 'start' condition.

The addressed slave responds by acknowledging and gets ready for data transfer.
If data has to be read from a specific address of the slave device, the master sends the 7-bit address of the
slave first following a 'start' condition. R/
bit is sent as 'low'. The addressed slave acknowledges by pulling the
ACK line low. The master then sends the 8-bit internal address of the slave from which data has to be read. The
slave acknowledges. Since R/

bit was initially 0, the master is in the write mode. To change this to read mode,

the 'start' condition is again generated followed by 7-bit address of the slave with R/
= 1. The slave
acknowledges. The slave then sends data from previously specified internal address to the master. The master
acknowledges by pulling ACK bit low. The data transfer stops when the master does not acknowledge the data
reception and a 'stop' condition is generated.

Bus operationBus subroutines

Serial EEPROM
Analog to Digital Converter
UART-Baud rate selection
Data handling circuit
Initialization
LCD and keyboard Interfacing
ADC, DAC, and
ADC Module
An analog-to-digital converter (ADC) converts an analog signal into an equivalent digital number. PIC 16C74A has
an inbuilt ADC with the following features

8-bit conversion

8 analog input channels

An analog multiplexer

A sample and hold circuit for signal on the selected input channel

Alternative clock sources for carrying out conversion

Adjustable sampling rate

Choice of an internal or external reference voltage

Interrupt to microcontroller on end of conversion

Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D conversion, the input analog
voltage is digitized and an equivalent digital output is generated as shown in the figure.

Fig 23.1 Digital output versus analog input

Port-A pins (Alternate functions)

RA0/AN0
can be used as analog input-0
RA1/AN1
can be used as analog input-1
RA2/AN2
can be used as analog input-2
RA3/AN3/Vref can be used as analog input-3 or analog reference voltage
RA4/TOCKI clock input to Timer-0
RA5/ /AN4
can be used for analog input 4 or slave select for the synchronized serial port.
Port-E pins (Alternate functions)

RE0/

/AN5 - can be used as analog input-5

RE1/

/AN6 - can be used as analog input-6

RE2/

/AN7 - can be used as analog input-7

PIC microcontroller has internal sample and hold circuit. The input signal should be stable across the capacitor
before the conversion is initiated.

Fig 23.2 Sample and Hold Circuit

After waiting for the sampling time, a conversion can be initiated. The ADC Circuit will open the sampling switch
and carry out the conversion of the input voltage as it was at the moment of opening of the switch. Upon
completion of the conversion, the sampling switch is again closed and VHold once again tracks VSource.
Using the A/D Converter

Registers ADCON1, TRISA, and TRISE must be initialized to select the reference voltage and input channels. The
first step selects the ADC clock from among the four choices (f osc/2, fosc/8, fosc/32, and RC). The constraint for
selcting clock frequency is that the ADC clock period must be 1.6micro seconds or greater.
The A/D module has 3registers. These registers are:

A/D result register (ADRES)

A/D control register 0 (ADCON 0)

A/D control register 1 (ADCON 1)

The ADCON0 register, which is shown below, controls the operation of A/D module.

Fig 23.3 ADCON0 register

Bit 7-6 - A/D Clock select bits
ADCS1:ADCS0
00 = fosc/2
01 = fosc/8
10 = fosc/32
11 = fRC- clock derived from an internal RC oscillator
Bit 5-3 - A/D Channel Select
CHS2:CHS0
000 - Channel 0 - AN0
001 - Channel 1 - AN1
010 - Channel 2 - AN2
011 - Channel 3 - AN3
100 - Channel 4 - AN4
101 - Channel 5 - AN5
110 - Channel 6 - AN6
111 - Channel 7 - AN7
Bit 2 - A/D conversion status bit

GO /
if A/D Converter is enabled (ie. ADON = 1) then
If GO /

= 1, A/D conversion is in progress

(setting this bit starts A/D conversion)

If GO /

= 0, A/D conversion is not in progress

(This bit is automatically cleared by hardware when A/D conversion is complete)
Bit1 - Unimplemented
Bit 0 - ADON: A/D On bit

1.

A/D Converter module is ON

2. A/D Converter module is OFF

ADCON1 Register

This register specifies the analog inputs

Fig 23.4 ADCON1 register

PCFG2:PCFG0

RA0

RA1

RA2

RA5

RA3

RE0

RE1

RE2

VREF

000

VDD

001

VREF

RA3

010

VDD

011

VREF

RA3

100

VDD

101

VREF

RA3

11X

Fig 23.5 PCFG2:PCFG0 = A/D Port configuration control bits

A
D = Digital I/O

Analog

input

Fig 23.6 Schematic diagram of A/D convertor analog inputs and reference voltage
Steps for A/D conversion

1.

2.

Configure A/D module

Configure analog inputs/voltage reference and digital I/O (ADCON1)

Select A/D Channel (ADCON0)

Select A/D Conversion Clock (ADCON0)

Turn on A/D Module (ADCON0)

Configure A/D Interrupt (Optional)

Clear ADIF bit in PIR1 register

Set ADIE bit in PIE1 register

Set GIE bit

3.

Wait for required acquisition time

4.

Start Conversion - set GO/

5.

Wait for A/D conversion to complete, by either polling GO/

6.

Read A/D result registers (ADRES). Clear ADIF if required.

Example
A/D conversion with interrupt

bit (ADCON0)

bit or by waiting for the A/D interrupt

Program

org 000H
goto Mainline
org 020H
bsf STATUS, RP0
;
Select Bank 1
clrf ADCON 1
;
Configure A/D inputs
bsf PIE1, ADIE
;
Enable A/D interrupt
bcf STATUS, RP0
;
Select Bank 0
movlw 081H
;
Select fosc/32, channel 0, A/D on
movwf ADCON0
bcf
PIR1, ADIF
bsf
INTCON, PEIE
;
Enable peripheral and global interrupt bits
bsf
INTCON, GIE
;
interrupt bits
; Ensure that the required sampling time of the selected input channel has been elapsed.
; Then conversion may be started.
; bsf ADCON0, GO
; Start A/D conversion.
; ADIF bit will be set and GO/
; bit is cleared upon completion of A/D conversion.
Interrupt Service Routine
Org
Movf ADRES, W ; Result of A/D conversion in W
Consideration of Sampling Time

004H

When a channel is selected (writing to ADCON0), the switch 'SW' in Fig 23.8 is closed, changing C HOLD to VSource .
When A/D conversion is started (setting Go bit in ADCON0), SW is opened. The time from the closure of 'SW' till
the voltage across CHOLD (Vo) reaches VSource is the minimum sampling time Ts . The actual sampling time can be
higher
than
Ts .
The graph between Ts and source resistance RSource is shown in Fig 23.7.+

Fig 23.7 Relation between sampling time and source resistance

Fig 23.8 Sampling circuit in the PIC C

Rss is the resistance of the sampling switch 'SW' and CHold is the charge holding capacitance. CHold is nearly 50pF.
RSource is the impedance of the external analog source Vsource. Once the switch 'SW' is closed, the capacitor
Chold takes some time to charge up. This time it is called the sampling time (T s). This time varies linearly with
RSource as shown. The recommended value of impedance of the external analog source, Vsource, is less than
10k.
The circuit in Fig 23.8 is a first order RC circuit. When SW is closed, Vo varies as shown in Fig 23.9.

Fig 23.9

From Fig 23.9,

Ts = 5
= 5 ( Rsource + Rss) CHOLD
= 5 Rss CHOLD + 5 Rsource CHOLD
Hence sampling time Ts varies linearly with RSource as shown in Fig 23.7.

Sensor Interfacing.