To Study and Simulate the Electrical Characteristics of Silicon Nanowire

Transistors (SNWTs) in Analog and Digital Circuits

Saurabh Chaubey, ID no - 4877517
Final Project Report, Semiconductor Properties and Devices II, EE-5164
AbstractThis work explores the present day advancement in
the field of Silicon Nanowire Transistors (SNWTs) for sub 10nm
channel length. We show that these types of structures solve the
fundamental problem of short channel devices i.e gate control.
These structures enhance the gate control by having Gate All
Around (GAA) strategy with ultra low parasitics. We will show
that these structures will have an impressive Ion /Iof f . We will
study the electrical characteristics of the SNWTs and related
exotic structures. Also for the first time, I am trying to use
the models developed by the latest works [1-4] of these devices
in order to apply on basic analog and digital building blocks.
I present a basic and simple verilog-A framework to predict
the future performances (in coming years) of analog and digital
circuits based on these SNWTs. I am also exploring the impact of
parasitic capacitances and resistances on the circuit performances
using these devices. According to the SPICE circuit simulations
(of the verilog-A models), we find that the basic SNWT can have
an instrisic DC gain of 30.08 dB and bandwidth of 11 GHz
with a Gain-Bandwidth product of 347 GHz. The Ft(frequency
at which the transistor ceases to be an amplifier) is found to be
1.18 THz. The digital delay (of a minimum size inverter) is 2.3
pSec. It should be noted that the models used in SPICE for these
simulations are abstract and simplified versions of the detailed
model developed in literature like of those [2-5] and are of very
basic and just indicative of the performance trends.

(a)

KeywordsSilicon Nanowire Transistors, Gate All Around,

Gate control, Analog Circuit Performances, Digital Circuit Performances, Process Mismatch, Parasitic

I.

I NTRODUCTION

Conventional scaling of gate oxide thickness, source/drain

extension (SDE), junction depths, and gate lengths have
enabled MOS gate dimensions to be reduced from 10mm
in the 1970s to a present day size of 0.1mm. To enable
transistor scaling into the 21st century, new solutions such
as high dielectric constant materials for gate insulation and
shallow, ultra low resistivity junctions need to be developed.
We know that traditional SiO2 gate dielectrics will reach
fundamental leakage limits, due to tunneling, for an effective
electrical thickness below 2.3 nm. Experimental data and
simulations were used by researchers to show that although
conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results
in performance degradation. Because of these limits, it will
not be possible to further improve short channel effects. This
will result in either unacceptable off-state leakage currents or
strongly degraded device performance for gate lengths below
100nm. MOS transistor limits will be reached for 0.13um
process technologies in production during 2002. Because of
these problems, new solutions will need to be developed for
continued transistor scaling. The fundamental problems and
issues of MOSFETs beyond sub-10nm channel length are the
electrostatic limits, source-to-drain tunneling, carrier mobility

(b)
Fig. 1. (a) International Technology Roadmap for Semiconductors (ITRS)
based technology trends for scaling of MOSFETs for higher performances.
(b) Conventional scaling of MOSFETs till 2011 without use of exotic FET
structures and using standard CMOS processes.

degradation, process variations, and static leakage. The trend

towards ultra-short gate length MOSFETs requires a more and
more effective control of the channel by the gate leading to
new device architecture. Diverse device structures have been
recently proposed and explored, and have found better characteristics than that of single gate metal oxide semiconductor
field effect transistors (MOSFETs). For example, the double
gate MOSFETs can suppress the short-channel effects (SCEs)
and have high transconductance and ideal subthreshold swing
(SS). In order to further lower the SCEs, promising device
structure the so-called surrounding-gate nanowire FinFET were
fabricated and demonstrated fascinating device characteristic in
recent literatures. However, these structures face difficulties in
fabrication with advanced fabrication processes.
Multi-gate MOSFETs based on the concept of volume
inversion are widely recognized as one of the most promising

Cross-section of Modern exotic FET structure cadidates for sub 10nm

Gate-Metal

(a)

(b)

(c)

Channel-Silicon

(d)

(e)

(f)

Fig. 2. (a) Early Intel FINFEts (b) Trigate (c) Omega-Gate (d) Pi- Gate (e)
Gate All Around (GAA) (d) Crosssection of Nanowire FET (SNWTs)

solutions for meeting the ITRS roadmap requirements. A wide

variety of multi-gate architectures, including Double-Gate
(DG), Gate-All-Around (GAA), Pi-FET and Fin Field-Effect
Transistors (FinFETs), rectangular or cylindrical nanowire
MOSFETs have been proposed in common academic/scientific
literatures. In all cases, these structures exhibit a superior
control of short channel effects resulting from an exceptional
electrostatic coupling between the conduction channel and the
surrounding gate electrode. The nanowire (NW) transistors
can be seen as the ultimate integration of the innovative
nanodevices and is one of the candidates which have gained
significant attention from both the device and circuit developers because of its potential for building highly dense
and high performance electronic circuits. Recent advances in
nanoscale fabrication techniques have shown that semiconductor nanowires may become the candidate for next generation
technologies. Si and Ge nanowire transistors are also important
because of their compatibility with the CMOS technology.
Fig.1 shows the the advancements in conventional MOSFET designs till 2001-2012. Fig.1 (a) shows the International
Technology Roadmap for Semiconductors (ITRS) based technology trends for scaling of MOSFETs for higher performances. ITRS predicts the future of industries technology for
commercial purposes. From this, we can see that the industry
is expected to use MOSFETs of channel lengths of 14nm by
the end of this year (2016). Also it predicts that by year 2020
commercial requirements will be of sub-10nm MOSFETs. So
the research in the field these exotic sub 10nm devices is
very much needed. Fig 1(b) shows some the latest technology
advancements to the present day from Intel using almost
standard CMOS processes and convectional FET geometries.
We will begin by reviewing the present and popular candidates for sub-10 nm transistors. We will explore the pros and
cons of each of them. After the literature survey we will move
towards the structural details of the GAA based nano-wire
SNWTs in section III. We will see the latest research work in
the field of GAA fabrication, transport mechanism, parasitics,
noise and variability. Then we will move the abstraction of
the equations developed in earlier sections in terms of verilogA modelling. We simulated the SNWTs in both analog and
digital sub-blocks. Using the simulations I tried to predict the
circuit performance of the conventional blocks in future (when
SNWTs will be used commercially).

Fig. 3. Various design issues with GAA based SNWTs. We will discuss
carrier transport, Parasitic,Variability and mismatch. Rest of them are
also important but not convered in this report. Detail are taken from [13]

Fig. 4. 3-D illustration of single gate-wire SNWT with source and drain
extensions. It can be seen that charge transport can be modelled as a ballastic
charge transport

II.

L ITERATURE S URVEY AND C OMPARISON OF

CANDIDATE STRUCTURES

Fig. 2 presents different possible candidates for short

channel MOSFETs in near future. Fig.2(a) represents the
convectional intel FINFET developed in 2008-09. This has
dual gates on the sides of the channel. Devices based this
structures are being commercially manufactures in technology
nodes of TSMC 28nm and INTEL 22nm. Fig.2(b) shows a
slight variation of FINFET called tri-gate having three gate
(along the tree sides). This has a better Gate control than
conventional FINFETs. Fig.2(c)-(d) represents the omega and
pi structures to have even better gate control and less parasitic
[6]. Finally Fig.2(d-e) show the GAA strategy for Nanowire
MOSFETs (SNWTs). Fig.3 shows the various design issues
with a modern small channel SNWTs. In the next section,
(literature survey section) we will explore each of these issues.
A. Transport Mechanism
The basic carrier transport mechanism of the nano-wire
SNWTs is fundamentally different than FINFETs. According
to [7] we see the mechanism for the channel formed under the
GAA (Gate All Around) is ballistic transport behaviour. Fig 4
shows the illustration.
As devices are scaled to the nano-scale dimension, ballistic
transport of carriers becomes increasingly important. It is

Fig. 5.

Ballistic transport mechanism as explained in [7]

Fig. 6.

possible that the channel length is shorter than the mean

free path such that the channel carriers will not suffer from
any scattering events. However, in the quasi-ballistic regime
(LG=(10nm,100nm)) the channel length would be larger than
the mean-free-path, and the possibility of ballistic-transport for
carriers will decrease. Therefore, in this regime, conventional
transport mechanism also plays a major role. The drain current
for a device is governed by:
IDsat = Qef f .Vinj .Bsat .(VGS VT H )

(1)

where Vinj and Bsat are the injection velocity and ballistic
efficiency. Eq.(1) describes how fast carriers are injected from
the source-Vinj, and how efficiently carriers will be transported
through the channel-Bsat. The more the carriers are reflected,
e.g., rc, the lower the Bsat is, as shown in Fig. 4, where rc
is the reflection coefficient, and the correlation between Bsat
and rc can be given by as per texts [9-10] :
Bsat =

(1 rc )
(1 + rc )

(2)

In this work, we use a simple yet accurate approach VD,sat

method based on velocity saturation concept. From VD,sat
method as indicated in [11], Bsat can be expressed by a
compact form,
Bsat,q =

1 VD,sat
(VGS VT H )

(3)

in which Bsat,q can be uniquely determined from VD,sat of

the ID-VDS curves. Bsat,q is treated as Bsat determined by
VD.sat method to distinguish it from Bsat extracted by TDM.
I infer from work done in [6,9,10,11], that both TDM and the
new VD,sat methods are useful for the devices for channel
lengths lesser than 40nm. Summary of the equations used for
ID vs VD are presented in Fig.4 right-hand side.
B. Parasitic of the device
Use-fullness of any device in a circuit largely depends
on the intrinsic parasitics of the device. As we will see
later both analog and digital circuit parameters are largely
defined by the intrinsic device parasitic. Literature work done
in [12] shows the nature of important parasitic capacitance and
resistances of the GAA based SNWTs. Also Fig.6 illustrates
the lumped model for parasitic capacitances in a SWNT device.
As schematically shown in Fig. 6, the parasitic capacitances

Parasitic breakdown of different structures in a SNWT.

of SNWTs consist of inner-fringing capacitance (Cinner,f

), overlap capacitance (Cov), and outer-fringing capacitance
(Couter,f ) and can be expressed as Cparasitic = Couter,f + Cov
+ Cinner,f . Outer fringing capacitance (Couter,f ) comprises
the capacitances between the gate and the raised source/drain
and between the gate and the SDE (Source-Drain extension)
region. Overlap capacitance (Cov) is the capacitance between
the gate and the SDE regions under the gate. If Cov and
Couter,f are absent, Cinner,f manifests itself as the residual
capacitance component when the transistor is switched off,
and it can be screened by the inversion layer when increasing
the gate voltage. Up to 40of Cinner,f /(Cint + Cinner,f ) is
observed when dw = 10 nm. It should be noted here that
transient response of SNWTs operating at moderate inversion
region will be degraded by the large inner-fringing capacitance.
Outer-fringing capacitance is the main component of the
parasitic capacitances and is essentially important in the
nanowire structures. It is observed that the proportion is up
to about 90% when Hg/Lg = 2 (where Hg is height of the
nano-wire gate). This can be mainly attributed to the fact that
the diameter of the silicon nanowire is only several nanometers
and that the length of the SDE regions cannot be very large in
order to avoid large parasitic resistance. As a result, the outerfringing capacitance may be even several times larger than
the intrinsic capacitance. These high parasitic capacitances are
unique for the nanowire structures and may offset the high
current drivability of the SNWTs leading to degraded transient
response characteristics.
Parasitic resistance in SNWTs mainly consists of the resistance of the ultranarrow SDE (extensions) regions and the
contact resistance. According to the ITRS, the source/drain
parasitic contact series resistance of 150 ohm m for doublegate (DG) MOSFETs with 13-nm effective gate length is
specified. For multigate structures like SNWTs, transistors are
usually designed with several fingers to obtain large enough
current, and sources/drains are connected to share contacts.
This reduces the impact of the contact resistance on each
nanowire. If ten nanowires are connected in parallel, contact
resistance of up to 1500 may be possible for each nanowire.
Therefore, the parasitic contact resistance of a single SNWT
ranges from 0 to 2000 ohm in the simulation. It is observed that
the contact resistance only slightly influences either the gm or
the ft at low gate overdrive voltage (0.1 V). The degradation
is still less than 5% even when the contact resistance is 2000
ohm. This is probably due to the fact that the contact resistance

Ft is freq at which
(Iout/Iin)VD=0 =1
Iout Ft=Gm/(2*pi*CG)

Vout
Vin

RDS =

dIDS
dt

-1

Intrinsic Gain = GmRDS

Gm:Transconductance

M3

M4

IInd Gain Stage

Iin

Intrinsic drain
capacitor, CD

Current Biasing Resistor

Intrinsic Gate
capacitor, CG

M1

M2

Fig. 7. Definition of basic analog parameters Transition frequency and low

frequency gain to be calculated/simulated from the modified BSIM-CMG
models with ballastic charge transport.
M5

is small compared with that induced by the ultranarrow SDE

regions, which are often on the order of 104 ohm [9-12].
Therefore, the contact resistance requirements can be relaxed
for SNWTs, and device optimization to reduce the parasitic
resistance should concentrate on the SDE regions.

INPUT Differential Stage

Fig. 8. Circuit test bench of a two stage operational amplifier circuit in

Cadence VIRTUOSO. The circuit was simulated with verilog-A model files
of the transistors. The models of the transistors are of SNFTs based. The
circuit has a VDD=1.0V and simulated at T=27C.

C. Other issues- noise and mismatch

From a circuit designer prospective, knowing the noise
contribution and device mismatch profile is very important.
Unfortunately, there has been very few investigations done in
this regard. Works shown in [11-12] touch upon the basic noise
and variability issues. R. Wang and others showed [12] the
fundamental reasons for the variability in the SNWTs. These
topics are out of scope of this report. For our simulations, I
neglected the process mismatch and noise contributions.
III.

C IRCUIT S IMULATIONS

Once we have understood the basic functioning of SNWTs,

I applied these basic knowledge to adapt the existing BSIM
MOS models in order to develop the basic verilog-A models
which can be simulated in SPICE soft-wares. For this work
I modified BSIM-CMG models [14]. We know that BSIM
models are the best MOFET models having all the required parameters and empirical relations of a typical MOSFET system.
Moreover, these models are free for academic purposes. Using
the work suggested in section II.A (Transport Mechanism), I
made the changes in the saturation condition of the SNWTs
in the existing BSIM-CMG models.
Main ID,SAT equations used to change the models are as
follows:
(1 rc )
ID,sat = Cox .W.vT
(4)
(1 + rc ).(VGS VT )
Also, the value of rC is as follows:
rC0
rC =
1 + 2.E0 /vT

(5)

Vin
Vin

CD

Vout

Vout

CD

CG

CD
CD

CD

CG
Inverter

CD
Fan-Out of 4

Fig. 9. Basic definitions of the digital circuit parameters. Digital delay is

defined as the Fan-out of 4 delay also known as FO4 delay. This means
the delay occured when a unit sized inverter drives four such inverters at the
output

performances, low frequency (DC) gain and 3-dB frequency

are the most important. These two values set the gainbandwidth product of an amplifying stage.
Fig.8 shows the OTA circuit simulated in CadenceVIRTUOSO tool. The op-amp circuit is composed of two
stages. The first stage is the 5-Transistor based OTA followed
by class-A P-type common source stage. M1.M2 are the input
transistors while M5 is the biasing transistor. By basic analog
circuit theory we know that the parasitics of devices M1,M2
determine the dominant pole of this system.
Fig.9 shows the definition of the digital circuit parameters.
In order to complete the circuit performance metric we designed an inverter from the SNWTs as shown in Fig.9. Then
as shown in Fig.9, we calculated the fan-out of 4 delay. In
standard digital processes fan-out 4 delay represent an average
generic delay unit.

A. Analog circuit simulations

Fig.7 shows the basic analog circuit parameters. Fig.7 (left)
shows the Ft (transition frequency) of an device. FT is defined
as the frequency at which the current gain is unity. Therefore
FT is the frequency at which the MOS ceases to act as an
amplifier and acts as an attenuator.
I used the circuit parameters defined in BSIM files and
equations (6) and (7) to simulate both analog and digital
blocks. Among all the important parameters for analog circuit

Table I summarizes the simulated circuit parameters for the

SNWTs. We observe that RDS,ON = 620ohm/um of the gate
wire radius. The DC gain of a single stage is around 30.08 dB
with gain-bandwidth product = 347 GHz. Also, simulation of
digital circuits reveals the power delay product as 4.56 uW-pS.
It should be noted that the electrical characteristics in
existing technology like that of 65nm process are as shown
in Tablew II

[3]

30.08 dB
3dB=11GHz

Low frequency gain (dB)

10

[4]

GBW=341GHz

[5]

10

[6]

[7]

-1

10

10

10

10

10

[8]

Frequency (Hz)
Fig. 10. Bode plot of the simulated OTA comprised of SNWTs. The DCgain is 30.08 dB and the dominant pole is at 11.01 GHz.

(Table-I: Simulated circuit parameters SNWTs)

Simulated parameters
Value
RDS,on
620 ohm/um-radius
DC-Gain
30dB
FT (transition frequency)
1.18 THz
Gain Bandwidth Product
347 GHz
Digital Delay
2.34 pSec
Power delay product
4.56 uW-pS
(Table-II: 65nm- circuit parameters)
Simulated parameters
Value
RDS,on
1610 ohm/um-radius
DC-Gain
26dB
FT (transition frequency)
183 GHz
Gain Bandwidth Product
28 GHz
Digital Delay
12.04 pSec
Power delay product
12.35 uW-pS
Now we can easily see the trends in SNWTs as compared
to the conventional 65nm BULK process. SNWTs have better
speed and lower power.
IV.

C ONCLUSION

We investigated the structure and performance details of

SNWTs based on verilog-A modelling. This work explores
the present day advancement in the field of Silicon Nanowire
Transistors (SNWTs) for sub 10nm channel length. We show
that these types of structures solve the fundamental problem of
short channel devices i.e gate control. These structures enhance
the gate control by having Gate All Around (GAA) strategy
with ultra low parasitics.
R EFERENCES
[1]

[2]

N. Singh et al., High-performance fully depleted silicon nanowire

(diameter /spl les/ 5 nm) gate-all-around CMOS devices, in IEEE
Electron Device Letters, vol. 27, no. 5, pp. 383-386, May 2006.
Jing Wang, A. Rahman, A. Ghosh, G. Klimeck and M. Lundstrom, On
the validity of the parabolic effective-mass approximation for the I-V
calculation of silicon nanowire transistors, in IEEE Transactions on
Electron Devices, vol. 52, no. 7, pp. 1589-1595, July 2005.

[9]
[10]
[11]
[12]

[13]

[14]

A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak and

K. De Meyer, Analysis of the parasitic S/D resistance in multiple-gate
FETs, in IEEE Transactions on Electron Devices, vol. 52, no. 6, pp.
1132-1140, June 2005.
Sung Dae Suk et al., High performance 5nm radius Twin Silicon
Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability, IEEE InternationalElectron Devices Meeting,
2005. IEDM Technical Digest., Washington, DC, 2005
S. Mittal et al., Epitaxially Defined FinFET: Variability Resistant
and High-Performance Technology, in IEEE Transactions on Electron
Devices, vol. 61, no. 8, pp. 2711-2718, Aug. 2014.
T. Park et al., PMOS body-tied FinFET (Omega MOSFET) characteristics, Device Research Conference, 2003, Salt Lake City, UT, USA,
2003, pp. 33-34.
J. J. Gu, Y. Q. Liu, Y. Q. Wu, R. Colby, R. G. Gordon and P. D.
Ye, First experimental demonstration of gate-all-around IIIV MOSFETs
by top-down approach, Electron Devices Meeting (IEDM), 2011 IEEE
International, Washington,
R. Wang et al., Experimental Investigations on Carrier Transport in Si
Nanowire Transistors: Ballistic Efficiency and Apparent Mobility, in
IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 2960-2967,
Nov. 2008.
M. Lundstrom, Elementary scattering theory of the Si MOSFET, in
IEEE Electron Device Letters, vol. 18, no. 7, pp. 361-363, July 1997.
S.S. Chung et al., IEEE Silicon Nanoelectronics Workshop, p. 19, 2007.
Y. Yaur et al., Fundamentals of Modern VLSI Devices, 1998.
J. Zhuge, R. Wang, R. Huang, X. Zhang and Y. Wang, Investigation
of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications, in IEEE Transactions on Electron Devices,
vol. 55, no. 8, pp. 2142-2147, Aug. 2008.
R. Huang et al., Characterization and analysis of gate-all-around Si
nanowire transistors for extreme scaling, 2011 IEEE Custom Integrated
Circuits Conference (CICC), San Jose, CA, 2011, pp. 1-8.
http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG

ADAPTED VERILOG-A CODE FOR THIS PROJECT

//Modified BSIM-CMG code taking care of

ballastic transport mechansim of
// SNWTs as described in this project.
//"ORIGINAL CODE" was develoed by BSIM lab,
University of Berkely, adapted by me for 1-D
quasi ballastic transport

electrical si, di;

`ifdef __NQSMOD1__
electrical gi;
`endif

`ifdef __NQSMOD2__
electrical q;

// EE-5164 Final Project Code

//This has been taken as the blue-print for our
verilog-A model development in this report
// Some parameterts have been added and
deleted from this coed.
`define __OPINFO__

`endif

`ifdef __RGATEMOD__
electrical ge;
`endif

`define __DEBUG__
`define __SHMOD__

`ifdef __SHMOD__

`define __RDSMOD__

thermal t;

//`define __NQSMOD1__

branch (t) rth_branch;

`define __NQSMOD2__

branch (t) ith_branch;

`define __RGATEMOD__
//`define __TNOIMOD1__

`else
thermal t;
`endif

`include "common_defs.include"
`include "bsimcmg_cfringe.include"

// Internal node controlled by Correlated

Thermal Noise Switch
`ifdef __TNOIMOD1__
electrical N;

module bsimcmg(d, g, s, e, t);

inout

`endif

g, d, s, e, t;

electrical g, d, s, e;

`include "bsimcmg_body.include"

// Mathematical functions
//`define SINH(x)
endmodule

`define COSH(x)

(0.5 * (lexp(x) + lexp(-(x))))

//`define TANH(x)
((lexp(x) - lexp(-(x))) /
(lexp(x) + lexp(-(x))))

// Numerical Constants
`define EXPL_THRESHOLD

`define COT(x)
((x)>=`M_PI/2 ? 0 : ((x)<=`M_PI/2 ? 0 : 1.0/tan(x)))

80.0

`define MAX_EXPL

5.540622384e34

`define MIN_EXPL

1.804851387e-35

`define N_MINLOG

1.0e-38

`define MEXPQM

`define DELTA_1

0.02

`define DELTA_ASYMM

// Junction capacitance
//ex:(ves_jct, Czbs, PBS_t, SBS, MJS, MJS2,
Qes1)
`define BSIM6JunctnCap(vex, Cz, PB, SJ, MJ,
MJ2, Qej)
\

0.04

`define CONSTCtoK
`define REFTEMP
degrees C */

(0.5 * (lexp(x) - lexp(-(x))))

begin

(273.15)

if (Cz > 0.0) begin

(300.15) /* 27

T1 = vex / PB;

if (T1 < 0.9) begin

if (SJ > 0.0) begin /*second-step
junction*/ \

// Model type definitions

`define ntype

`define ptype

vec = PB * (1.0 - lexp((1.0 / MJ) *

lln(1.0/SJ))); /*Switch over voltage*/\
pb2 = PB * SJ * MJ2 / MJ / lexp(- (1.0
+ MJ) * lln(1.0 - vec / PB)); /*PB for second
doping region*/\

// Physical Constants
`define q
`define EPS0

1.60219e-19
8.8542e-12

`define HBAR

1.05457e-34

`define MEL

9.11e-31

`define KboQ
degree

8.617087e-5

// Coul

if (vex > vec) begin

\

// F/m
// Joule-sec
// kg

arg = 1.0 - T1;

\
sqrt(arg);

// Joule /
lln(arg));

if (MJ == 0.5) sarg = 1.0 /

\
else
\

sarg = lexp(-MJ *

Qej = PB * Cz * (1.0 - arg * sarg) /

(1.0 - MJ); \

end else begin /*vex/PB>=0.9*/

\

end else begin /*vex < vec*/

\

T2 = lexp(-MJ * lln(0.1));
\

arg = 1.0 - vec / PB;

\

T3 = 1.0 / (1.0-MJ);
\

if (MJ == 0.5) sarg = 1.0 /

\

sqrt(arg);

else
\

lln(arg));

T4 = T2 * (T1 - 1.0) * (5.0 * MJ * (T11.0) + (1.0 + MJ) );

\

sarg = lexp(-MJ *
* T2 );

Qec = PB * Cz * (1.0 - arg * sarg) /

(1.0 - MJ); \

Qej = PB * Cz * (T4 + T5); /*Quadratic

equation for Qej when vex/PB>=0.9*/\

arg = 1.0 - (vex - vec) / pb2;

\

end
\

if (MJ2 == 0.5) sarg = 1.0 /

\

sqrt(arg);

else
lln(arg));

T5 = T3 * (1.0 - 0.05 * MJ * (1.0 + MJ)

\

end else begin

\

sarg = lexp(-MJ2 *

Qej = 0.0;
\

Qej = Qec + SJ * pb2 * Cz * (1.0 arg * sarg) / (1.0 - MJ2); \

end
\

end

end

\
end else begin /*single junction*/
\
arg = 1.0 - T1;
\

//
// Macros for the model/instance parameters
//

if (MJ == 0.5) sarg = 1.0 / sqrt(arg);

\

// MPRxx model parameter real

// MPIxx model parameter integer

else

sarg = lexp(-MJ * lln(arg));

// IPRxx instance parameter real

Qej = PB * Cz * (1.0 - arg * sarg) /

(1.0 - MJ);
\

// IPIxx instance parameter integer

end
\

//

||

// cc closed lower bound, closed upper

bound

// oo open lower bound, open upper

bound
// co closed lower bound, open upper
bound
// oc open lower bound, closed upper
bound
// cz closed lower bound=0, open upper
bound=inf
// oz open lower bound=0, open upper
bound=inf
//

nb no bounds

//

ex no bounds with exclude

// sw switch(integer only, values 0=false

and 1=true)
// ty switch(integer only, values -1=p-type
and +1=n-type)

`define MPRcc(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
real nam=def from[lwr:upr] ;
`define MPRoo(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
real nam=def from(lwr:upr) ;
`define MPRco(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
real nam=def from[lwr:upr) ;
`define MPRoc(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
real nam=def from(lwr:upr] ;
`define MPRcz(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
real nam=def from[ 0:inf);
`define MPRoz(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
real nam=def from( 0:inf);

//
// IPM instance parameter
mFactor(multiplicity, implicit for LRM2.2)
// OPP operating point parameter, includes
units and description for printing
//
`define ALIAS(alias,paramName) aliasparam
alias = paramName ;
`define OPP(nam,uni,des)
desc=des*)
real nam ;

(*units=uni,

`define MPRnb(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
real nam=def ;
`define MPRex(nam,def,uni,exc, des)
(*units=uni,
desc=des*) parameter
real nam=def exclude exc ;

`define MPInb(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
integer nam=def ;
`define MPIex(nam,def,uni,exc, des)
(*units=uni,
desc=des*) parameter
integer nam=def exclude exc ;
`define MPIcc(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
integer nam=def from[lwr:upr] ;
`define MPIoo(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
integer nam=def from(lwr:upr) ;
`define MPIco(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
integer nam=def from[lwr:upr) ;
`define MPIoc(nam,def,uni,lwr,upr,des)
(*units=uni,
desc=des*) parameter
integer nam=def from(lwr:upr] ;

`define MPIcz(nam,def,uni,
des) (*units=uni,
desc=des*) parameter integer nam=def from[
0:inf);
`define MPIoz(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
integer nam=def from( 0:inf);

`define IPRoz(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter real
nam=def from( 0:inf);

`define IPInb(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter integer
nam=def ;

`define MPIsw(nam,def,uni,
des)
(*units=uni,
desc=des*) parameter
integer nam=def from[ 0: 1] ;

`define IPIex(nam,def,uni,exc, des)

(*units=uni, type="instance", desc=des*)
parameter integer nam=def exclude exc ;

`define MPIty(nam,def,uni,
des) (*units=uni,
desc=des*) parameter integer nam=def from[ 1: 1] exclude 0 ;

`define IPIcc(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter integer nam=def from[lwr:upr] ;

`define IPRnb(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter real
nam=def ;
`define IPRex(nam,def,uni,exc, des)
(*units=uni, type="instance", desc=des*)
parameter real nam=def exclude exc ;
`define IPRcc(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter real nam=def from[lwr:upr] ;
`define IPRoo(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter real nam=def from(lwr:upr) ;
`define IPRco(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter real nam=def from[lwr:upr) ;
`define IPRoc(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter real nam=def from(lwr:upr] ;
`define IPRcz(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter real
nam=def from[ 0:inf);

`define IPIoo(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter integer nam=def from(lwr:upr) ;
`define IPIco(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter integer nam=def from[lwr:upr) ;
`define IPIoc(nam,def,uni,lwr,upr,des)
(*units=uni, type="instance", desc=des*)
parameter integer nam=def from(lwr:upr] ;
`define IPIcz(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter integer
nam=def from[ 0:inf);
`define IPIoz(nam,def,uni,
des) (*units=uni,
type="instance", desc=des*) parameter integer
nam=def from( 0:inf);

`ifdef EXPLICIT_MFACTOR
`define IPM
(*units="" ,
type="instance", desc="multiplicity factor"*)
parameter real m=1.0 from(0.0:inf) ;
`define MFACTOR_USE m
`else //
`define IPM

`define MFACTOR_USE 1.0

`endif

Rdrain = rdstemp * (RDrainGeo +

(RDWMIN_i + T5 * T0) * WeffWRFactor);
end
0: begin

// Source-Drain Resistance Model

case(RDSMOD)
1: begin
Rdsi

= 0.0;

Dr

= 1.0;

Rsource = RSourceGeo;
Rdrain = RDrainGeo;
T4

= 1.0 + PRWGS_i * qia;

T1

= 1.0 / T4;

T0

= 0.5 * (T1 + sqrt(T1 * T1 + 0.01));

Rdsi = rdstemp * (RDSWMIN_i + RDSW_i

* T0) * WeffWRFactor;
T2

= vgs_noswap - vfbsd;

T3

= sqrt(T2 * T2 + 1.0e-1);

Dr
= 1.0 + (NFINtotal) * beta *
ids0_ov_dqi / (Dmob * Dvsat) * Rdsi;

vgs_eff = 0.5 * (T2 + T3);

end

T4

= 1.0 + PRWGS_i * vgs_eff;

2: begin

T1

= 1.0 / T4;

T4

= 1.0 + PRWGS_i * qia;

T0

= 0.5 * (T1 + sqrt(T1 * T1 + 0.01));

T1

= 1.0 / T4;

T0

= 0.5 * (T1 + sqrt(T1 * T1 + 0.01));

T5
= RSW_i * (1.0 + RSDR_a * lexp(0.5 *
PRSDR * lln(V(si,s) * V(si,s) + 1.0E-6)));
Rsource = rdstemp * (RSourceGeo +
(RSWMIN_i + T5 * T0) * WeffWRFactor);

T2

= vgd_noswap - vfbsd;

T3

= sqrt(T2 * T2 + 1.0e-1);

vgd_eff = 0.5 * (T2 + T3);

T4

= 1.0 + PRWGD_i * vgd_eff;

T1

= 1.0 / T4;

T0

= 0.5 * (T1 + sqrt(T1 * T1 + 0.01));

T5
= RDW_i * (1.0 + RDDR_a * lexp(0.5
* PRDDR * lln(V(di,d) * V(di,d) + 1.0E-6)));

Rdsi = rdstemp * (RSourceGeo +

RDrainGeo + RDSWMIN_i + RDSW_i * T0) *
WeffWRFactor;
Dr
= 1.0 + (NFINtotal) * beta *
ids0_ov_dqi / (Dmob * Dvsat) * Rdsi;
Rsource = 0.0;
Rdrain = 0.0;
end
endcase