Tms320f2812 Data Manual

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

Digital Signal Processors
Data Manual
Literature Number: SPRS174J

April 2001 - Revised December 2003
This document contains information on

products in more than one phase of
development. The status of each device is
indicated on the page(s) specifying its
electrical characteristics.
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Contents
Contents
Section
1
2
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Terminal Assignments for the GHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Pin Assignments for the PGF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Pin Assignments for the PBK Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Brief Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
C28x CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Memory Bus (Harvard Bus Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Real-Time JTAG and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
External Interface (XINTF) (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
Flash (F281x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7
ROM (C281x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8
M0, M1 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9
L0, L1, H0 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12
Peripheral Interrupt Expansion (PIE) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13
External Interrupts (XINT1, 2, 13, XNMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16
Peripheral Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.18
Peripheral Frames 0, 1, 2 (PFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19
General-Purpose Input/Output (GPIO) Multiplexer . . . . . . . . . . . . . . . . . . . . . . . .
3.2.20
32-Bit CPU-Timers (0, 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.21
Control Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.22
Serial Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
External Interface, XINTF (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
XREVISION Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Loss of Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
External Reference Oscillator Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11
Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12
Low-Power Modes Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS174J
11
12
12
13
14
14
15
16
17
26
27
32
32
33
33
33
33
34
34
34
34
34
35
35
35
36
36
36
36
36
37
37
37
37
37
40
40
42
42
43
46
47
49
50
50
51
51
52
Contents
5
6
7
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1
32-Bit CPU-Timers 0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.1
General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.2
Full-Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.3
Programmable Deadband Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.4
PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.5
Double Update PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.6
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.7
Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.9
External ADC Start-of-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3
Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4
Enhanced Controller Area Network (eCAN) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5
Multichannel Buffered Serial Port (McBSP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.6
Serial Communications Interface (SCI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.7
Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.8
GPIO MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.1
Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320F281x). . . . . . . . . . . . . . . . . . . 87
7.5
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320C281x) . . . . . . . . . . . . . . . . . . 88
7.6
Current Consumption Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.7
Reducing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.8
Power Sequencing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.9
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.10
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.11
General Notes on Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.12
Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.13
Device Clock Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.14
Clock Requirements and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.14.1
Input Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.14.2
Output Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.15
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.16
Low-Power Mode Wakeup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.17
Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.17.1
PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.17.2
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.18
General-Purpose Input/Output (GPIO) - Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.19
General-Purpose Input/Output (GPIO) - Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.20
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.21
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.22
External Interface (XINTF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPRS174J
Contents
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
XINTF Signal Alignment to XCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

External Interface Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
External Interface Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
External Interface Ready-on-Read Timing With One External Wait State . . . . . . . . . . . . . . . . 123
External Interface Ready-on-Write Timing With One External Wait State . . . . . . . . . . . . . . . . 126
XHOLD and XHOLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
XHOLD/XHOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
On-Chip Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.30.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.30.2
Electrical Characteristics Over Recommended Operating Conditions . . . . . . . 132
7.30.3
Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)133
7.30.4
ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.30.5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.30.6
Sequential Sampling Mode (Single-Channel) (SMODE = 0) . . . . . . . . . . . . . . . 135
7.30.7
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) . . . . . . . . . . . . . . 137
7.30.8
Definitions of Specifications and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.31
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.31.1
McBSP Transmit and Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.31.2
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.32
Flash Timing (F281x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.32.1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
8
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8.1
Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8.2
Low-Profile Quad Flatpacks (LQFPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SPRS174J
Figures
List of Figures
Figure
Page
2-1 TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . 14
2-2 TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2-3 TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP
(Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3-2 F2812/C2812 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3-3 F2811/C2811 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-4 F2810/C2810 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3-5 External Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3-6 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3-7 Multiplexing of Interrupts Using the PIE Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3-8 Clock and Reset Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3-9 OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3-10. Recommended Crystal/ Clock Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3-11 Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4-1 CPU-Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4-2 CPU-Timer Interrupts Signals and Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4-3 Event Manager A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4-4 Block Diagram of the F281x and C281x ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4-5 ADC Pin Connections (See Notes A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4-6 eCAN Block Diagram and Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4-7 eCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4-8 McBSP Module With FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4-9 Serial Communications Interface (SCI) Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4-10 Serial Peripheral Interface Module Block Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4-11 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5-1 TMS320x28x Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7-1 F2812/F2811/F2810 Typical Current Consumption (With Peripheral Clocks Enabled) . . . . . . . . . . . . . . . . . 89
7-2 F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence - Option 2 . . . . . . . . . . . . . . . . . . . . . . 91
7-3 Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7-4 Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7-5 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7-6 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7-7 Power-on Reset in Microcomputer Mode (XMP/MC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7-8 Power-on Reset in Microprocessor Mode (XMP/MC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7-9 Warm Reset in Microcomputer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7-10 Effect of Writing Into PLLCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7-11 IDLE Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7-12 STANDBY Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7-13 HALT Wakeup Using XNMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7-14 PWM Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SPRS174J
Figures
7-15 TDIRx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7-16 EVASOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7-17 EVBSOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7-18 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7-19 General-Purpose Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7-20 GPIO Input Qualifier - Example Diagram for QUALPRD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7-21 General-Purpose Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7-22 SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7-23 SPI Master External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7-24 SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7-25 SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7-26 Relationship Between XTIMCLK and SYSCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7-27 Example Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7-28 Example Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7-29 Example Read With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7-30 Example Read With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7-31 Write With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7-32 Write With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7-33 External Interface Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7-34 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7-35 ADC Analog Input Impedance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7-36 ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7-37 Sequential Sampling Mode (Single-Channel) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7-38 Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7-39 McBSP Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7-40 McBSP Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7-41 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8-1 TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8-2 TMS320F2812 and TMS320C2812 176-Pin PGF LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8-3 TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP . . . . . . . . . . . . 149
SPRS174J
Tables
List of Tables
Table
Page
3-1 Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3-2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4-1 Addresses of Flash Sectors in F2812 and F2811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4-2 Addresses of Flash Sectors in F2810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4-3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4-4 Peripheral Frame 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4-7 Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-8 XINTF Configuration and Control Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-9 XREVISION Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-10 PIE Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4-11 PIE Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4-12 External Interrupts Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4-14 PLLCR Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4-15 Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4-16 F281x and C281x Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5-1 CPU-Timers 0, 1, 2 Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5-2 Module and Signal Names for EVA and EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5-3 EVA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5-4 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5-5 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . 66
5-6 CAN Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5-7 McBSP Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5-8 SCI-A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5-9 SCI-B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5-10 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5-11 GPIO Mux Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5-12 GPIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7-1 Typical Current Consumption by Various Peripherals (at 150 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7-2 Recommended Low-Dropout Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7-3 TMS320F281x and TMS320C281x Clock Table and Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7-4 Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-5 XCLKIN Timing Requirements - PLL Bypassed or Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-6 XCLKIN Timing Requirements - PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-7 Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7-9 Reset (XRS) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7-10 IDLE Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7-11 STANDBY Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7-12 HALT Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7-13 PWM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7-14 Timer and Capture Unit Timing Requirements# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7-15 External ADC Start-of-Conversion - EVA - Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7-16 External ADC Start-of-Conversion - EVB - Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPRS174J
Tables
7-17 Interrupt Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7-18 Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7-19 General-Purpose Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7-20 General-Purpose Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7-21 SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7-22 SPI Master Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7-23 SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7-24 SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7-25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse . . . . . . . . . . . . . . . 117
7-26 XINTF Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7-27 External Memory Interface Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7-28 External Memory Interface Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7-29 External Memory Interface Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7-30 External Memory Interface Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7-31 External Memory Interface Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7-32 Synchronous XREADY Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7-33 Asynchronous XREADY Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7-34 External Memory Interface Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7-35 Synchronous XREADY Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7-36 Asynchronous XREADY Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7-37 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 131
7-39 DC Specifications (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7-40 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7-41 ADC Power-Up Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7-42 Sequential Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7-43 Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7-44 McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7-45 McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7-46 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . . . . . . 142
7-47 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . . 142
7-48 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . . . . . 143
7-54 Flash Parameters at 150-MHz SYSCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7-55 Flash/OTP Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7-56 Minimum Required Wait-States at Different Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
8-1 Thermal Resistance Characteristics for 179-GHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8-2 Thermal Resistance Characteristics for 176-PGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8-3 Thermal Resistance Characteristics for 128-PBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPRS174J
10
SPRS174J
Features
Features
D High-Performance Static CMOS Technology
D
D
D
D
D
D
D
- 150 MHz (6.67-ns Cycle Time)

- Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
- 3.3-V Flash Voltage
JTAG Boundary Scan Support
High-Performance 32-Bit CPU
(TMS320C28x)
- 16 x 16 and 32 x 32 MAC Operations
- 16 x 16 Dual MAC
- Harvard Bus Architecture
- Atomic Operations
- Fast Interrupt Response and Processing
- Unified Memory Programming Model
- 4M Linear Program Address Reach
- 4M Linear Data Address Reach
- Code-Efficient (in C/C++ and Assembly)
- TMS320F24x/LF240x Processor Source
Code Compatible
On-Chip Memory
- Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
- ROM Devices: Up to 128K x 16 ROM
- 1K x 16 OTP ROM
- L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)
- H0: 1 Block of 8K x 16 SARAM
- M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
Boot ROM (4K x 16)
- With Software Boot Modes
- Standard Math Tables
External Interface (2812)
- Up to 1M Total Memory
- Programmable Wait States
- Programmable Read/Write Strobe Timing
- Three Individual Chip Selects
Clock and System Control
- Dynamic PLL Ratio Changes Supported
- On-Chip Oscillator
- Watchdog Timer Module
Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
128-Bit Security Key/Lock
- Protects Flash/ROM/OTP and L0/L1
SARAM
- Prevents Firmware Reverse Engineering
D Three 32-Bit CPU-Timers

D Motor Control Peripherals
D
D
D
D
D
D
- Two Event Managers (EVA, EVB)

- Compatible to 240xA Devices
Serial Port Peripherals
- Serial Peripheral Interface (SPI)
- Two Serial Communications Interfaces
(SCIs), Standard UART
- Enhanced Controller Area Network
(eCAN)
- Multichannel Buffered Serial Port
(McBSP) With SPI Mode
12-Bit ADC, 16 Channels
- 2 x 8 Channel Input Multiplexer
- Two Sample-and-Hold
- Single/Simultaneous Conversions
- Fast Conversion Rate: 80 ns/12.5 MSPS
Up to 56 Individually Programmable,
Multiplexed General-Purpose Input / Output
(GPIO) Pins
Advanced Emulation Features
- Analysis and Breakpoint Functions
- Real-Time Debug via Hardware
Development Tools Include
- ANSI C/C++ Compiler/Assembler/Linker
- Supports TMS320C24x/240x
Instructions
- Code Composer Studio IDE
- DSP/BIOS
- JTAG Scan Controllers
[Texas Instruments (TI) or Third-Party]
- Evaluation Modules
- Broad Third-Party Digital Motor Control
Support
Low-Power Modes and Power Savings
- IDLE, STANDBY, HALT Modes Supported
- Disable Individual Peripheral Clocks
Package Options
- 179-Ball MicroStar BGA With External
Memory Interface (GHH) (2812)
- 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
- 128-Pin LQFP Without External Memory
Interface (PBK) (2810, 2811)
Temperature Options:
- A: - 40C to 85C (GHH, PGF, PBK)
- S: - 40C to 125C (GHH, PGF, PBK)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
IEEE Standard 1149.1- 1990, IEEE Standard Test-Access Port
SPRS174J
11
Introduction
Introduction
This section provides a summary of each devices features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812
devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions
for demanding control applications. The functional blocks and the memory maps are described in Section 3,
Functional Overview.
Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810,
F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811, and
TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM
devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and
2812 denotes both F2812 and C2812 devices.
TMS320C28x is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.
12
SPRS174J
Introduction
2.2
Device Summary
Table 3 - 1 provides a summary of each devices features.
Table 3 - 1. Hardware Features
FEATURE
F2810
F2811
F2812
C2810
C2811
C2812
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
6.67 ns
6.67 ns
6.67 ns
6.67 ns
Single-Access RAM (SARAM)

(16-bit word)
18K
18K
18K
18K
18K
18K
3.3-V On-Chip Flash (16-bit word)
64K
128K
128K
On-Chip ROM (16-bit word)
64K
128K
128K
Code Security for

On-Chip Flash/SARAM/OTP/ROM
Yes
Yes
Yes
Yes
Yes
Yes
Boot ROM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
OTP ROM (1K X 16)

External Memory Interface
Event Managers A and B
(EVA and EVB)
Yes
Yes
Yes
Yes
Yes
Yes
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
General-Purpose (GP) Timers
Compare (CMP)/PWM
16
16
16
16
16
16
Capture (CAP)/QEP Channels
6/2
6/2
6/2
6/2
6/2
6/2
Watchdog Timer
Yes
Yes
Yes
Yes
Yes
Yes
12-Bit ADC
Yes
Yes
Yes
Yes
Yes
Yes
16
16
16
16
16
16
Channels
32-Bit CPU Timers
Yes
Yes
Yes
Yes
Yes
Yes
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
CAN
Yes
Yes
Yes
Yes
Yes
Yes
McBSP
Yes
Yes
Yes
Yes
Yes
Yes
Digital I/O Pins (Shared)
56
56
56
56
56
56
External Interrupts
SPI
SCIA, SCIB
Supply Voltage
1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
128-pin PBK
128-pin PBK
179-ball GHH
176-pin PGF
128-pin PBK
128-pin PBK
179-ball GHH
176-pin PGF
A: - 40C to
85C
Yes
Yes
Yes
Yes
Yes
Yes
S: - 40C to
125C
Yes
Yes
Yes
Yes
Yes
Yes
TMS#
TMS#
TMS#
TMX||
TMX||
TMX||
Packaging
Temperature Options
Product Status
The TMS320F2810 and TMS320F2812 Digital Signal Processors Silicon Errata (literature number SPRZ193) has been posted on the Texas
Instruments (TI) website. It will be updated as needed.
On C281x devices, OTP is replaced by a 1K X 16 block of ROM.
S temperature option ( - 40C to 125C) characterization data will be available at TMS.
PRODUCT PREVIEW (PP) information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION (AI) concerns new products in the sampling or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
PRODUCTION DATA (PD) information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
# TMS: Electrical specifications of F2810/11/12 devices are to be considered as advance information for C2810/11/12 devices.
|| TMX: Experimental device that contains information on products in more than one phase of development. The status of each device is indicated
on the page(s) specifying its electrical characteristics and is not necessarily representative of the final devices electrical specifications.
SPRS174J
13
Introduction
2.3
Pin Assignments
Figure 2 - 1 illustrates the ball locations for the 179-ball GHH ball grid array (BGA) package. Figure 2 - 2 shows
the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2 - 3 shows the pin
assignments for the 128-pin PBK LQFP. Table 3 - 2 describes the function(s) of each pin.
2.3.1
Terminal Assignments for the GHH Package

See Table 3 - 2 for a description of each terminals function(s).
XZCS0AND1 PWM8
PWM10
VSS
VDD
CAP6
_QEPI2
XD[8]
VSS
VDD
SPISOMIA
PWM7
PWM9
XR/W
T4PWM
_T4CMP
C4TRIP
TEST2
VDD3VFL
XD[11]
XA[2]
XWE
SPISIMOA
XA[1]
XRD
PWM12
CAP4
_QEP3
CAP5
_QEP4
TEST1
XD[9]
X2
VSS
XA[3]
VDD
VSS
XD[6]
PWM11
XD[7]
C5TRIP
VDDIO
TDIRB
XD[10]
VDDIO
VSS
SPICLKA
XD[4]
SPISTEA
T3PWM
_T3CMP
VSS
C6TRIP
TCLKINB
X1/
XCLKIN
MCLKXA
MFSRA
XD[3]
VDDIO
VDD
MCLKRA
XD[1]
MDXA
MDRA
XMP/MC
ADCRESEXT
AVDDAVSSADCREFM ADCINA5 ADCXHOLD

ADCREFP
REFBG
REFBG
BGREFIN
SCIRXDB
PWM2
VSS
PWM3
PWM4
XD[12]
XHOLDA
PWM5
VDD
VSS
PWM6
XD[5]
XD[13]
T1PWM
_T1CMP
XA[4]
T2PWM
_T2CMP
VSS
MFSXA
XD[2]
CAP1
_QEP1
CAP2
_QEP2
CAP3
_QEPI1
XA[5]
T1CTRIP
_PDPINTA
XD[0]
VSS
XA[0]
T2CTRIP/
EVASOC
VDDIO
VDD
VSS
XA[6]
VSSA1
VDDA1
ADCINB7
C3TRIP XCLKOUT
XA[7]
TCLKINA
TDIRA
ADCINB3 ADCINB0 ADCINB1 ADCINA2
ADCINB2
SCITXDB
PWM1
VSSAIO
XZCS2
VDDIO
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
VDD
CANTXA CANRXA
VDDAIO
T3CTRIP T4CTRIP/
_PDPINTB EVBSOC
VSSA2
VDDIO
XA[13]
C2TRIP
XA[8]
C1TRIP
VSS
XRS
XA[18]
XINT2
_ADCSOC
XINT1
_XBIO
VSS
EMU0
TDO
TMS
XA[9]
VSS1
SCITXDA
VDD
EMU1
VSS
XA[12]
XA[10]
TDI
VDD
XA[17]
VSS
XA[15]
VDD
XD[14]
TRST
ADCLO ADCINA3 ADCINA7 XREADY
ADCINA0 ADCINA4
XNMI
_XINT13
XZCS6AND7 VSS
VDDA2
VDD1
SCIRXDA
XA[16]
XD[15]
XA[14]
XF
_XPLLDIS
TCK
TESTSEL
XA[11]
10
11
12
13
14
Figure 2 - 1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View)
14
SPRS174J
Introduction
2.3.2
Pin Assignments for the PGF Package
XA[11]
TDI
XA[10]
V SS
V DD
TDO
TMS
XA[9]
C3TRIP
C2TRIP
C1TRIP
XA[8]
V SS
XCLKOUT
XA[7]
TCLKINA
TDIRA
T2CTRIP / EVASOC
V DDIO
V SS
V DD
XA[6]
T1CTRIP_PDPINTA
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
V SS
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
V DD
V SS
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320F2812 and TMS320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are
shown in Figure 2 - 2. See Table 3 - 2 for a description of each pins function(s).
132
89
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
176
XZCS2
CANTXA
VSS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
VDDIO
XA[2]
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
XD[11]
XD[10]
TCLKINB
TDIRB
VSS
VDD3VFL
XD[9]
TEST1
TEST2
XD[8]
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
VSS
CAP4_QEP3
VDD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
VSS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
VSS
VDD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
88
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
133
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
VSS
VDD
XA[14]
VDDIO
45
V DDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
V DDA1
V SSA1
ADCRESEXT
XMP/ MC
XA[0]
V SS
MDRA
XD[0]
MDXA
V DD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
V DDIO
V SS
XD[4]
SPICLKA
SPISTEA
XD[5]
V DD
V SS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
44
Figure 2 - 2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)
SPRS174J
15
Introduction
2.3.3
Pin Assignments for the PBK Package
TDI
VSS
VDD
TDO
TMS
C3TRIP
C2TRIP
C1TRIP
VSS
XCLKOUT
TCLKINA
TDIRA
T2CTRIP/ EVASOC
VDDIO
VDD
T1CTRIP_PDPINTA
CAP3_QEPI1
CAP2_QEP2
CAP1_QEP1
T2PWM_T2CMP
T1PWM_T1CMP
PWM6
VDD
VSS
PWM5
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad
flatpack (LQFP) pin assignments are shown in Figure 2 - 3. See Table 3 - 2 for a description of each pins
function(s).
96
65
64
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
97
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
VDD
VSS
VDDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
VSS
VDD
SCITXDA
SCIRXDA
XRS
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
128
CANTXA
VDD
VSS
T4CTRIP/EVBSOC
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
TCLKINB
TDIRB
VSS
VDD3VFL
TEST1
TEST2
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
VDD
T4PWM_T4CMP
T3PWM_T3CMP
VSS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
VSS
MDRA
MDXA
VDD
MCLKRA
MFSXA
MCLKXA
MFSRA
VDDIO
VSS
SPICLKA
SPISTEA
VDD
VSS
SPISIMOA
SPISOMIA
32
Figure 2 - 3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View)
16
SPRS174J
Introduction
2.4
Signal Descriptions
Table 3 - 2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All
outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-A (or 20-A) pullup/pulldown is used.
Table 3 - 2. Signal Descriptions
PIN NO.
NAME
I/O/Z
PU/PD
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
XA[18]
D7
158
O/Z
XA[17]
B7
156
O/Z
XA[16]
A8
152
O/Z
XA[15]
B9
148
O/Z
XA[14]
A10
144
O/Z
XA[13]
E10
141
O/Z
XA[12]
C11
138
O/Z
XA[11]
A14
132
O/Z
XA[10]
C12
130
O/Z
XA[9]
D14
125
O/Z
XA[8]
E12
121
O/Z
XA[7]
F12
118
O/Z
XA[6]
G14
111
O/Z
XA[5]
H13
108
O/Z
XA[4]
J12
103
O/Z
XA[3]
M11
85
O/Z
XA[2]
N10
80
O/Z
XA[1]
M2
43
O/Z
XA[0]
G5
18
O/Z
XD[15]
A9
147
I/O/Z
PU
XD[14]
B11
139
I/O/Z
PU
XD[13]
J10
97
I/O/Z
PU
XD[12]
L14
96
I/O/Z
PU
XD[11]
N9
74
I/O/Z
PU
XD[10]
L9
73
I/O/Z
PU
XD[9]
M8
68
I/O/Z
PU
XD[8]
P7
65
I/O/Z
PU
XD[7]
L5
54
I/O/Z
PU
XD[6]
L3
39
I/O/Z
PU
XD[5]
J5
36
I/O/Z
PU
XD[4]
K3
33
I/O/Z
PU
XD[3]
J3
30
I/O/Z
PU
XD[2]
H5
27
I/O/Z
PU
XD[1]
H3
24
I/O/Z
PU
XD[0]
G3
21
I/O/Z
PU
DESCRIPTION
XINTF SIGNALS (2812 ONLY)
19-bit
19
bit XINTF Address Bus
16 bit XINTF Data Bus

16-bit
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
SPRS174J
17
Introduction
Table 3 - 2. Signal Descriptions (Continued)

PIN NO.
NAME
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
XINTF SIGNALS (2812 ONLY) (CONTINUED)
XMP/MC
XHOLD
F1
E7
17
159
PD
Microprocessor/Microcomputer Mode Select. Switches

between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC pin is ignored
after reset.
PU
External Hold Request. XHOLD, when active (low), requests

the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
XHOLDA
K10
82
O/Z
External Hold Acknowledge. XHOLDA is driven active (low)

when the XINTF has granted a XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when
XHOLDA is active (low).
XZCS0AND1
P1
44
O/Z
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active

(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XZCS2
P13
88
O/Z
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an

access to the XINTF Zone 2 is performed.
XZCS6AND7
B13
133
O/Z
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active

(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
XWE
N11
84
O/Z
Write Enable. Active-low write strobe. The write strobe

waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
XRD
M3
42
O/Z
Read Enable. Active-low read strobe. The read strobe

waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
XR/W
N4
51
O/Z
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
18
SPRS174J
Introduction

PIN NO.
NAME
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
XINTF SIGNALS (2812 ONLY) (CONTINUED)

XREADY
B6
161
PU
Ready Signal. Indicates peripheral is ready to complete the

access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
K9
77
58
Oscillator Input - input to the internal oscillator. This pin is also

used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
digital power supply (VDD), rather than the 3.3-V I/O supply
(VDDIO). A clamping diode may be used to clamp a buffered
clock signal to ensure that the logic-high level does not
exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
X2
M9
76
57
Oscillator Output
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
XCLKOUT
F11
119
87
TESTSEL
A13
134
97
PD
Test Pin. Reserved for TI. Must be connected to ground.

Device Reset (in) and Watchdog Reset (out).
XRS
D6
160
113
I/O
PU
Device reset. XRS causes the device to terminate execution.

The PC will point to the address contained at the location
0x3FFFC0. When XRS is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal
pullup (100 A, typical). It is recommended that this pin be
driven by an open-drain device.
TEST1
TEST2
M7
N7
67
66
51
50
I/O
I/O
Test Pin. Reserved for TI. On F281x devices, TEST1 must be

left unconnected. On C281x devices, this pin is a no connect
(NC) (i.e., this pin is not connected to any circuitry internal
to the device).
Test Pin. Reserved for TI. On F281x devices, TEST2 must be

left unconnected. On C281x devices, this pin is a no connect
(NC) (i.e., this pin is not connected to any circuitry internal
to the device).
SPRS174J
19
Introduction

PIN NO.
NAME
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
JTAG
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TRST
B12
135
98
PD
TCK
A12
136
99
PU
JTAG test clock with internal pullup
TMS
D13
126
92
PU
JTAG test-mode select (TMS) with internal pullup. This serial

control input is clocked into the TAP controller on the rising
edge of TCK.
TDI
C13
131
96
PU
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDO
D12
127
93
O/Z
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is used

as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
EMU1
C9
146
105
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is used

as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS

ADCINA7
B5
167
119
ADCINA6
D5
168
120
ADCINA5
E5
169
121
ADCINA4
A4
170
122
ADCINA3
B4
171
123
ADCINA2
C4
172
124
ADCINA1
D4
173
125
ADCINA0
A3
174
126
8-Channel analog inputs for Sample-and-Hold A. The ADC

pins should not be driven before VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
20
SPRS174J
Introduction

PIN NO.
NAME
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
179-PIN
GHH
176-PIN
PGF
ADCINB7
F5
ADCINB6
D1
ADCINB5
D2
ADCINB4
D3
ADCINB3
C1
ADCINB2
B1
ADCINB1
C3
ADCINB0
C2
ADCREFP
E2
11
11
ADC Voltage Reference Output (2 V). Requires a low ESR

(50 m - 1.5 ) ceramic bypass capacitor of 10 F to analog
ground.
ADCREFM
E4
10
10
ADC Voltage Reference Output (1 V). Requires a low ESR

(50 m - 1.5 ) ceramic bypass capacitor of 10 F to analog
ground.
ADCRESEXT
F2
16
16
ADC External Current Bias Resistor (24.9 k 5%)
ADCBGREFIN
E6
164
116
Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG
E3
12
12
ADC Analog GND
AVDDREFBG
E1
13
13
ADC Analog Power (3.3-V)
ADCLO
B3
175
127
Common Low Side Analog Input. Connect to analog ground.
VSSA1
F3
15
15
ADC Analog GND
VSSA2
C5
165
117
ADC Analog GND
VDDA1
F4
14
14
ADC Analog 3.3-V Supply
VDDA2
A5
166
118
ADC Analog 3.3-V Supply
VSS1
C6
163
115
ADC Digital GND
VDD1
A6
162
114
ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO
B2
VSSAIO
A2
176
128
ADC ANALOG INPUT SIGNALS (CONTINUED)
8-Channel Analog Inputs for Sample-and-Hold B. The ADC

pins should not be driven before the VDDA1, VDDA2, and
VDDAIO pins have been fully powered up.
3.3-V Analog I/O Power Pin

Analog I/O Ground Pin
SPRS174J
21
Introduction

PIN NO.
NAME
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
H1
23
20
VDD
L1
37
29
VDD
P5
56
42
VDD
P9
75
56
VDD
P12
63
VDD
K12
100
74
VDD
G12
112
82
VDD
C14
128
94
VDD
B10
143
102
VDD
C8
154
110
VSS
G4
19
17
VSS
K1
32
26
VSS
L2
38
30
VSS
P4
52
39
VSS
K6
58
VSS
P8
70
53
VSS
M10
78
59
VSS
L11
86
62
VSS
K13
99
73
VSS
J14
105
VSS
G13
113
VSS
E14
120
88
VSS
B14
129
95
VSS
D10
142
VSS
C10
103
VSS
B8
153
109
VDDIO
J4
31
25
VDDIO
L7
64
49
VDDIO
L10
81
VDDIO
N14
VDDIO
G11
114
83
VDDIO
E9
145
104
I/O/Z
PU/PD
DESCRIPTION
POWER SIGNALS
VDD
VDD3VFL
N8
69
52
1.8-V or 1.9-V Core Digital Power Pins. See Section 7.2,

Recommended Operating Conditions,
Conditions
for voltage
requirements.
Core and Digital I/O Ground Pins
3 3 V I/O Digital Power Pins

3.3-V
3.3-V Flash Core Power Pin. This pin should be connected to

3.3 V at all times after power-up sequence requirements have
been met. This pin is used as VDDIO in ROM parts and must
be connected to 3.3 V in ROM parts as well.
22
SPRS174J
Introduction

PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS
GPIOA0
PWM1 (O)
M12
92
68
I/O/Z
PU
GPIO or PWM Output Pin #1
GPIOA1
PWM2 (O)
M14
93
69
I/O/Z
PU
GPIOA2
PWM3 (O)
L12
94
70
I/O/Z
PU
GPIOA3
PWM4 (O)
L13
95
71
I/O/Z
PU
GPIOA4
PWM5 (O)
K11
98
72
I/O/Z
PU
GPIOA5
PWM6 (O)
K14
101
75
I/O/Z
PU
GPIOA6
T1PWM_T1CMP (I)
J11
102
76
I/O/Z
PU
GPIO or Timer 1 Output
GPIOA7
T2PWM_T2CMP (I)
J13
104
77
I/O/Z
PU
GPIOA8
CAP1_QEP1 (I)
H10
106
78
I/O/Z
PU
GPIO or Capture Input #1
GPIOA9
CAP2_QEP2 (I)
H11
107
79
I/O/Z
PU
GPIOA10
CAP3_QEPI1 (I)
H12
109
80
I/O/Z
PU
GPIOA11
TDIRA (I)
F14
116
85
I/O/Z
PU
GPIO or Timer Direction
GPIOA12
TCLKINA (I)
F13
117
86
I/O/Z
PU
GPIO or Timer Clock Input
GPIOA13
C1TRIP (I)
E13
122
89
I/O/Z
PU
GPIO or Compare 1 Output Trip
GPIOA14
C2TRIP (I)
E11
123
90
I/O/Z
PU
GPIOA15
C3TRIP (I)
F10
124
91
I/O/Z
PU
GPIOB OR EVB SIGNALS

GPIOB0
PWM7 (O)
N2
45
33
I/O/Z
PU
GPIOB1
PWM8 (O)
P2
46
34
I/O/Z
PU
GPIOB2
PWM9 (O)
N3
47
35
I/O/Z
PU
GPIOB3
PWM10 (O)
P3
48
36
I/O/Z
PU
GPIOB4
PWM11 (O)
L4
49
37
I/O/Z
PU
GPIOB5
PWM12 (O)
M4
50
38
I/O/Z
PU
GPIOB6
T3PWM_T3CMP (I)
K5
53
40
I/O/Z
PU
GPIOB7
T4PWM_T4CMP (I)
N5
55
41
I/O/Z
PU
GPIOB8
CAP4_QEP3 (I)
M5
57
43
I/O/Z
PU
GPIOB9
CAP5_QEP4 (I)
M6
59
44
I/O/Z
PU
GPIOB10
CAP6_QEPI2 (I)
P6
60
45
I/O/Z
PU
GPIOB11
TDIRB (I)
L8
71
54
I/O/Z
PU
GPIO or Timer Direction
GPIOB12
TCLKINB (I)
K8
72
55
I/O/Z
PU
GPIO or Timer Clock Input
GPIOB13
C4TRIP (I)
N6
61
46
I/O/Z
PU
GPIOB14
C5TRIP (I)
L6
62
47
I/O/Z
PU
GPIOB15
C6TRIP (I)
K7
63
48
I/O/Z
PU
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
SPRS174J
23
Introduction

PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
GPIOD OR EVA SIGNALS

GPIOD0
T1CTRIP_PDPINTA (I)
H14
110
81
I/O/Z
PU
Timer 1 Compare Output Trip
GPIOD1
T2CTRIP/EVASOC (I)
G10
115
84
I/O/Z
PU
Timer 2 Compare Output Trip or External

ADC Start-of-Conversion EV-A
GPIOD OR EVB SIGNALS

GPIOD5
T3CTRIP_PDPINTB (I)
P10
79
60
I/O/Z
PU
Timer 3 Compare Output Trip
GPIOD6
T4CTRIP/EVBSOC (I)
P11
83
61
I/O/Z
PU
Timer 4 Compare Output Trip or External

ADC Start-of-Conversion EV-B
GPIOE0
XINT1_XBIO (I)
D9
149
106
I/O/Z
GPIOE1
XINT2_ADCSOC (I)
D8
151
108
GPIOE2
XNMI_XINT13 (I)
E8
150
107
GPIOF0
SPISIMOA (O)
M1
40
31
I/O/Z
GPIO or SPI slave in, master out
GPIOF1
SPISOMIA (I)
N1
41
32
I/O/Z
GPIO or SPI slave out, master in
GPIOF2
SPICLKA (I/O)
K2
34
27
I/O/Z
GPIO or SPI clock
GPIOF3
SPISTEA (I/O)
K4
35
28
I/O/Z
GPIO or SPI slave transmit enable
GPIOE OR INTERRUPT SIGNALS

-
GPIO or XINT1 or XBIO input
I/O/Z
GPIO or XINT2 or ADC start of conversion
I/O/Z
PU
GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF OR SCI-A SIGNALS

GPIOF4
SCITXDA (O)
C7
155
111
I/O/Z
PU
GPIO or SCI asynchronous serial port TX

data
GPIOF5
SCIRXDA (I)
A7
157
112
I/O/Z
PU
GPIO or SCI asynchronous serial port RX

data
GPIOF6
CANTXA (O)
N12
GPIOF7
CANRXA (I)
N13
GPIOF OR CAN SIGNALS

87
64
I/O/Z
PU
GPIO or eCAN transmit data
89
65
I/O/Z
PU
GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS

GPIOF8
MCLKXA (I/O)
J1
28
23
I/O/Z
PU
GPIO or transmit clock
GPIOF9
MCLKRA (I/O)
H2
25
21
I/O/Z
PU
GPIO or receive clock
GPIOF10
MFSXA (I/O)
H4
26
22
I/O/Z
PU
GPIO or transmit frame synch
GPIOF11
MFSRA (I/O)
J2
29
24
I/O/Z
PU
GPIO or receive frame synch
GPIOF12
MDXA (O)
G1
22
19
I/O/Z
GPIOF13
MDRA (I)
G2
20
18
I/O/Z
PU
GPIO or transmitted serial data

GPIO or received serial data
24
SPRS174J
Introduction

PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
PU/PD
DESCRIPTION
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOF14
XF_XPLLDIS (O)
A11
140
101
I/O/Z
PU
This pin has three functions:

1. XF - General-purpose output pin.
2. XPLLDIS - This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
3. GPIO - GPIO function
GPIOG OR SCI-B SIGNALS

GPIOG4
SCITXDB (O)
P14
90
66
I/O/Z
GPIO or SCI asynchronous serial port

transmit data
GPIOG5
SCIRXDB (I)
M13
91
67
I/O/Z
GPIO or SCI asynchronous serial port

receive data
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions.
SPRS174J
25
Functional Overview
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
Real-Time JTAG
CPU-Timer 2
TINT2
INT14
PIE
(96 interrupts)
TINT1
XINT13
XNMI
External Interrupt
Control
(XINT1/2/13, XNMI)
INT[12:1]
INT13
NMI
G
P
I
GPIO Pins
SCIA/SCIB
FIFO
SPI
FIFO
McBSP
FIFO
XRS
C28x CPU
X1/XCLKIN
X2
XF_XPLLDIS
(Oscillator and PLL

+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
Data(16)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
Flash
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
ROM
128K x 16 (C2812)
128K x 16 (C2811)
64K x 16 (C2810)
12-Bit ADC
System Control
Address(19)
L1 SARAM
4K x 16
EVA/EVB
16 Channels
Control
L0 SARAM
4K x 16
eCAN
U
X
External
Interface
(XINTF)
RS
CLKIN
OTP
1K x 16
H0 SARAM
8K 16
Memory Bus
Boot ROM
4K 16
Peripheral Bus
Protected by the code-security module.
45 of the possible 96 interrupts are used on the devices.

XINTF is available on the F2812 and C2812 devices only.
On C281x devices, the OTP is replaced with a 1K X 16 block of ROM
Figure 3 - 1. Functional Block Diagram
26
SPRS174J
Functional Overview
3.1
Memory Map
Block
Start Address
On-Chip Memory
Data Space
0x00 0000
0x00 0040
0x00 0400
Low 64K
(24x/240x Equivalent Data Space)
0x00 0800
0x00 0D00
0x00 0E00
0x00 2000
Prog Space
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
High 64K
(24x/240x Equivalent
Program Space)
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
Prog Space
M0 SARAM (1K 16)

M1 SARAM (1K 16)
Peripheral Frame 0
(2K 16)
PIE Vector - RAM
(256 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
XINTF Zone 0 (8K 16, XZCS0AND1)
Peripheral Frame 1
(4K 16, Protected)
Peripheral Frame 2
(4K 16, Protected)
XINTF Zone 1 (8K 16, XZCS0AND1) (Protected)
L0 SARAM (4K 16, Secure Block)
0x3F FFC0
LEGEND:
0x00 4000
Reserved
XINTF Zone 2 (0.5M 16, XZCS2)
0x08 0000
XINTF Zone 6 (0.5M 16, XZCS6AND7)
0x10 0000
0x18 0000
OTP (or ROM) (1K 16, Secure Block)

Reserved (1K)
Flash (or ROM) (128K 16, Secure Block)
Reserved
128-Bit Password
H0 SARAM (8K 16)

Reserved
0x3F F000
0x00 2000
Reserved
Reserved
0x3D 7C00
Data Space
M0 Vector - RAM (32 32)

(Enabled if VMAP = 0)
Reserved
0x00 6000
External Memory XINTF
Boot ROM (4K 16)

(Enabled if MP/MC = 0)
BROM Vector - ROM (32 32)

(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x3F C000
XINTF Zone 7 (16K 16, XZCS6AND7)

XINTF Vector - RAM (32 32)

Only one of these vector mapsM0 vector, PIE vector, BROM vector, XINTF vectorshould be enabled at a time.
NOTES: A.
B.
C.
D.
Memory blocks are not to scale.

Reserved locations are reserved for future expansion. Application should not access these areas.
Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 3 - 2. F2812/C2812 Memory Map
SPRS174J
27
Functional Overview
Block
Start Address
On-Chip Memory
Data Space
0x00 0000
0x00 0040
Low 64K
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
0x00 2000
Prog Space

M0 SARAM (1K 16)
M1 SARAM (1K 16)
Peripheral Frame 0
(2K 16)
PIE Vector - RAM
(256 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
Peripheral Frame 1
(4K 16, Protected)
Peripheral Frame 2
(4K 16, Protected)
Reserved
Reserved
0x3D 7800
High 64K
Program Space)
0x3D 7C00
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
Reserved (1K)

128-Bit Password
H0 SARAM (8K 16)

Reserved
0x3F F000
0x3F FFC0
LEGEND:
Boot ROM (4K 16)


Only one of these vector mapsM0 vector, PIE vector, BROM vector, XINTF vectorshould be enabled at a time.
NOTES: A. Memory blocks are not to scale.

B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
28
SPRS174J
Functional Overview
Block
Start Address
On-Chip Memory
Data Space
0x00 0000
0x00 0040

M0 SARAM (1K 16)
0x00 0400
Low 64K
Prog Space
0x00 0800
0x00 0D00
0x00 0E00
M1 SARAM (1K 16)
Peripheral Frame 0
(2K 16)
PIE Vector - RAM
(256 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(4K 16, Protected)
0x00 7000
Peripheral Frame 2
(4K 16, Protected)
Reserved
0x00 8000
0x00 9000
0x00 A000
Reserved
0x3D 7800
0x3D 7C00
Reserved
High 64K
Program Space)
0x3E 8000
0x3F 7FF8
128-Bit Password
0x3F 8000
H0 SARAM (8K 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
LEGEND:
Boot ROM (4K 16)


Only one of these vector mapsM0 vector, PIE vector, BROM vectorshould be enabled at a time.
NOTES: A. Memory blocks are not to scale.

B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
SPRS174J
29
Functional Overview
Table 4 - 1. Addresses of Flash Sectors in F2812 and F2811

ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000
0x3D 9FFF
Sector J, 8K x 16
0x3D A000
0x3D BFFF
Sector I, 8K x 16
0x3D C000
0x3D FFFF
Sector H, 16K x 16
0x3E 0000
0x3E 3FFF
Sector G, 16K x 16
0x3E 4000
0x3E 7FFF
Sector F, 16K x 16
0x3E 8000
0x3E BFFF
Sector E, 16K x 16
0x3E C000
0x3E FFFF
Sector D, 16K x 16
0x3F 0000
0x3F 3FFF
Sector C, 16K x 16
0x3F 4000
0x3F 5FFF
Sector B, 8K x 16
0x3F 6000
Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the

Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash Entry Point

(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
Table 4 - 2. Addresses of Flash Sectors in F2810
30
SPRS174J
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000
0x3E BFFF
Sector E, 16K x 16
0x3E C000
0x3E FFFF
Sector D, 16K x 16
0x3F 0000
0x3F 3FFF
Sector C, 16K x 16
0x3F 4000
0x3F 5FFF
Sector B, 8K x 16
0x3F 6000
Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the

Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash Entry Point

(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
Functional Overview
The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can be
used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from
XINTF Zone 7 (if MP/MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample
or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
NOTE:
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into
a single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only),
for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the
user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset
is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and
hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by
XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 4 - 3.
SPRS174J
31
Functional Overview
Table 4 - 3. Wait States
3.2
3.2.1
AREA
WAIT-STATES
M0 and M1 SARAMs
0-wait
Fixed
COMMENTS
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0 & L1 SARAMs
0-wait
OTP (or ROM)
Programmable,
1-wait minimum
Programmed via the Flash registers. 1-wait-state operation is possible at a

reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more
information.
Flash (or ROM)
Programmable,
0-wait minimum
Programmed via the Flash registers. 0-wait-state operation is possible at

reduced CPU frequency. The CSM password locations are hardwired for
16 wait-states. See Section 3.2.6, Flash (F281x Only), for more information.
H0 SARAM
0-wait
Fixed
Boot-ROM
1-wait
Fixed
XINTF
Programmable,
1-wait minimum
Programmed via the XINTF registers.

Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Brief Descriptions
C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant
software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop
not only their system control software in a high-level language, but also enables math algorithms to be
developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically
are handled by microcontroller devices. This efficiency removes the need for a second processor in many
systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x
to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive
floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical
registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.
The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables
the C28x to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
C28x and TMS320C2000 are trademarks of Texas Instruments.
32
SPRS174J
Functional Overview
3.2.2
Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single
cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to
fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories
attached to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses
can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Lowest:
3.2.3
Fetches
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F281x
and C281x adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines
and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on
the F281x and C281x. One version only supports 16-bit accesses (called peripheral frame 2) and this retains
compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses
(called peripheral frame 1).
3.2.4
Real-Time JTAG and Analysis

The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F281x and
C281x support real-time mode of operation whereby the contents of memory, peripheral and register locations
can be modified while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F281x and C281x implement the real-time mode in hardware within the CPU. This is a
unique feature to the F281x and C281x, no software monitor is required. Additionally, special analysis
hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and
generate various user selectable break events when a match occurs.
3.2.5
External Interface (XINTF) (2812 Only)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
Simultaneous Data and Program writes cannot occur on the Memory Bus.
Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.
SPRS174J
33
Functional Overview
3.2.6
Flash (F281x Only)

The F2812 and F2811 contain 128K x 16 of embedded Flash memory and 1K x 16 of OTP memory. The Flash
memory is segregated into four 8K x 16 sized sectors, and six 16K x 16 sized sectors. The user can individually
erase, program and validate a sector while leaving other sectors untouched. However, it is not possible to use
one sector of the Flash (or the OTP) to execute flash algorithms that erase/program other sectors. Special
memory pipelining is provided to enable the Flash module to achieve higher performance. The Flash/OTP is
mapped to both program and data space hence can be used to execute code or store data information.
The F2810 has 64K x 16 of embedded Flash and 1K x 16 of OTP memory. The address range of OTP is
0x3D 7800 - 0x3D 7BFF in the F281x devices.
NOTE:
The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application. This
allows applications running at slower frequencies to configure the flash to use fewer
wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash
options register. With this mode enabled, effective performance of linear code execution will
be much faster than the raw performance indicated by the wait state configuration alone. The
exact performance gain when using the Flash pipeline mode is application-dependent. The
pipeline mode is not available for the OTP block.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see
the TMS320F28x System Control and Interrupts Peripheral Reference Guide (literature
number SPRU078).
3.2.7
ROM (C281x Only)

The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In addition to this, there
is a 1K X 16 ROM block that replaces the OTP memory available in flash devices. For information on how to
submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide (literature number
SPRU430).
3.2.8
M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.9
L0, L1, H0 SARAMs

The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into 3 blocks
(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is
mapped to both program and data space.
3.2.10 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal Flash.
The Boot ROM will also contain standard tables, such as SIN/COS waveforms, for use in math related
algorithms.
34
SPRS174J
Functional Overview
3.2.11
Security
The F281x and C281x support high levels of security to protect the user firmware from being reversed
engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user programs
into the Flash. One code security module (CSM) is used to protect the Flash/ROM/OTP and the L0/L1 SARAM
blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG
port, executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit
KEY value, which matches the value stored in the password locations within the Flash/ROM.
NOTE:
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used
as program code or data, but must be programmed to 0x0000 when the Code Security
Passwords are programmed. If security is not a concern, then these addresses may be used
for code or data.
Code Security Module Disclaimer

The Code Security Module (CSM) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TIs published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
3.2.12 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On the F281x and C281x, 45 of the possible 96 interrupts
are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU
interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated
RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing
the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU
can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each
individual interrupt can be enabled/disabled within the PIE block.
3.2.13 External Interrupts (XINT1, 2, 13, XNMI)

The F281x and C281x support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts
can be selected for negative or positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
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Functional Overview
3.2.14 Oscillator and PLL

The F281x and C281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator
circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed
on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is
desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass
mode.
3.2.15 Watchdog
The F281x and C281x support a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can
be disabled if necessary.
3.2.16 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when
a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
3.2.17 Low-Power Modes

The F281x and C281x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event.
HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this
mode.
3.2.18 Peripheral Frames 0, 1, 2 (PFn)

The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
36
XINTF:
External Interface Configuration Registers (2812 only)
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Control, Programming, Erase, Verify Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
PF1:
eCAN:
eCAN Mailbox and Control Registers
PF2:
SYS:
System Control Registers
GPIO:
GPIO Mux Configuration and Control Registers
EV:
Event Manager (EVA/EVB) Control Registers
McBSP:
McBSP Control and TX/RX Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Peripheral Interface (SPI) Control and RX/TX Registers
ADC:
12-Bit ADC Registers
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Functional Overview
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.20 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system functions. CPU-Timer 2 is
connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of the CPU. CPU-Timer 0 is for
general use and is connected to the PIE block.
3.2.21 Control Peripherals

The F281x and C281x support the following peripherals which are used for embedded control and
communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on the F281x and C281x are compatible to the
event managers on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.22 Serial Port Peripherals

The F281x and C281x support the following serial communication peripherals:
eCAN:
McBSP:
SPI:
SCI:
3.3
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On the F281x and C281x, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F281x and C281x, the port supports a 16-level, receive and
transmit FIFO for reducing servicing overhead.
Register Map
The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
SPRS174J
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Functional Overview
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 4 - 4.
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 4 - 5.
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 4 - 6.
Table 4 - 4. Peripheral Frame 0 Registers
ACCESS TYPE
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x00 0880
0x00 09FF
384
reserved
0x00 0A00
0x00 0A7F
128
FLASH Registers
0x00 0A80
0x00 0ADF
96
Code Security Module Registers
0x00 0AE0
0x00 0AEF
16
reserved
0x00 0AF0
0x00 0B1F
48
XINTF Registers
0x00 0B20
0x00 0B3F
32
reserved
0x00 0B40
0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00
0x00 0C3F
64
reserved
0x00 0C40
0x00 0CDF
160
PIE Registers
0x00 0CE0
0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00
0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00
0x00 0FFF
512
NAME
EALLOW protected
EALLOW protected
CSM Protected
EALLOW protected
Registers in Frame 0 support 16-bit and 32-bit accesses.

If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).

NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
eCAN Registers
0x00 6000
0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN

control registers) are EALLOW-protected.
eCAN Mailbox RAM
0x00 6100
0x00 61FF
256
(128 x 32)
Not EALLOW-protected
reserved
0x00 6200
0x00 6FFF
3584
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
38
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Functional Overview

ADDRESS RANGE
SIZE (x16)
reserved
0x00 7000
0x00 700F
16
System Control Registers
0x00 7010
0x00 702F
32
reserved
0x00 7030
0x00 703F
16
SPI-A Registers
0x00 7040
0x00 704F
16
Not EALLOW Protected
SCI-A Registers
0x00 7050
0x00 705F
16
reserved
0x00 7060
0x00 706F
16
External Interrupt Registers
0x00 7070
0x00 707F
16
reserved
0x00 7080
0x00 70BF
64
GPIO Mux Registers
0x00 70C0
0x00 70DF
32
EALLOW Protected
GPIO Data Registers
0x00 70E0
0x00 70FF
32
ADC Registers
0x00 7100
0x00 711F
32
reserved
0x00 7120
0x00 73FF
736
EV-A Registers
0x00 7400
0x00 743F
64
reserved
0x00 7440
0x00 74FF
192
EV-B Registers
0x00 7500
0x00 753F
64
reserved
0x00 7540
0x00 774F
528
SCI-B Registers
0x00 7750
0x00 775F
16
reserved
0x00 7760
0x00 77FF
160
McBSP Registers
0x00 7800
0x00 783F
64
reserved
0x00 7840
0x00 7FFF
1984
NAME
ACCESS TYPE
EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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Functional Overview
3.4
Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 4 - 7.
Table 4 - 7. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DEVICECNF
0x00 0880
0x00 0881
Device Configuration Register
reserved
0x00 0882
Not supported on Revision C and later silicon
DEVICEID
0x00 0883
Device ID Register (0x0003 - silicon - Rev. C)
PROTSTART
0x00 0884
Block Protection Start Address Register
PROTRANGE
0x00 0885
Block Protection Range Address Register
reserved
0x00 0886
0x00 09FF
378
3.5
DESCRIPTION
External Interface, XINTF (2812 Only)

This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 devices.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the 2812 is mapped into five fixed zones shown in Figure 3 - 5.
Figure 3 - 5 shows the 2812 XINTF signals.
40
SPRS174J
Functional Overview
Data Space
Prog Space
0x00 0000
XD(15:0)
XA(18:0)
0x00 2000
0x00 4000
XINTF Zone 0
(8K 16)
XINTF Zone 1
(8K 16)
XZCS0
XZCS1
XZCS0AND1
0x00 6000
0x08 0000
0x10 0000
XINTF Zone 2
(512K 16)
XZCS2
XINTF Zone 6
(512K 16)
XZCS6
XINTF Zone 7
(16K 16)
(mapped here if MP/MC = 1)
XZCS7
XZCS6AND7
0x18 0000
0x3F C000
0x40 0000
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note E)
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects
(XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable
glueless connection to many external memories and peripherals.
C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external memory
that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.
D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
E. XCLKOUT is also pinned out on the 2810 and 2811.
Figure 3 - 5. External Interface Block Diagram
SPRS174J
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Functional Overview
The operation and timing of the external interface, can be controlled by the registers listed in Table 4 - 8.
Table 4 - 8. XINTF Configuration and Control Register Mappings
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
NAME
0x00 0B20
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register
XTIMING1
0x00 0B22
XTIMING2
0x00 0B24
XTIMING6
0x00 0B2C
XTIMING7
0x00 0B2E
XINTCNF2
0x00 0B34
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register
XBANK
0x00 0B38
XINTF Bank Control Register
XREVISION
0x00 0B3A
XINTF Revision Register
3.5.1
Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect
to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 7 - 26.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320F28x DSP
External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2
XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 4 - 9.
Table 4 - 9. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
15- 0
REVISION
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
42
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Functional Overview
3.6
Interrupts
Figure 3 - 6 shows how the various interrupt sources are multiplexed within the F281x and C281x devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
WAKEINT
LPMINT
PIE
96 Interrupts
INT1 to INT12
Interrupt Control
Watchdog
Low-Power Modes
XINT1
XINT1CR(15:0)
XINT1CTR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
C28x CPU
XINT2CTR(15:0)
TINT0
TINT2
INT14
TIMER 2 (for RTOS)
TINT1
TIMER 1 (for RTOS)
MUX
INT13
GPIO
MUX
TIMER 0
select
enable
NMI
Interrupt Control
XNMI_XINT13
XNMICR(15:0)
XNMICTR(15:0)
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3 - 6. Interrupt Sources
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Functional Overview
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the F281x and C281x, 45 of these are used by
peripherals as shown in Table 4 - 10.
IFR(12:1)
INTM
IER(12:1)
INT1
INT2
1
MUX
INT11
INT12
(Flag)
INTx
Global
Enable
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
CPU
From
Peripherals or
External
Interrupts
Figure 3 - 7. Multiplexing of Interrupts Using the PIE Block

Table 4 - 10. PIE Peripheral Interrupts
CPU
INTERRUPTS
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
INT2
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
INT3
reserved
CAPINT3
(EV-A)
INT4
reserved
INT5
INTx.4
INTx.3
INTx.2
INTx.1
XINT1
reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
reserved
reserved
MXINT
(McBSP)
MRINT
(McBSP)
reserved
reserved
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
INT7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN0INT
(CAN)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
ECAN1INT
(CAN)
INT10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
44
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Functional Overview
Table 4 - 11. PIE Configuration and Control Registers

NAME
ADDRESS
Size (x16)
DESCRIPTION
PIECTRL
0x0000- 0CE0
PIE, Control Register
PIEACK
0x0000- 0CE1
PIE, Acknowledge Register
PIEIER1
0x0000- 0CE2
PIE, INT1 Group Enable Register
PIEIFR1
0x0000- 0CE3
PIE, INT1 Group Flag Register
PIEIER2
0x0000- 0CE4
PIEIFR2
0x0000- 0CE5
PIEIER3
0x0000- 0CE6
PIEIFR3
0x0000- 0CE7
PIEIER4
0x0000- 0CE8
PIEIFR4
0x0000- 0CE9
PIEIER5
0x0000- 0CEA
PIEIFR5
0x0000- 0CEB
PIEIER6
0x0000- 0CEC
PIEIFR6
0x0000- 0CED
PIEIER7
0x0000- 0CEE
PIEIFR7
0x0000- 0CEF
PIEIER8
0x0000- 0CF0
PIEIFR8
0x0000- 0CF1
PIEIER9
0x0000- 0CF2
PIEIFR9
0x0000- 0CF3
PIEIER10
0x0000- 0CF4
PIEIFR10
0x0000- 0CF5
PIEIER11
0x0000- 0CF6
PIEIFR11
0x0000- 0CF7
PIEIER12
0x0000- 0CF8
PIEIFR12
0x0000- 0CF9
Reserved
0x0000- 0CFA
0x0000- 0CFF
Reserved
Note:
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
SPRS174J
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Functional Overview
3.6.1
External Interrupts
Table 4 - 12. External Interrupts Registers
ADDRESS
SIZE (x16)
XINT1CR
NAME
0x00 7070
XINT1 control register
DESCRIPTION
XINT2CR
0x00 7071
XINT2 control register
reserved
0x00 7072
0x00 7076
XNMICR
0x00 7077
XNMI control register
XINT1CTR
0x00 7078
XINT1 counter register
XINT2CTR
0x00 7079
XINT2 counter register
reserved
0x00 707A
0x00 707E
XNMICTR
0x00 707F
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more
information, see the TMS320F28x System Control and Interrupts Peripheral Reference Guide (literature
number SPRU078).
46
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Functional Overview
3.7
System Control
This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog function
and the low power modes. Figure 3 - 8 shows the various clock and reset domains in the F281x and C281x
devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
C28x
CPU
X1/XCLKIN
PLL
OSC
Power
Modes
Control
System
Control
Registers
eCAN
Peripheral Bus
Low-Speed Prescaler
I/O
LSPCLK
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
I/O
GPIOs
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
XF_XPLLDIS
Clock Enables
Peripheral
Registers
Peripheral
Registers
X2
High-Speed Peripherals
EV-A/B
I/O
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3 - 8. Clock and Reset Domains
SPRS174J
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Functional Overview
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 4 - 13.
Table 4 - 13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
ADDRESS
SIZE (x16)
reserved
0x00 7010
0x00 7017
reserved
0x00 7018
reserved
0x00 7019
HISPCP
0x00 701A
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
NAME
LOSPCP
DESCRIPTION
0x00 701B
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR
0x00 701C
Peripheral Clock Control Register
reserved
0x00 701D
LPMCR0
0x00 701E
Low Power Mode Control Register 0
LPMCR1
0x00 701F
Low Power Mode Control Register 1
reserved
0x00 7020
PLLCR
0x00 7021
PLL Control Register
SCSR
0x00 7022
System Control & Status Register
WDCNTR
0x00 7023
Watchdog Counter Register
reserved
0x00 7024
WDKEY
0x00 7025
reserved
0x00 7026
0x00 7028
WDCR
0x00 7029
reserved
0x00 702A
0x00 702F
Watchdog Reset Key Register
Watchdog Control Register
All of the above registers can only be accessed, by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.
48
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Functional Overview
3.8
OSC and PLL Block

Figure 3 - 9 shows the OSC and PLL block on the F281x and C281x.
XPLLDIS
Latch
XF_XPLLDIS
XRS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
CLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
CPU
SYSCLKOUT
4-Bit PLL Select

X2
PLL
4-Bit PLL Select
PLL Block
Figure 3 - 9. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the
X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the
X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD.
The PLLCR bits [3:0] set the clocking ratio.
Table 4 - 14. PLLCR Register Bit Definitions
BIT(S)
NAME
TYPE
XRS RESET
15:4
reserved
R=0
0:0
DESCRIPTION
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
3:0
DIV
R/W
0,0,0,0
Bit Value
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
SPRS174J
49
Functional Overview
3.8.1
Loss of Input Clock

In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1- 4 MHz. The PLLCR register should have been written to with a non-zero value for this feature
to work.
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset
or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing
(i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the
application firmware to detect the input clock failure and initiate necessary shut-down procedure for the
system.
3.9
PLL-Based Clock Module

The F281x and C281x have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR
register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 XCLKIN
cycles.
The PLL-based clock module provides two modes of operation:
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
External clock source operation

This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the X1/XCLKIN pin.
X1/XCLKIN
Cb1
(see Note A)
X2
Crystal
X1/XCLKIN
Cb2
(see Note A)
(a)
X2
External Clock Signal

(Toggling 0 - VDD)
NC
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 3 - 10. Recommended Crystal / Clock Connection

Table 4 - 15. Possible PLL Configuration Modes
PLL MODE
50
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value n into PLLCR register. The /2 module

in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
SPRS174J
XCLKIN
Functional Overview
3.10 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
3.11
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40
Watchdog Block
The watchdog block on the F281x and C281x is identical to the one used on the 240x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog
counter. Figure 3 - 11 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY(7:0)
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
WDRST
WDINT
XRS
Core-reset
WDCR (WDCHK(2:0))
WDRST
Bad
WDCHK
Key
SCSR (WDENINT)
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3 - 11. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional
is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal
is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.12,
Low-Power Modes Block, for more details.
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Functional Overview
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.12 Low-Power Modes Block

The low-power modes on the F281x and C281x are similar to the 240x devices. Table 4 - 16 summarizes the
various modes.
Table 4 - 16. F281x and C281x Low-Power Modes
EXIT
MODE
IDLES
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
Normal
low
X,X
on
on
on
on
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
Debugger
off
off
XRS,
WDINT,
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger
off
off
XRS,
XNMI,
Debugger
IDLE
high
0,0
on
on
on
STANDBY
high
0,1
(watchdog still
running)
off
HALT
high
1,X
(oscillator and
PLL turned
off, watchdog
not functional)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:

IDLE Mode:
This mode is, exited by any enabled interrupt or an NMI that is

recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them in when the IDLE instruction was executed.
52
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Peripherals
Peripherals
The integrated peripherals of the F281x and C281x are described in the following subsections:
4.1
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Enhanced controller area network (eCAN) module
Multichannel buffered serial port (McBSP) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
Digital I/O and shared pin functions
32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F281x and C281x devices (CPU-TIMER0/1/2).
CPU-Timers 1 and 2 are reserved for the Real-Time OS (such as DSP/BIOS). CPU-Timer 0 can be used in
user applications. These timers are different from the general-purpose (GP) timers that are present in the
Event Manager modules (EVA, EVB).
NOTE: If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down

TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
16-Bit Prescale Counter

PSCH:PSC
Borrow
32-Bit Timer Period

PRDH:PRD
32-Bit Counter
TIMH:TIM
Borrow
TINT
NOTE A: The CPU-Timers are different from the general-purpose (GP) timers that are present in the
Event Manager modules (EVA, EVB).
Figure 4 - 1. CPU-Timers
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Peripherals
In the F281x and C281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown
in Figure 4 - 2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
INT13
TINT1
CPU-TIMER 1
(for RTOS use)
XINT13
INT14
TINT2
CPU-TIMER 2
(for RTOS use)
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4 - 2. CPU-Timer Interrupts Signals and Output Signal

The general operation of the timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the value
in the period register PRDH:PRD. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 5 - 1 are used to configure the timers. For more information, see the TMS320F28x System Control
and Interrupts Peripheral Reference Guide (literature number SPRU078).
54
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Peripherals
Table 5 - 1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x00 0C00
CPU-Timer 0, Counter Register
TIMER0TIMH
0x00 0C01
CPU-Timer 0, Counter Register High
TIMER0PRD
0x00 0C02
CPU-Timer 0, Period Register
TIMER0PRDH
0x00 0C03
CPU-Timer 0, Period Register High
TIMER0TCR
0x00 0C04
CPU-Timer 0, Control Register
reserved
0x00 0C05
TIMER0TPR
0x00 0C06
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x00 0C07
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x00 0C08
TIMER1TIMH
0x00 0C09
TIMER1PRD
0x00 0C0A
TIMER1PRDH
0x00 0C0B
TIMER1TCR
0x00 0C0C
reserved
0x00 0C0D
TIMER1TPR
0x00 0C0E
TIMER1TPRH
0x00 0C0F
TIMER2TIM
0x00 0C10
TIMER2TIMH
0x00 0C11
TIMER2PRD
0x00 0C12
TIMER2PRDH
0x00 0C13
TIMER2TCR
0x00 0C14
reserved
0x00 0C15
TIMER2TPR
0x00 0C16
TIMER2TPRH
0x00 0C17
reserved
0x00 0C18
0x00 0C3F
40
DESCRIPTION
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55
Peripherals
4.2
Event Manager Modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 5 - 2 shows the module and signal names
used. Table 5 - 2 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to functionhowever,
module/signal names would differ. Table 5 - 3 lists the EVA registers. For more information, see the
TMS320F28x DSP Event Manager (EV) Reference Guide (literature number SPRU065).
Table 5 - 2. Module and Signal Names for EVA and EVB
EVENT MANAGER MODULES
EVB
SIGNAL
MODULE
SIGNAL
GP Timers
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare Units
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP Channels
QEP1
QEP2
QEPI1
QEP1
QEP2
QEP3
QEP4
QEPI2
QEP3
QEP4
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
Compare
C1TRIP
C2TRIP
C3TRIP
Compare
C4TRIP
C5TRIP
C6TRIP
External Clock Inputs

External Trip Inputs
External Trip Inputs
EVA
MODULE
T1CTRIP_PDPINTA
T2CTRIP/EVASOC
T3CTRIP_PDPINTB
T4CTRIP/EVBSOC
In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.
56
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Peripherals
Table 5 - 3. EVA Registers

NAME
ADDRESS
SIZE
(x16)
GPTCONA
0x00 7400
GP Timer Control Register A
T1CNT
0x00 7401
GP Timer 1 Counter Register
T1CMPR
0x00 7402
GP Timer 1 Compare Register
T1PR
0x00 7403
GP Timer 1 Period Register
T1CON
0x00 7404
GP Timer 1 Control Register
T2CNT
0x00 7405
GP Timer 2 Counter Register
T2CMPR
0x00 7406
GP Timer 2 Compare Register
DESCRIPTION
T2PR
0x00 7407
GP Timer 2 Period Register
T2CON
0x00 7408
GP Timer 2 Control Register
EXTCONA
0x00 7409
GP Extension Control Register A
COMCONA
0x00 7411
Compare Control Register A
ACTRA
0x00 7413
Compare Action Control Register A
DBTCONA
0x00 7415
Dead-Band Timer Control Register A
CMPR1
0x00 7417
Compare Register 1
CMPR2
0x00 7418
Compare Register 2
CMPR3
0x00 7419
Compare Register 3
CAPCONA
0x00 7420
Capture Control Register A
CAPFIFOA
0x00 7422
Capture FIFO Status Register A
CAP1FIFO
0x00 7423
Two-Level Deep Capture FIFO Stack 1
CAP2FIFO
0x00 7424
CAP3FIFO
0x00 7425
CAP1FBOT
0x00 7427
Bottom Register Of Capture FIFO Stack 1
CAP2FBOT
0x00 7428
CAP3FBOT
0x00 7429
EVAIMRA
0x00 742C
Interrupt Mask Register A
EVAIMRB
0x00 742D
Interrupt Mask Register B
EVAIMRC
0x00 742E
Interrupt Mask Register C
EVAIFRA
0x00 742F
Interrupt Flag Register A
EVAIFRB
0x00 7430
Interrupt Flag Register B
EVAIFRC
0x00 7431
Interrupt Flag Register C
The EV-B register set is identical except the address range is from 0x00 - 7500 to 0x00 - 753F. The above registers are mapped to Zone 2. This
space allows only 16-bit accesses. 32-bit accesses produce undefined results.
New register compared to 24x/240x
SPRS174J
57
Peripherals
GPTCONA(12:4), CAPCONA(8), EXTCONA[0]
EVAENCLK
EVATO ADC (Internal)
T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP
Control Logic
EVASOC ADC (External)

Output
T1PWM_T1CMP
Logic
Timer 1 Compare
16
T1CON(5,4)
GPTCONA(1,0)
TCLKINA
T1CON(1)
clock
GP Timer 1
HSPCLK
Prescaler
dir
T1CON(10:8)
16
TDIRA
T1CON(15:11,6,3,2)
Full Compare 1
SVPWM
Peripheral Bus
Full Compare 2
State
Machine
Full Compare 3
ACTRA(15:12),
COMCONA(15:5,2:0)
PWM1
PWM2
PWM3
Output
Logic
DeadBand
Logic
PWM4
PWM5
PWM6
DBTCONA(15:0)
COMCONA(12),
T1CON(13:11)
ACTRA(11:0)
Output
Timer 2 Compare
T2PWM_T2CMP
Logic
16
T2CON(5,4)
T2CON(1)
GPTCONA(3,2)
TCLKINA
GP Timer 2
clock
dir
reset
Prescaler
HSPCLK
QEPCLK
16
T2CON(10:8)
T2CON(15:11,7,6,3,2,0)
CAPCONA(10,9)
QEP
Logic
QEPDIR
16
TDIRA
CAP1_QEP1
CAP2_QEP2
Capture Units
Index Qual
CAPCONA(15:12,7:0)
CAP3_QEPI1
EXTCONA(1:2)
NOTE A: The EVB module is similar to the EVA module.
Figure 4 - 3. Event Manager A Functional Block Diagram
58
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Peripherals
4.2.1
General-Purpose (GP) Timers

There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up / down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the
time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP
timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period
and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse
width as needed.
4.2.2
Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
4.2.3
Programmable Deadband Generator

Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed by
way of the double-buffered ACTRx register.
4.2.4
PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5
Double Update PWM Mode

The F281x and C281x Event Manager supports Double Update PWM Mode. This mode refers to a PWM
operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse
are independently modifiable in each PWM period. To support this mode, the compare register that determines
the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning
of a PWM period and another time in the middle of a PWM period. The compare registers in F281x and C281x
Event Managers are all buffered and support three compare value reload/update (value in buffer becoming
active) modes. These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR
Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for
compare value reload.
SPRS174J
59
Peripherals
4.2.6
PWM Characteristics
Characteristics of the PWMs are as follows:
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space

vector PWM waveforms
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx
register.
4.2.7
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
EXTCON register bits provide options to individually trip control for each PWM pair of signals
Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of
three capture circuits.
4.2.8
Capture units include the following features:

-
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet the input qualification circuitry requirements. The input pins
CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
Quadrature-Encoder Pulse (QEP) Circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with
EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
60
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4.2.9
External ADC Start-of-Conversion

EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
4.3
Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 4 - 4. The ADC module consists
of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 autoconversions in a single session. Each conversion can

be programmed to select any 1 of 16 input channels
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values

-
The digital value of the input analog voltage is derived by:

Digital Value + 4095
Input Analog Voltage * ADCLO

3
Multiple triggers as sources for the start-of-conversion (SOC) sequence

-
S/W - software immediate start
EVA - Event manager A (multiple event sources within EVA)
EVB - Event manager B (multiple event sources within EVB)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in start/stop mode, allowing multiple time-sequenced triggers to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event managers
A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at
25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules
to service event managers A and B. The two independent 8-channel modules can be cascaded to form a
16-channel module. Although there are multiple input channels and two sequencers, there is only one
converter in the ADC module. Figure 4 - 4 shows the block diagram of the F281x and C281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has
the choice of selecting any one of the respective eight channels available through an analog MUX. In the
cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once
the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
SPRS174J
61
Peripherals
System
Control Block
SYSCLKOUT
High-Speed
Prescaler
ADCENCLK
C28x
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers

S/W
EVA
SOC
Sequencer 1
Sequencer 2
ADCSOC
SOC
S/W
EVB
Figure 4 - 4. Block Diagram of the F281x and C281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2 , AVDDREFBG ) from the digital
supply. Figure 4 - 5 shows the ADC pin connections for the F281x and C281x devices.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will
still function. This is necessary to make sure all registers and modes go into their default reset state. The
analog module will however be in a low-power inactive state. As soon as reset goes high, then the clock to
the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms
range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the
CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
62
SPRS174J
Peripherals
ADC 16-Channel
Analog Inputs
ADCINA[7:0]
ADCINB[7:0]
ADCLO
Test Pin ADCBGREFIN

ADC External Current Bias Resistor
ADCRESEXT
Analog Input 0 - 3 V with

Respect to ADCLO
Connect to analog ground
24.9 kW
10 mF
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
ADC Digital Power
VDD1
VSS1
10 mF
ADCREFP and ADCREFM should not

be loaded by external circuitry.
Analog 3.3 V
Analog Ground
Digital Ground
1.8 V Can use the same 1.8-V (or 1.9-V)

supply as the digital core but
separate the two with a ferrite bead
or a filter.
Provide access to this pin in PCB layouts. Intended for test purposes only.
TAIYO YUDEN EMK325F106ZH - T or equivalent
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC
performance.
Figure 4 - 5. ADC Pin Connections (See Notes A and B)
SPRS174J
63
Peripherals
The ADC operation is configured, controlled, and monitored by the registers listed in Table 5 - 4.
Table 5 - 4. ADC Registers
64
NAME
ADDRESS
SIZE
(x16)
ADCTRL1
0x00 7100
ADC Control Register 1
DESCRIPTION
ADCTRL2
0x00 7101
ADCMAXCONV
0x00 7102
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x00 7103
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x00 7104
ADCCHSELSEQ3
0x00 7105
ADCCHSELSEQ4
0x00 7106
ADCASEQSR
0x00 7107
ADC Auto-Sequence Status Register
ADCRESULT0
0x00 7108
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x00 7109
ADCRESULT2
0x00 710A
ADCRESULT3
0x00 710B
ADCRESULT4
0x00 710C
ADCRESULT5
0x00 710D
ADCRESULT6
0x00 710E
ADCRESULT7
0x00 710F
ADCRESULT8
0x00 7110
ADCRESULT9
0x00 7111
ADCRESULT10
0x00 7112
ADCRESULT11
0x00 7113
ADCRESULT12
0x00 7114
ADCRESULT13
0x00 7115
ADCRESULT14
0x00 7116
ADCRESULT15
0x00 7117
ADCTRL3
0x00 7118
ADCST
0x00 7119
ADC Status Register
reserved
0x00 711C
0x00 711F
The above registers are Peripheral Frame 2 Registers.
SPRS174J
Peripherals
4.4
Enhanced Controller Area Network (eCAN) Module

The CAN module has the following features:
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:

-
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
Self-test mode
-
Operates in a loopback mode receiving its own message. A dummy acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.
SPRS174J
65
Peripherals
eCAN0INT
Controls Address
eCAN1INT
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
32-Message Mailbox
of 4 32-Bit Words
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
32
eCAN Protocol Kernel

Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4 - 6. eCAN Block Diagram and Interface Circuit

Table 5 - 5. 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs
66
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
--
- 40 C to 85 C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
--
- 40 C to 125 C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
--
- 40 C to 85 C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
--
- 40 C to 125 C
SN65HVD232
3.3 V
None
None
None
--
- 40 C to 85 C
SN65HVD232Q
3.3 V
None
None
None
--
- 40 C to 125 C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic
Loopback
- 40 C to 125 C
SPRS174J
Peripherals
Table 5 - 5. 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs (Continued)
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD234
3.3 V
Standby & Sleep
Adjustable
None
--
- 40OC to 125OC
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud
Loopback
- 40OC to 125OC
eCAN Control and Status Registers

Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
eCAN Memory (512 Bytes)
6000h
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Abort Acknowledge - CANAA

Received Message Pending - CANRMP
Control and Status Registers
Received Message Lost - CANRML

Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)

(32 32-Bit RAM)
Global Acceptance Mask - CANGAM

Master Control - CANMC
Message Object Time Stamps (MOTS)

(32 32-Bit RAM)
Bit-Timing Configuration - CANBTC

Error and Status - CANES
Message Object Time-Out (MOTO)

(32 32-Bit RAM)
Transmit Error Counter - CANTEC

Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN Memory RAM (512 Bytes)

6100h- 6107h
Mailbox 0
6108h- 610Fh
Mailbox 1
6110h- 6117h
Mailbox 2
6118h- 611Fh
Mailbox 3
6120h- 6127h
Mailbox 4
Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h- 61E7h
Mailbox 28
61E8h- 61EFh
Mailbox 29
61F0h- 61F7h
Mailbox 30
61F8h- 61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)

61E8h- 61E9h
Message Identifier - MSGID
61EAh- 61EBh
Message Control - MSGCTRL
61ECh- 61EDh
Message Data Low - MDL
61EEh- 61EFh
Message Data High - MDH
Figure 4 - 7. eCAN Memory Map
SPRS174J
67
Peripherals
The CAN registers listed in Table 5 - 6 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 5 - 6. CAN Registers Map
REGISTER NAME
ADDRESS
SIZE
(x32)
DESCRIPTION
CANME
0x00 6000
Mailbox enable
CANMD
0x00 6002
Mailbox direction
CANTRS
0x00 6004
Transmit request set
CANTRR
0x00 6006
Transmit request reset
CANTA
0x00 6008
Transmission acknowledge
CANAA
0x00 600A
Abort acknowledge
CANRMP
0x00 600C
Receive message pending
CANRML
0x00 600E
Receive message lost
CANRFP
0x00 6010
Remote frame pending
CANGAM
0x00 6012
Global acceptance mask
CANMC
0x00 6014
Master control
CANBTC
0x00 6016
Bit-timing configuration
CANES
0x00 6018
Error and status
CANTEC
0x00 601A
Transmit error counter
CANREC
0x00 601C
Receive error counter
CANGIF0
0x00 601E
Global interrupt flag 0
CANGIM
0x00 6020
Global interrupt mask
CANGIF1
0x00 6022
Global interrupt flag 1
CANMIM
0x00 6024
Mailbox interrupt mask
CANMIL
0x00 6026
Mailbox interrupt level
CANOPC
0x00 6028
Overwrite protection control
CANTIOC
0x00 602A
TX I/O control
CANRIOC
0x00 602C
RX I/O control
CANTSC
0x00 602E
Time stamp counter (Reserved in SCC mode)
CANTOC
0x00 6030
Time-out control (Reserved in SCC mode)
CANTOS
0x00 6032
Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.
68
SPRS174J
Peripherals
4.5
Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
HIghly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
McBSP clock rate = CLKG =

CLKR.
CLKSRG
, where CLKSRG source could be LSPCLK, CLKX, or
(1 ) CLKGDIV)
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit20-MHz maximum.
SPRS174J
69
Peripherals
Figure 4 - 8 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x
version of Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
MXINT
To CPU
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO _15
TX FIFO _15
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
DXR2 Transmit Buffer
LSPCLK
McBSP Registers
and Control Logic
16
DXR1 Transmit Buffer
CLKX
XSR2
XSR1
DX
RSR2
RSR1
DR
16
CLKR
Expand Logic
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
To CPU
RX Interrupt Logic
RX FIFO
Interrupt
FSX
16
Compand Logic
16
McBSP
16
FSR
16
RX FIFO _15
RX FIFO _15
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4 - 8. McBSP Module With FIFO
70
SPRS174J
Peripherals
Table 5 - 7 provides a summary of the McBSP registers.

Table 5 - 7. McBSP Register Summary
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT

-
0x0000
McBSP Receive Buffer Register
0x0000
McBSP Receive Shift Register
0x0000
McBSP Transmit Shift Register
DRR2
00
0x0000
McBSP Data Receive Register 2

- Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1
01
0x0000
McBSP Data Receive Register 1

- Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
0x0000
McBSP Data Transmit Register 2

- Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
0x0000
McBSP Data Transmit Register 1

- Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS

SPCR2
04
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
05
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
06
R/W
0x0000
McBSP Receive Control Register 2
RCR1
07
R/W
0x0000
McBSP Receive Control Register 1
XCR2
08
R/W
0x0000
McBSP Transmit Control Register 2
XCR1
09
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0B
R/W
0x0000
McBSP Sample Rate Generator Register 1
MCR2
0C
R/W
0x0000
McBSP Multichannel Register 2
MULTICHANNEL CONTROL REGISTERS

MCR1
0D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
10
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
11
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR1
12
R/W
0x0000
McBSP Pin Control Register
RCERC
13
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
14
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
15
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
16
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
SPRS174J
71
Peripherals
Table 5 - 7. McBSP Register Summary (Continued)

NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
RCERE
17
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
RCERF
18
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
XCERE
19
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
XCERF
1A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
RCERG
1B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
RCERH
1C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
XCERG
1D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
XCERH
1E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)

FIFO Data Registers
DRR2
00
0x0000
McBSP Data Receive Register 2 - Top of receive FIFO

- Read First FIFO pointers will not advance
DRR1
01
0x0000
McBSP Data Receive Register 1 - Top of receive FIFO

- Read Second for FIFO pointers to advance
DXR2
02
0x0000
McBSP Data Transmit Register 2 - Top of transmit FIFO

- Write First FIFO pointers will not advance
DXR1
03
0x0000
McBSP Data Transmit Register 1 - Top of transmit FIFO

- Write Second for FIFO pointers to advance
MFFTX
20
R/W
0xA000
McBSP Transmit FIFO Register
MFFRX
21
R/W
0x201F
McBSP Receive FIFO Register
FIFO Control Registers
MFFCT
22
R/W
0x0000
McBSP FIFO Control Register
MFFINT
23
R/W
0x0000
McBSP FIFO Interrupt Register
MFFST
24
R/W
0x0000
McBSP FIFO Status Register
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
72
SPRS174J
Peripherals
4.6
Serial Communications Interface (SCI) Module

The F281x and C281x devices include two serial communications interface (SCI) modules. The SCI modules
support digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
Two external pins:

-
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE:
Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates

-
Baud rate =
=
LSPCLK , when BRR 0

(BRR ) 1) * 8
LSPCLK ,
when BRR = 0
16
Data-word format
-
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
-
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
Max bit rate + 150 MHz + 9.375

2 8
10 6 bs
than the I/O buffer speed limit20 MHz maximum.
SPRS174J
73
Peripherals
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7 - 0), and the upper byte (15 - 8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced features:
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 5 - 8 and Table 5 - 9.
Table 5 - 8. SCI-A Registers
NAME
ADDRESS
SIZE (x16)
SCICCRA
0x00 7050
SCI-A Communications Control Register
DESCRIPTION
SCICTL1A
0x00 7051
SCI-A Control Register 1
SCIHBAUDA
0x00 7052
SCI-A Baud Register, High Bits
SCILBAUDA
0x00 7053
SCI-A Baud Register, Low Bits
SCICTL2A
0x00 7054
SCI-A Control Register 2
SCIRXSTA
0x00 7055
SCI-A Receive Status Register
SCIRXEMUA
0x00 7056
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x00 7057
SCI-A Receive Data Buffer Register
SCITXBUFA
0x00 7059
SCI-A Transmit Data Buffer Register
SCIFFTXA
0x00 705A
SCI-A FIFO Transmit Register
SCIFFRXA
0x00 705B
SCI-A FIFO Receive Register
SCIFFCTA
0x00 705C
SCI-A FIFO Control Register
SCIPRIA
0x00 705F
SCI-A Priority Control Register
Shaded registers are new registers for the FIFO mode.
Table 5 - 9. SCI-B Registers

NAME
ADDRESS
SIZE (x16)
SCICCRB
0x00 7750
SCI-B Communications Control Register
DESCRIPTION
SCICTL1B
0x00 7751
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
SCI-B Control Register 2
SCIRXSTB
0x00 7755
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
SCI-B Transmit Data Buffer Register
SCIFFTXB
0x00 775A
SCI-B FIFO Transmit Register
SCIFFRXB
0x00 775B
SCI-B FIFO Receive Register
SCIFFCTB
0x00 775C
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
SCI-B Priority Control Register
Shaded registers are new registers for the FIFO mode.

NOTE: The above registers are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
74
SPRS174J
Peripherals
Figure 4 - 9 shows the SCI module block diagram.

SCICTL1.1
SCITXD
Frame Format and Mode

Parity
Even/Odd Enable
TXSHF
Register
8
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
TXENA
TXRDY
Transmitter- Data
Buffer Register
SCICTL2.0
TXINT
TX Interrupt
Logic
TX FIFO _1
-----
TX FIFO _15
WUT
TX INT ENA
SCICTL2.7
TX FIFO
Interrupts
TX FIFO _0
SCITXD
TX EMPTY
SCICTL2.6
To CPU
SCI TX Interrupt select logic
SCITXBUF.7 - 0
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7 - 0
RXRDY
BRKDT
RX FIFO _15
----RX FIFO_1
RX FIFO _0
SCIRXBUF.7 - 0
RX/BK INT ENA
SCIRXST.6
RX FIFO
Interrupts
SCIRXST.5
RX Interrupt
Logic
To CPU
RX FIFO registers
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
RXFFOVF
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4 - 9. Serial Communications Interface (SCI) Module Block Diagram
SPRS174J
75
Peripherals
4.7
Serial Peripheral Interface (SPI) Module

The F281x and C281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a
high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen
bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
Four external pins:

-
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates

-
Baud rate =
=
LSPCLK
, when BRR 0
(SPIBRR ) 1)
LSPCLK ,
when BRR = 0, 1, 2, 3
4
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
-
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7 - 0), and the upper byte (15 - 8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced feature:
76
16-level transmit/receive FIFO
Delayed transmit control
than the I/O buffer speed limit20 MHz maximum.
SPRS174J
Peripherals
The SPI port operation is configured and controlled by the registers listed in Table 5 - 10.
Table 5 - 10. SPI Registers
NAME
ADDRESS
SIZE (x16)
SPICCR
0x00 7040
SPI Configuration Control Register
DESCRIPTION
SPICTL
0x00 7041
SPI Operation Control Register
SPISTS
0x00 7042
SPI Status Register
SPIBRR
0x00 7044
SPI Baud Rate Register
SPIRXEMU
0x00 7046
SPI Receive Emulation Buffer Register
SPIRXBUF
0x00 7047
SPI Serial Input Buffer Register
SPITXBUF
0x00 7048
SPI Serial Output Buffer Register
SPIDAT
0x00 7049
SPI Serial Data Register
SPIFFTX
0x00 704A
SPI FIFO Transmit Register
SPIFFRX
0x00 704B
SPI FIFO Receive Register
SPIFFCT
0x00 704C
SPI FIFO Control Register
SPIPRI
0x00 704F
SPI Priority Control Register
NOTE: The above registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
SPRS174J
77
Peripherals
Figure 4 - 10 is a block diagram of the SPI in slave mode.

SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
-----
SPIINT/SPIRXINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
-----
TX Interrupt
Logic
TX FIFO Interrupt
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
SPIDAT.15 - 0
SW1
SPISIMO
M
S
SW2
SPISOMI
Talk
SPICTL.1
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 - 0
3
SW3
M
SPI Bit Rate

LSPCLK
SPIBRR.6 - 0
6
SPICTL.2
S
M
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
SPISTE is driven low by the master for a slave device.
Figure 4 - 10. Serial Peripheral Interface Module Block Diagram (Slave Mode)
78
SPRS174J
Peripherals
4.8
GPIO MUX
The GPIO Mux registers, are used to select the operation of shared pins on the F281x and C281x devices.
The pins can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via
the GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction
(via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL)
registers). Table 5 - 11 lists the GPIO Mux Registers.
Table 5 - 11. GPIO Mux Registers
NAME
ADDRESS
SIZE (x16)
GPAMUX
0x00 70C0
GPIO A Mux Control Register
REGISTER DESCRIPTION
GPADIR
0x00 70C1
GPIO A Direction Control Register
GPAQUAL
0x00 70C2
GPIO A Input Qualification Control Register
reserved
0x00 70C3
GPBMUX
0x00 70C4
GPIO B Mux Control Register
GPBDIR
0x00 70C5
GPIO B Direction Control Register
GPBQUAL
0x00 70C6
GPIO B Input Qualification Control Register
reserved
0x00 70C7
reserved
0x00 70C8
reserved
0x00 70C9
reserved
0x00 70CA
reserved
0x00 70CB
GPDMUX
0x00 70CC
GPIO D Mux Control Register
GPDDIR
0x00 70CD
GPIO D Direction Control Register
GPDQUAL
0x00 70CE
GPIO D Input Qualification Control Register
reserved
0x00 70CF
GPEMUX
0x00 70D0
GPIO E Mux Control Register
GPEDIR
0x00 70D1
GPIO E Direction Control Register
GPEQUAL
0x00 70D2
GPIO E Input Qualification Control Register
reserved
0x00 70D3
GPFMUX
0x00 70D4
GPIO F Mux Control Register
GPFDIR
0x00 70D5
GPIO F Direction Control Register
reserved
0x00 70D6
reserved
0x00 70D7
GPGMUX
0x00 70D8
GPIO G Mux Control Register
GPGDIR
0x00 70D9
GPIO G Direction Control Register
reserved
0x00 70DA
reserved
0x00 70DB
reserved
0x00 70DC
0x00 70DF
Reserved locations will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
SPRS174J
79
Peripherals
If configured for Digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 5 - 12 lists the GPIO Data Registers. For more information, see the TMS320F28x System
Control and Interrupts Peripheral Reference Guide (literature number SPRU078).
Table 5 - 12. GPIO Data Registers
NAME
ADDRESS
SIZE (x16)
GPADAT
0x00 70E0
GPIO A Data Register
REGISTER DESCRIPTION
GPASET
0x00 70E1
GPIO A Set Register
GPACLEAR
0x00 70E2
GPIO A Clear Register
GPATOGGLE
0x00 70E3
GPIO A Toggle Register
GPBDAT
0x00 70E4
GPIO B Data Register
GPBSET
0x00 70E5
GPIO B Set Register
GPBCLEAR
0x00 70E6
GPIO B Clear Register
GPBTOGGLE
0x00 70E7
GPIO B Toggle Register
reserved
0x00 70E8
reserved
0x00 70E9
reserved
0x00 70EA
reserved
0x00 70EB
GPDDAT
0x00 70EC
GPIO D Data Register
GPDSET
0x00 70ED
GPIO D Set Register
GPDCLEAR
0x00 70EE
GPIO D Clear Register
GPDTOGGLE
0x00 70EF
GPIO D Toggle Register
GPEDAT
0x00 70F0
GPIO E Data Register
GPESET
0x00 70F1
GPIO E Set Register
GPECLEAR
0x00 70F2
GPIO E Clear Register
GPETOGGLE
0x00 70F3
GPIO E Toggle Register
GPFDAT
0x00 70F4
GPIO F Data Register
GPFSET
0x00 70F5
GPIO F Set Register
GPFCLEAR
0x00 70F6
GPIO F Clear Register
GPFTOGGLE
0x00 70F7
GPIO F Toggle Register
GPGDAT
0x00 70F8
GPIO G Data Register
GPGSET
0x00 70F9
GPIO G Set Register
GPGCLEAR
0x00 70FA
GPIO G Clear Register
GPGTOGGLE
0x00 70FB
GPIO G Toggle Register
reserved
0x00 70FC
0x00 70FF
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
80
SPRS174J
Peripherals
Figure 4 - 11 shows how the various register bits select the various modes of operation.
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
GPxQUAL
Register
Digital I/O
GPxMUX
Register Bit
Peripheral I/O
HighImpedance
Control
GPxDIR
Register Bit
1
MUX
1
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
Boundary Off
XRS
Internal (Pullup or Pulldown)
PIN
NOTES: A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value
written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the
corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0s or all 1s). This feature
removes unwanted spikes from the input signal.
Figure 4 - 11. Modes of Operation

CAUTION:
The input function of the GPIO pin and the input path to the peripheral are always
enabled. It is the output function of the GPIO pin that is multiplexed with the output path
of the primary (peripheral) function. Since the output buffer of a pin connects back to
the input buffer, any GPIO signal present at the pin will be propagated to the peripheral
module as well. Therefore, when a pin is configured for GPIO operation, the
corresponding peripheral functionality (and interrupt-generating capability) must be
disabled. Otherwise, interrupts may be inadvertently triggered. This is especially
critical when the PDPINTA and PDPINTB pins are used as GPIO pins, since a value of
zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a high-impedance
state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM pins in high
impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.
SPRS174J
81
Development Support
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F281x- and C281x-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/C++/Assembly debugger and code profiler
Hardware Development Tools:
SPI515
XDS510PP, XDS510PP Plus, XDS510 USB
Development tools for the 28x are as follows:
5.1
Code Composer Studio Integrated Development Environment (IDE) Version 2.x

-
Code Composer Studio Version 2.0 Debugger
Code Generation Tools
Assembler/Linker
C/C++ Compiler
Cycle Accurate Simulator
JTAG-Based Emulator
Sample Applications Code
Universal 5-V DC Power Supply
Documentation and Cables
Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final devices electrical specifications
TMP
Final silicon die that conforms to the devices electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMS320 is a trademark of Texas Instruments.
82
SPRS174J
Development Support
TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TIs standard warranty applies.
Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PBK) and temperature range (for example, A). Figure 5 - 1 provides a legend for reading
the complete device name for any TMS320x28x family member.
TMS 320
2810
PBK
PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device
DEVICE FAMILY
320 = TMS320 DSP Family
TECHNOLOGY
F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
C = ROM (1.8-V/1.9-V Core/3.3-V I/O)
BGA =
LQFP =
TEMPERATURE RANGE
A
S
=
=
- 40C to 85C
- 40C to 125C
PACKAGE TYPE
GHH = 179-ball MicroStar BGA
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2810
2811
2812
Ball Grid Array

Low-Profile Quad Flatpack
Figure 5 - 1. TMS320x28x Device Nomenclature
SPRS174J
83
Documentation Support
Documentation Support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets
and data manuals, with design specifications; and hardware and software applications. Useful reference
documentation includes:
3.3-V DSP for Digital Motor Control application report (literature number SPRA550)
TMS320F28x DSP Serial Communication Interface (SCI) Reference Guide (literature number SPRU051)
TMS320F28x DSP Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059)
TMS320F28x Analog-to-Digital
number SPRU060)
TMS320F28x DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature
number SPRU061)
TMS320F28x DSP Event Manager (EV) Reference Guide (literature number SPRU065)
TMS320F28x DSP External Interface (XINTF) Reference Guide (literature number SPRU067)
TMS320F28x DSP Enhanced Controller Area Network (eCAN) Reference Guide (literature
number SPRU074)
TMS320F28x System Control and Interrupts Peripheral Reference Guide (literature number SPRU078)
TMS320F28x DSP Boot ROM Reference Guide (literature number SPRU095)
TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430)
TMS320F28x DSP Peripherals Reference Guide (literature number SPRU566)
TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608)
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number
SPRU625)
TMS320C28x Assembly Language Tools Users Guide (SPRU513)
TMS320C28x Optimizing C/C++ Compiler Users Guide (SPRU514)
Converter
(ADC)
Peripheral
Reference
Guide
(literature
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number SPRS174),
use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and
support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
84
SPRS174J
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F281x and TMS320C281x DSPs.
7.1
Absolute Maximum Ratings

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature
ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Section 7.2 is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
Supply voltage range, VDDIO , VDDA1, VDDA2, VDDAIO, and AVDDREFBG . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V
Supply voltage range, VDD, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 2.5 V
VDD3VFL range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V
Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating ambient temperature ranges, TA: A version (GHH, PGF, PBK) . . . . . . . . . . . . . . - 40C to 85C
TA: S version (GHH, PGF, PBK) . . . . . . . . . . . . . - 40C to 125C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Continous clamp current per pin is 2 mA

Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
SPRS174J
85
Recommended Operating Conditions
7.2
VDDIO
Device supply voltage, I/O
MAX
UNIT
V
3.14
3.3
3.47
1.8 V (135 MHz)
1.71
1.8
1.89
1.9 V (150 MHz)
1.81
1.9
Device supply voltage,

voltage CPU
VSS
Supply ground
VDDA1 , VDDA2 ,
AVDDREFBG, VDDAIO
ADC supply voltage
3.14
3.3
3.47
VDD3VFL
Flash programming supply voltage
3.14
3.3
3.47
fSYSCLKOUT
Device clock frequency

(system clock)
VIH
High level input voltage

High-level
VIL
Low level input voltage

Low-level
IOH
High level output source current,

High-level
VOH = 2.4 V
All I/Os except Group 2
-4
Group 2
-8
IOL
Low-level
Low
level output sink current,
VOL = VOL MAX
All I/Os except Group 2
Group 2
TA
Ambient
temperature
VDD = 1.9 V 5%
150
VDD = 1.8 V 5%
135
VDDIO
0.7VDD
VDD
All inputs except XCLKIN

XCLKIN (@ 50 A max)
All inputs except XCLKIN
0.8
XCLKIN (@ 50 A max)
0.3VDD
A version
- 40
85
S version
- 40
125
MHz
V
V
mA
mA
C
See Section 7.8 for power sequencing of VDDIO , VDDAIO , VDD , VDDA1 / VDDA2 /AVDDREFBG , and VDD3VFL .
Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
In Revision C, EVA (GPIOA0 - GPIOA15) and GPIOD0 are 4 mA drive.
7.3
Electrical Characteristics Over Recommended Operating Conditions

(Unless Otherwise Noted)
PARAMETER
VOH
High level output voltage

High-level
VOL
Low level output voltage

Low-level
IIL
NOM
VDD , VDD1
MIN
IInputt currentt
(low level)
TEST CONDITIONS
IOH = IOHMAX
MIN
TYP
MAX
2.4
IOH = 50 A
UNIT
V
VDDIO - 0.2
IOL = IOLMAX
04
0.4
All I/Os except EVB
- 80
- 140
- 190
GPIOB/EVB
- 13
- 25
- 35
With pullup
VDDIO = 3.3 V,
VIN = 0 V
With pulldown
VDDIO = 3.3 V, VIN = 0 V
With pullup
VDDIO = 3.3 V, VIN = VDD
With pulldown
VDDIO = 3.3 V,
VIN = VDD
V
A
IIH
Input current
(high level)
IOZ
Output current, high-impedance

state (off-state)
Ci
Input capacitance
pF
Co
Output capacitance
pF
28
50
80
2
VO = VDDIO or 0 V
The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST..
86
SPRS174J
7.4

During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320F281x)
MODE
TEST CONDITIONS
Operational
All peripheral clocks are

enabled. All PWM pins are
toggled at 100 kHz.
Data is continuously
transmitted out of the
SCIA, SCIB, and CAN
ports. The hardware
multiplier is exercised.
Code is running out of
flash with 5 wait-states.
IDLE
STANDBY
IDDIO
IDDA
IDD3VFL
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
195 mA
230 mA
15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
Flash is powered down

XCLKOUT is turned off
All peripheral clocks
are on, except ADC
125 mA
150 mA
5 mA
10 mA
2 A
4 A
1 A
20 A

Peripheral clocks are
turned off
Pins without an internal
PU/PD are tied
high/low
5 mA
10 mA
5 A
20 A
2 A
4 A
1 A
20 A

turned off
PU/PD are tied
high/low
Input clock is disabled
70 A
5 A
20 A
2 A
4 A
1 A
20 A
HALT
IDD
IDDA includes current into VDDA1, VDDA2, AVDDREFBG , and VDDAIO pins.
MAX numbers are at 125C, and max voltage (V
DD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
SPRS174J
87
7.5

During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320C281x)
MODE
Operational
IDLE
STANDBY
All peripheral clocks are enabled. All PWM pins

are toggled at 100 kHz.
Data is continuously transmitted out of the SCIA,
SCIB, and CAN ports. The hardware multiplier is
exercised.
Code is running out of ROM with 5 wait-states.
MAX
MAX
TYP
TYP
160 mA
10 mA
40 mA
XCLKOUT is turned off

All peripheral clocks
are on, except ADC
125 mA
5 mA
1 A

turned off
PU/PD are tied
high/low
3 mA
5 A
1 A

turned off
PU/PD are tied
high/low
Input clock is disabled
10 A
5 A
1 A
TYP
IDDA
IDDIO
HALT
IDD
TEST CONDITIONS
MAX
IDDA includes current into VDDA1, VDDA2, AVDDREFBG , and VDDAIO pins.
88
SPRS174J
7.6
Current Consumption Graphs
Current Vs Frequency
300
Current (mA)
250
200
150
100
50
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
SYSCLKOUT (MHz)
IDD
Legend:
IDDIO
IDD3VFL
IDDA1
TOTAL
NOTES: A. Flash uses five wait-states for paged and random access for frequencies above 5 MHz. For frequencies of 1 to
5 MHz, it was made to operate at zero wait-states.
B. ADC operates at SYSCLKOUT/6 for frequencies above 5 MHz. For frequencies of 1 to 5 MHz, it was made to
operate at SYSCLKOUT.
Figure 7 - 1. F2812/F2811/F2810 Typical Current Consumption (With Peripheral Clocks Enabled)
7.7
Reducing Current Consumption

28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 7 - 1 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals.
Table 7 - 1. Typical Current Consumption by Various Peripherals (at 150 MHz)
PERIPHERAL MODULE
IDD CURRENT REDUCTION (mA)
eCAN
12
EVA
EVB
ADC
SCI
SPI
McBSP
13
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks
are turned on.
SPRS174J
89
This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the
elimination of the current drawn by the analog portion of the ADC (ICCA) as well.
7.8
Power Sequencing Requirements

TMS320F2812/F2811/F2810/C2812/C2811/C2810 silicon requires dual voltages (1.8-V, 1.9-V, and 3.3-V) to
power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during
power up, there are some requirements to be met while powering up/powering down the device. The current
F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp board) suggests two options for
the power sequencing circuit.
Option 1:
In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or
1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG )
modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the
recommended approach.
Option 2:
Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then
ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset
signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules
inside the device. See Figure 7 - 7 for power-on reset timing.
Power-Down Sequencing:
During power-down, the device reset should be asserted low (8 s, minimum) before the VDD supply
reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies
ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or
voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with
the aid of additional external components) may be used to meet the power sequencing requirement. See
www.spectrumdigital.com for F2812 eZdsp schematics and updates.
Table 7 - 2. Recommended Low-Dropout Regulators
SUPPLIER
PART NUMBER
Texas Instruments
TPS767D301
CAUTION:
The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.
eZdsp is a trademark of Spectrum Digital Incorporated.

90
SPRS174J
2.5 V
(see Note A)
See Note C
3.3 V
3.3 V
VDD_3.3V
<10 ms
1.8 V (or
1.9 V)
1.5 V
1.8 V (or
1.9 V)
VDD_1.8V
>1 ms
See Note B
> 8 s
XRS
See Note D
XRS
Power-Up Sequence
VDD_3.3V
VDD_1.8V
Power-Down Sequence
VDDIO , VDD3VFL , VDDAIO , VDDA1 , VDDA2 , AVDDREFBG

VDD , VDD1
NOTES: A. 1.8-V (or 1.9 V) supply should ramp after the 3.3-V supply reaches at least 2.5 V.
B. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 7 - 7, Power-on Reset in Microcomputer Mode
(XMP/MC = 0), for minimum requirements.
C. Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this occurs
a few milliseconds before the 1.8-V (or 1.9 V) supply reaches 1.5 V.
D. Keeping reset low (XRS) at least 8 s prior to the 1.8-V (or 1.9 V) supply reaching 1.5 V will keep the flash module in complete
reset before the supplies ramp down.
E. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9 V) supply reaches at least 1 V, this supply should be ramped
as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).
F. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.
Figure 7 - 2. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence - Option 2
SPRS174J
91
7.9
Signal Transition Levels

The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.4 V.
Figure 7 - 3 shows output levels.
2.4 V (VOH)
80%
20%
0.4 V (VOL)
Figure 7 - 3. Output Levels

Output transition times are specified as follows:
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total
voltage range and higher and the level at which the output is said to be high is 80% of the total voltage
range and higher.
Figure 7 - 4 shows the input levels.

2.0 V (VIH)
90%
10%
0.8 V (VIL)
Figure 7 - 4. Input Levels

Input transition times are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the
total voltage range and lower.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the
total voltage range and higher.
NOTE: See the individual timing diagrams for levels used for testing timing parameters.
92
SPRS174J
7.10 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
7.11
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
access time
High
cycle time (period)
Low
delay time
Valid
fall time
Unknown, changing, or dont care level
hold time
High impedance
rise time
su
setup time
transition time
valid time
pulse duration (width)
General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this document.
7.12 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42
3.5 nH
Transmission Line
Z0 = 50
(see note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 7 - 5. 3.3-V Test Load Circuit
SPRS174J
93
7.13 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options
available on the F281x and C281x DSPs. Table 7 - 3 lists the cycle times of various clocks.
Table 7 - 3. TMS320F281x and TMS320C281x Clock Table and Nomenclature
MIN
On chip oscillator clock
On-chip
XCLKIN
SYSCLKOUT
XCLKOUT
HSPCLK
LSPCLK
ADC clock
SPI clock
McBSP
XTIMCLK
tc(OSC) , Cycle time

Frequency
tc(CI) , Cycle time
Frequency
tc(SCO) , Cycle time
Frequency
tc(XCO) , Cycle time
Frequency
tc(HCO) , Cycle time
35
MHz
ns
150
MHz
6.67
500
ns
150
MHz
6.67
2000
ns
0.5
150
MHz
6.67
13.3
Frequency
ns
150
26.6
37.5
MHz
ns
75
40
MHz
ns
25
MHz
20
MHz
20
MHz
50
ns
50
Frequency
tc(XTIM) , Cycle time
13.3
75
Frequency
tc(CKG) , Cycle time
ns
250
Frequency
tc(SPC) , Cycle time
UNIT
50
20
Frequency
tc(ADCCLK) , Cycle time
MAX
6.67
Frequency
tc(LCO) , Cycle time
NOM
28.6
ns
6.67
ns
150
MHz
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower.
ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
This is the default reset vallue if SYSCLKOUT = 150 MHz.
94
SPRS174J
7.14 Clock Requirements and Characteristics

7.14.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 7 - 4. Input Clock Frequency
PARAMETER
fx
MIN
Input clock frequency
fl
TYP
MAX
Resonator
20
Crystal
20
35
XCLKIN
150
UNIT
35
Limp mode clock frequency
MHz
MHz
Table 7 - 5. XCLKIN Timing Requirements - PLL Bypassed or Enabled

NO.
MIN
MAX
UNIT
6.67
250
ns
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time,
time XCLKIN
C10
tr(CI)
Rise time,
time XCLKIN
C11
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
40
60
C12
tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
60
MIN
MAX
UNIT
6.67
250
ns
Up to 30 MHz
Up to 150 MHz
Up to 30 MHz
Up to 150 MHz
ns
ns
Table 7 - 6. XCLKIN Timing Requirements - PLL Disabled

NO.
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time,
time XCLKIN
C10
tr(CI)
(C )
time XCLKIN
Rise time,
C11
tw(CIL)
Pulse duration,
duration X1/XCLKIN low as a percentage of tc(CI)
C12
tw(CIH)
Pulse duration,
duration X1/XCLKIN high as a percentage of tc(CI)
Up to 30 MHz
Up to 150 MHz
Up to 30 MHz
Up to 150 MHz
XCLKIN 120 MHz
40
60
120 < XCLKIN 150 MHz
45
55
XCLKIN 120 MHz
40
60
120 < XCLKIN 150 MHz
45
55
ns
ns
%
Table 7 - 7. Possible PLL Configuration Modes

PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value n into PLLCR register. The /2 module

in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
XCLKIN
SPRS174J
95
7.14.2 Output Clock Characteristics

Table 7 - 8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
No.
PARAMETER
MIN
TYP
MAX
6.67
C1
tc(XCO)
Cycle time, XCLKOUT
C3
tf(XCO)
Fall time, XCLKOUT
C4
tr(XCO)
Rise time, XCLKOUT
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H-2
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H-2
C7
tp
PLL lock time
UNIT
ns
ns
ns
H+2
ns
H+2
ns
131 072tc(CI)
ns
A load of 40 pF is assumed for these parameters.

H = 0.5tc(XCO)
The PLL must be used for maximum frequency operation.
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
C10
C9
C8
XCLKIN
C6
C3
C1
C4
C5
XCLKOUT
(see Note A)
NOTES: A. XCLKOUT configured to reflect SYSCLKOUT.
B. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 7 - 6 is
intended to illustrate the timing parameters only and may differ based on configuration.
Figure 7 - 6. Clock Timing
7.15 Reset Timing

Table 7 - 9. Reset (XRS) Timing Requirements
MIN
NOM
UNIT
Pulse duration, stable XCLKIN to XRS high
tw(RSL2)
Pulse duration,
duration XRS low
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST
Oscillator start-up time
tsu(XPLLDIS)
Setup time for XPLLDIS pin
16tc(CI)
cycles
th(XPLLDIS)
Hold time for XPLLDIS pin
16tc(CI)
cycles
th(XMP/MC)
Hold time for XMP/MC pin
16tc(CI)
cycles
2520tc(CI)
cycles
th(boot-mode)
Hold time for boot-mode pins
8tc(CI)
MAX
tw(RSL1)
Warm reset
cycles
8tc(CI)
WD-initiated reset
512tc(CI)
cycles
512tc(CI)
cycles
32tc(CI)
cycles
10
ms
Dependent on crystal/resonator and board design.

The boot ROM reads the password loacations. Therefore, this timing requirement includes the wakeup time for flash. Refer to SPRU095A and
SPRU078A for further information.
NOTE: If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
96
SPRS174J
VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
VDD, VDD1
(1.8 V (or 1.9 V))
2.5 V
0.3 V
XCLKIN
X1
XCLKIN/8
XCLKOUT
User-Code Dependent
tOSCST
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase

Address/Data/
Control
td(EX)
tsu(XPLLDIS)
XPLLDIS Sampling
XF/XPLLDIS
User-Code Execution Phase

User-Code Dependent
th(XPLLDIS)
(Dont Care)
GPIOF14
th(XMP/MC)
XMP/MC
(Dont Care)
th(boot-mode)
User-Code Dependent
Boot-Mode Pins
GPIO Pins as Input
See NOTE
Boot-ROM Execution Starts
I/O Pins
Peripheral/GPIO Function
Based on Boot Code
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
VDDAn - VDDA1/VDDA2 and AVDDREFBG
Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
XCLKIN/8 during this phase.
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT
Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The
BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot
modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
NOTE: The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V.
Figure 7 - 7. Power-on Reset in Microcomputer Mode (XMP/MC = 0)
SPRS174J
97
VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
VDD, VDD1 (1.8 V (or
1.9 V))
2.5 V
0.3 V
XCLKIN
X1
tOSCST
XCLKOUT
XCLKIN/8
tw(RSL)
XRS
td(EX)
Address/Data/
Control
(Dont Care)
XF/XPLLDIS
(Dont Care)
XPLLDIS Sampling
User-Code Dependent
Address/Data/Control Valid Execution

Begins From ExternalBoot Address 0x3FFFC0
th(XPLLDIS)
GPIOF14/XF (User-Code Dependent)
tsu(XPLLDIS)
XMP/MC
th(XMP/MC)
I/O Pins
(Dont Care)
User-Code Dependent
See NOTE
Input Configuration (State Depends on Internal PU/PD)
Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = XCLKIN/8
during this phase.
NOTE: The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V and
3.3-V supply reaches 2.5 V..
Figure 7 - 8. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
98
SPRS174J
XCLKIN
X1
XCLKIN/8
XCLKOUT
(XCLKIN * 5)
User-Code Dependent
tw(RSL2)
XRS
td(EX)
Address/Data/
Control
User-Code Execution
(Dont Care)
tsu(XPLLDIS)
XF/XPLLDIS
XMP/MC
GPIOF14/XF
(Dont Care)
th(XPLLDIS)
(Dont Care)
XPLLDIS Sampling
th(XMP/MC)
Boot-ROM Execution Starts

Boot-Mode Pins
User-Code Execution Phase
GPIO Pins as Input
GPIOF14
User-Code Dependent
(Dont Care)
th(boot-mode)
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT
Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The
BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot
modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 7 - 9. Warm Reset in Microcomputer Mode
SPRS174J
99
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN*2
XCLKIN/2
XCLKIN*4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing

With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131 072 XCLKIN Cycles Long.)
(Changed CPU Frequency)
Figure 7 - 10. Effect of Writing Into PLLCR Register
100
SPRS174J
7.16 Low-Power Mode Wakeup Timing

Table 7 - 10 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 7 - 10. IDLE Mode Switching Characteristics
PARAMETER
tw(WAKE-INT)
Pulse duration, external wake-up

signal
TEST CONDITIONS
MIN
Without input qualifier
2 * tc(SCO)
Cycles
1 * tc(SCO) + IQT
Cycles
8 * tc(SCO)
Cycles
8 * tc(SCO) + IQT
Cycles
1050*tc(SCO)
Cycles
1050 * tc(SCO) + IQT
Cycles
8 * tc(SCO)
Cycles
IQT
Cycles
With input qualifier
TYP
MAX
UNIT
Delay time, external wake signal to

program execution resume
td(WAKE-IDLE)
- Wake-up from Flash

- Flash module in active state


- Flash module in sleep state

- Wake-up from SARAM
8 * tc(SCO) +
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
td(WAKE - IDLE)
A0 - A15
XCLKOUT
tw(WAKE - INT)
WAKE INT
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 7 - 11. IDLE Entry and Exit Timing

Table 7 - 11 is also the STANDBY Mode Wake-Up Timing Requirements table.
SPRS174J
101
Table 7 - 11. STANDBY Mode Switching Characteristics

PARAMETER
TEST CONDITIONS
td(IDLE-XCOH)
Delay time, IDLE instruction

executed to XCLKOUT high
tw(WAKE-INT)
Pulse duration, external

wake-up signal
MIN
TYP
32 * tc(SCO)

MAX
35 * tc(SCO)
UNIT
Cycles
2 * tc(CI)
Cycles
(2 + QUALSTDBY) * tc(CI)
Cycles
85 * tc(SCO)
Cycles
85 * tc(SCO) + tw(WAKE-INT)
Cycles
1125 * tc(SCO)
Cycles
1125 * tc(SCO) +
tw(WAKE-INT)
Cycles
35 * tc(SCO)
Cycles
Delay time, external wake

signal to program execution
resume
td(WAKE-STBY)




35 * tc(SCO) + tw(WAKE-INT)
Cycles
QUALSTDBY is a 6-bit field in the LPMCR0 register.

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
B
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake- up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/XCLKIN
td(IDLE - XCOH)
XCLKOUT
32 SYSCLKOUT Cycles
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32 - cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake - up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device will respond to the interrupt (if enabled).
Figure 7 - 12. STANDBY Entry and Exit Timing
102
SPRS174J
Table 7 - 12. HALT Mode Switching Characteristics

PARAMETER
MIN
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2 * tc(CI)
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8 * tc(CI)
tp
32 * tc(SCO)
TYP
MAX
UNIT
45 * tc(SCO)
Cycles
Cycles
Cycles
131 072 * tc(CI) Cycles
PLL lock-up time

Delay time, PLL lock to program execution resume
- Wake-up from flash
td(wake)
1125*tc(SCO)
Cycles
35*tc(SCO)
Cycles

A
B
Device
Status
D
HALT
Flushing Pipeline
G
F
HALT
PLL Lock - up Time
Wake- up Latency
Normal
Execution
XNMI
tw(WAKE - XNMI)
tp
td(INT)
X1/XCLKIN
td(IDLE - XCOH)
Oscillator Start-up Time
XCLKOUT
32 SYSCLKOUT Cycles
XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
Figure 7 - 13. HALT Wakeup Using XNMI
SPRS174J
103
7.17 Event Manager Interface

7.17.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 7 - 13. PWM Switching Characteristics
PARAMETER
TEST CONDITIONS
tw(PWM)
Pulse duration, PWMx output high/low
td(PWM)XCO
Delay time, XCLKOUT high to PWMx output switching
MIN
MAX
25
XCLKOUT = SYSCLKOUT/4
UNIT
ns
10
ns
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
PWM outputs may be 100%, 0%, or increments of t
c(HCO) with respect to the PWM period.
Table 7 - 14. Timer and Capture Unit Timing Requirements#

MIN
MAX
2 * tc(SCO)
UNIT
tw(TDIR)
Pulse duration
duration, TDIRx low/high
tw(CAP)
Pulse duration,
duration CAPx input low/high
tw(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
40
60
tw(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60
tc(TCLKIN)
Cycle time, TCLKINx

cycles
1 * tc(SCO) + IQT||
2 * tc(SCO)
cycles
1 * tc(SCO) + IQT||
4 * tc(HCO)
ns
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is
2n SYSCLKOUT cycles, where n is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
# Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
|| Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
XCLKOUT
td(PWM)XCO
tw(PWM)
PWMx
XCLKOUT = SYSCLKOUT
Figure 7 - 14. PWM Output Timing
XCLKOUT
tw(TDIR)
TDIRx
XCLKOUT = SYSCLKOUT
Figure 7 - 15. TDIRx Timing
104
SPRS174J
Table 7 - 15. External ADC Start-of-Conversion - EVA - Switching Characteristics

MIN
PARAMETER
td(XCOH-EVASOCL)
tw(EVASOCL)
Delay time, XCLKOUT high to EVASOC low
MAX
UNIT
1 * tc(SCO)
cycle
32 * tc(HCO)
Pulse duration, EVASOC low
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVASOCL)
tw(EVASOCL)
EVASOC
Figure 7 - 16. EVASOC Timing

Table 7 - 16. External ADC Start-of-Conversion - EVB - Switching Characteristics
MIN
PARAMETER
td(XCOH-EVBSOCL)
Delay time, XCLKOUT high to EVBSOC low
tw(EVBSOCL)
Pulse duration, EVBSOC low
MAX
UNIT
1 * tc(SCO)
cycle
32 * tc(HCO)
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVBSOCL)
tw(EVBSOCL)
EVBSOC
Figure 7 - 17. EVBSOC Timing
SPRS174J
105
7.17.2 Interrupt Timing

Table 7 - 17. Interrupt Switching Characteristics
PARAMETER
td(PDP-PWM)HZ
td(TRIP-PWM)HZ
td(INT)
MIN
Without input
Delay time, PDPINTx low to PWM qualifier
high-impedance state
Delay time, CxTRIP/TxCTRIP
signals low to PWM
high-impedance state
UNIT
12
ns
1 * tc(SCO) + IQT + 12
Without input
qualifier
3 * tc(SCO)
ns
[2 * tc(SCO)] + IQT
Delay time, INT low/high to interrupt-vector fetch
MAX
tqual + 12tc(XCO)
ns
Table 7 - 18. Interrupt Timing Requirements

MIN
tw(INT)
Pulse duration
duration, INT input low/high
tw(PDP)
(
)
duration PDPINTx input low

Pulse duration,
tw(CxTRIP)
Pulse duration,
duration CxTRIP input low
tw(TxCTRIP)
Pulse duration,
duration TxCTRIP input low
with no qualifier
with qualifier
with no qualifier
with qualifier
with no qualifier
with qualifier
with no qualifier
with qualifier
2 * tc(SCO)
1 * tc(SCO) + IQT
2 * tc(SCO)
1 * tc(SCO) + IQT
2 * tc(SCO)
1 * tc(SCO) + IQT
2 * tc(SCO)
1 * tc(SCO) + IQT
MAX
UNIT
cycles
cycles
cycles
cycles
106
SPRS174J
XCLKOUT
tw(PDP), tw(CxTRIP), tw(TxCTRIP)

TxCTRIP, CxTRIP,
PDPINTx
td(PDP-PWM)HZ , td(TRIP-PWM)HZ
PWM
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Interrupt Vector
A0 - A15
XCLKOUT = SYSCLKOUT
TxCTRIP - T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP
CxTRIP - C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx - PDPINTA or PDPINTB
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin). The
state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
Figure 7 - 18. External Interrupt Timing
SPRS174J
107
7.18 General-Purpose Input/Output (GPIO) - Output Timing

Table 7 - 19. General-Purpose Output Switching Characteristics
MAX
UNIT
td(XCOH-GPO)
Dela time
Delay
time, XCLKOUT high to GPIO lo
low/high
/high
PARAMETER
All GPIOs
MIN
1 * tc(SCO)
cycle
tr(GPO)
Rise time, GPIO switching low to high
All GPIOs
10
ns
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
10
ns
fGPO
Toggling frequency, GPO pins
20
MHz
XCLKOUT
td(XCOH-GPO)
GPIO
tf(GPO)
tr(GPO)
Figure 7 - 19. General-Purpose Output Timing
108
SPRS174J
7.19 General-Purpose Input/Output (GPIO) - Input Timing

See Note A
GPIO
Signal
1
QUALPRD
Sampling Window
SYSCLKOUT
QUALPRD = 1
(2 x SYSCLKOUT cycles) x 5
Output From
Qualifier
NOTES: A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary
from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value n, the qualification sampling
period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin will be sampled). Six consecutive samples
must be of the same value for a given input to be recognized.
B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs
should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur.
Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7 - 20. GPIO Input Qualifier - Example Diagram for QUALPRD = 1

Table 7 - 20. General-Purpose Input Timing Requirements
MIN
tw(GPI)
(G )
Pulse duration
duration, GPIO low/high
All GPIOs
With no qualifier
With qualifier
MAX
2 * tc(SCO)
1 * tc(SCO) + IQT
UNIT
cycles
XCLKOUT
GPIOxn
tw(GPI)
Figure 7 - 21. General-Purpose Input Timing
NOTE:
The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC
pins as well.
SPRS174J
109
SPRS174J
Table 7 - 21. SPI Master Mode External Timing (Clock Phase = 0)

SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
NO.
1
MAX
MIN
MAX
5tc(LCO)
127tc(LCO)
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high

(clock polarity = 0)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
tw(SPCL)M

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) - 10
td(SPCH-SIMO)M
Delay time, SPICLK high to

SPISIMO valid (clock polarity = 0)
- 10
10
- 10
10
td(SPCL-SIMO)M
Delay time, SPICLK low to

SPISIMO valid (clock polarity = 1)
- 10
10
- 10
10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid

after SPICLK low
0.5tc(SPC)M - 10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid

after SPICLK high
0.5tc(SPC)M - 10
tsu(SOMI-SPCL)M
Setup time, SPISOMI before

SPICLK low (clock polarity = 0)
tsu(SOMI-SPCH)M

SPICLK high (clock polarity = 1)
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid

after SPICLK low
0.25tc(SPC)M - 10
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid

after SPICLK high
0.25tc(SPC)M - 10
8
ns
ns
ns
ns
0.5tc(SPC)M + 0.5tc(LCO) - 10
ns
0.5tc(SPC)M + 0.5tc(LCO) - 10
ns
0.5tc(SPC)M - 0.5tc(LCO) - 10
ns
0.5tc(SPC)M - 0.5tc(LCO) - 10
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
UNIT
MIN
tc(SPC)M
SPI WHEN (SPIBRR + 1)

IS ODD AND SPIBRR > 3
110
7.20 SPI Master Mode Timing
1
SPICLK
2
3
SPICLK
4
5
SPISIMO
Master Out Data Is Valid

8
9
SPISOMI
Master In Data
Must Be Valid
SPISTE
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 7 - 22. SPI Master Mode External Timing (Clock Phase = 0)
SPRS174J
111
SPRS174J
SPI WHEN (SPIBRR + 1) IS EVEN

OR SPIBRR = 0 OR 2
NO.
MIN
1
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
MIN
128tc(LCO)

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO) - 10
tw(SPCL)M

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO) - 10
tw(SPCL)M

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) - 10
tw(SPCH)M

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) - 10
tsu(SIMO-SPCH)M
Setup time, SPISIMO data

valid before SPICLK high
0.5tc(SPC)M - 10
tsu(SIMO-SPCL)M
Setup time, SPISIMO data

valid before SPICLK low
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
tv(SPCH-SIMO)M
Valid time, SPISIMO data

valid after SPICLK high
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
tv(SPCL-SIMO)M
Valid time, SPISIMO data

valid after SPICLK low
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
tsu(SOMI-SPCH)M

SPICLK high
tsu(SOMI-SPCL)M

SPICLK low
tv(SPCH-SOMI)M
Valid time, SPISOMI data

valid after SPICLK high
0.25tc(SPC)M - 10
0.5tc(SPC)M - 10
tv(SPCL-SOMI)M
Valid time, SPISOMI data

valid after SPICLK low
0.25tc(SPC)M - 10
10
11
5tc(LCO)
127tc(LCO)
ns
ns
ns
0.5tc(SPC)M - 10
ns
ns
ns
ns
0.5tc(SPC)M - 10
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
4
(SPIBRR ) 1)
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
UNIT
MAX
4tc(LCO)
MAX
SPI WHEN (SPIBRR + 1)

IS ODD AND SPIBRR > 3
112
Table 7 - 22. SPI Master Mode External Timing (Clock Phase = 1)
1
SPICLK
2
3
SPICLK
6
7
Data Valid
Master Out Data Is Valid
SPISIMO
10
11
Master In Data
Must Be Valid
SPISOMI
SPISTE
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 7 - 23. SPI Master External Timing (Clock Phase = 1)
SPRS174J
113
7.21 SPI Slave Mode Timing

Table 7 - 23. SPI Slave Mode External Timing (Clock Phase = 0)
NO.
12
13
14
15
MIN
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid

0.375tc(SPC)S - 10
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S - 10
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low

(clock polarity =0)
0.75tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high

(clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low

0.5tc(SPC)S
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high

0.5tc(SPC)S
16
19
MAX
4tc(LCO)
tc(SPC)S
20
UNIT
ns
ns
ns
ns
ns
ns
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
4
(SPIBRR ) 1)
114
SPRS174J
12
SPICLK
13
14
SPICLK
15
16
SPISOMI Data Is Valid
SPISOMI
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain
low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 7 - 24. SPI Slave Mode External Timing (Clock Phase = 0)
SPRS174J
115
Table 7 - 24. SPI Slave Mode External Timing (Clock Phase = 1)

NO.
12
13
14
17
MIN
Cycle time, SPICLK
tw(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCL)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCH)S
0.5tc(SPC)S - 10
0.5tc(SPC)S
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.125tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high

(clock polarity =0)
0.75tc(SPC)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low

(clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high

0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low

0.5tc(SPC)S
18
21
MAX
tc(SPC)S
22
8tc(LCO)
UNIT
ns
ns
ns
ns
ns
ns
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
4
(SPIBRR ) 1)
12
SPICLK
13
14
SPICLK
17
18
SPISOMI
Data Valid
SPISOMI Data Is Valid

21
22
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 7 - 25. SPI Slave Mode External Timing (Clock Phase = 1)
116
SPRS174J
7.22 External Interface (XINTF) Timing

Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 7 - 25 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 7 - 25. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)
DESCRIPTION
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD x tc(XTIM)
(XRDLEAD x 2) x tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) x tc(XTIM)
(XRDACTIVE x 2 + WS + 1) x tc(XTIM)
TR
Trail period, read access
XRDTRAIL x tc(XTIM)
(XRDTRAIL x 2) x tc(XTIM)
LW
Lead period, write access
XWRLEAD x tc(XTIM)
(XWRLEAD x 2) x tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) x tc(XTIM)
(XWRACTIVE x 2 + WS + 1) x tc(XTIM)
TW
Trail period, write access
XWRTRAIL x tc(XTIM)
(XWRTRAIL x 2) x tc(XTIM)
tc(XTIM) - Cycle time, XTIMCLK

WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zones XTIMING register. These
requirements are in addition to any timing requirements as specified by that devices data sheet. No internal
device hardware is included to detect illegal settings.
If the XREADY signal is ignored (USEREADY = 0), then:

LR tc(XTIM)
LW tc(XTIM)
1. Lead:
These requirements result in the following XTIMING register configuration restrictions:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when not sampling XREADY:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0, 1
Valid
0, 1
SPRS174J
117
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
LR tc(XTIM)
LW tc(XTIM)
1. Lead:
AR 2 x tc(XTIM)
AW 2 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
2. Active:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Examples of valid and invalid timing when using Synchronous XREADY:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0, 1
Invalid
0, 1
Valid
0, 1
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
LR tc(XTIM)
LW tc(XTIM)
1. Lead:
AR 2 x tc(XTIM)
AW 2 x tc(XTIM)
2. Active:
LR + AR 4 x tc(XTIM)
LW + AW 4 x tc(XTIM)
3. Lead + Active:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
or
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Examples of valid and invalid timing when using Asynchronous XREADY:

XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0, 1
Invalid
0, 1
Invalid
Valid
Valid
0, 1
0, 1
Valid
2
1
118
SPRS174J
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 7 - 26.
Table 7 - 26. XINTF Clock Configurations
Mode
SYSCLKOUT
XTIMCLK
XCLKOUT
1
Example:
150 MHz
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
2
Example:
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
3
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
4
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 7 - 26.

XTIMING0
XTIMING1
XTIMING2
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
SYSCLKOUT
C28x
CPU
/2
XTIMCLK
XINTCNF2
(XTIMCLK)
/2
1
0
XINTCNF2
(CLKMODE)
XCLKOUT
1
0
XINTCNF2
(CLKOFF)
Default Value after reset
Figure 7 - 26. Relationship Between XTIMCLK and SYSCLKOUT
7.23 XINTF Signal Alignment to XCLKOUT

For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of
XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency
of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling ege of XCLKOUT. In the XINTF timing tables, the notation XCOHL
is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or XCLKOUT
falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the notation XCOH
is used.
SPRS174J
119
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XR/W active low
XRDL
XRD active low
XWEL
XWE active low
XRDH
XRD inactive high
XWEH
XWE inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead +
active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with
respect to the falling edge of XCLKOUT.
Examples:
120
XRNWL
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
Zone chip-select active low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the
total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd,
then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XZCSL
SPRS174J
XZCSH
Zone chip-select inactive high
XRNWH
XR/W inactive high
7.24 External Interface Read Timing

Table 7 - 27. External Memory Interface Read Switching Characteristics
PARAMETER
MAX
UNIT
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
ns
Hold time, address valid after XRD inactive high
ns
th(XA)XRD
MIN
td(XCOH-XZCSL)
-2
-2
ns
ns
ns
ns
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 7 - 28. External Memory Interface Read Timing Requirements

MIN
MAX
UNIT
14
ns
AR - 12
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
(LR + AR) -
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
12
ns
th(XD)XRD
Hold time, read data valid after XRD inactive high
LR = Lead period, read access. AR = Active period, read access. See Table 7 - 25.
ns
Trail
Active
Lead
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
XR/W
ta(A)
th(XD)XRD
ta(XRD)
DIN
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 7 - 27. Example Read Access

XTIMING register parameters used for this example:
XRDLEAD
1
XRDACTIVE
XRDTRAIL
USEREADY
0
X2TIMING
0
XWRLEAD
N/A
XWRACTIVE
N/A
XWRTRAIL
N/A
READYMODE
N/A
N/A = Dont care for this example
SPRS174J
121
7.25 External Interface Write Timing

Table 7 - 29. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
MAX
UNIT
ns
ns
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active low
-2
-2
0
ns
4
th(XA)XZCSH
th(XD)XWE
Hold time, write data valid after XWE inactive high
ns
ns
TW - 2
ns
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
4
TW = Trail period, write access. See Table 7 - 25.
ns
Active
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
DOUT
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 7 - 28. Example Write Access

XRDLEAD
N/A
XRDACTIVE
XRDTRAIL
N/A
N/A
USEREADY
0
X2TIMING
0
XWRLEAD
1
XWRACTIVE
0
XWRTRAIL
0
READYMODE
N/A
122
SPRS174J
7.26 External Interface Ready-on-Read Timing With One External Wait State
Table 7 - 30. External Memory Interface Read Switching Characteristics
PARAMETER
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
th(XA)XZCSH
ns
Hold time, address valid after XRD inactive high
ns
th(XA)XRD
MIN
ns
ns
ns
Delay time, XCLKOUT high/low to XRD active low
ns
ns
-2
-2
Table 7 - 31. External Memory Interface Read Timing Requirements

MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
MAX
UNIT
14
ns
AR - 12
ns
(LR + AR) 12
ns
ns
LR = Lead period, read access. AR = Active period, read access. See Table 7 - 25.
Table 7 - 32. Synchronous XREADY Timing Requirements

MIN
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
th(XRDYsynchL)
Hold time, XREADY (Synch) low
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
MAX
UNIT
15
ns
ns
15
ns
ns
The first XREADY (Synch) sample occurs with respect to E in Figure 7 - 29:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) - tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 7 - 33. Asynchronous XREADY Timing Requirements

MIN
tsu(XRDYasynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (Asynch) low
tsu(XRDYasynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
MAX
UNIT
11
ns
ns
11
ns
ns
The first XREADY (Asynch) sample occurs with respect to E in Figure 7 - 30:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE - 3 +n) tc(XTIM) - tsu(XRDYasynchL)XCOHL
SPRS174J
123
See Notes A and B
WS (Synch)
Active
Lead
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:15]
DIN
th(XRDHsynchH)XZCSH
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
D
E
Legend:
= Dont care. Signal can be high or low during this time.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) - tsu(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
Figure 7 - 29. Example Read With Synchronous XREADY Access

XRDLEAD
1
XRDACTIVE
XRDTRAIL
USEREADY
1
X2TIMING
0
XWRLEAD
N/A
XWRACTIVE
N/A
XWRTRAIL
N/A
READYMODE
0 = XREADY
(Synch)
124
SPRS174J
WS (Asynch)
See Notes
A and B
Active
Lead
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
DIN
XD[0:15]
th(XRDYasynchL)
XREADY(Asynch)
D
E
Legend:
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE - 3 +n) tc(XTIM) - tsu(XRDYasynchL)XCOHL
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)
Figure 7 - 30. Example Read With Asynchronous XREADY Access

XRDLEAD
1
XRDACTIVE
XRDTRAIL
USEREADY
1
X2TIMING
0
XWRLEAD
N/A
XWRACTIVE
N/A
XWRTRAIL
N/A
READYMODE
1 = XREADY
(Asynch)
SPRS174J
125
7.27 External Interface Ready-on-Write Timing With One External Wait State
Table 7 - 34. External Memory Interface Write Switching Characteristics
PARAMETER
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
td(XCOHL-XWEL)
MIN
MAX
UNIT
ns
ns
ns
Delay time, XCLKOUT high/low to XWE low
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active low
th(XA)XZCSH
th(XD)XWE
Hold time, write data valid after XWE inactive high
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
-2
-2
0
ns
4
ns
ns
TW - 2
ns
ns
TW = trail period, write access (see Table 7 - 25)
Table 7 - 35. Synchronous XREADY Timing Requirements

MIN
Setup time, XREADY (Synch) low before XCLKOUT high/low
th(XRDYsynchL)
Hold time, XREADY (Synch) low
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
MAX
UNIT
15
ns
ns
15
ns
ns
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
D =(XWRLEAD + XWRACTIVE +n - 1) tc(XTIM) - tsu(XRDYsynchL)XCOHL
Table 7 - 36. Asynchronous XREADY Timing Requirements

MIN
Setup time, XREADY (Asynch) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (Asynch) low
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
MAX
UNIT
11
ns
ns
11
ns
ns
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
D = (XWRLEAD + XWRACTIVE - 3 + n) tc(XTIM) - tsu(XRDYasynchL)XCOHL
126
SPRS174J
WS (Synch)
See Notes
A and B
Trail
Active
Lead 1
See Note C
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYsynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
D
E
Legend:
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n - 1) tc(XTIM) - tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 7 - 31. Write With Synchronous XREADY Access

XRDLEAD
N/A
XRDACTIVE
XRDTRAIL
N/A
N/A
USEREADY
1
X2TIMING
0
XWRLEAD
1
XWRACTIVE
3
XWRTRAIL
1
READYMODE
0 = XREADY
(Synch)
SPRS174J
127
WS (Asynch)
See Notes
A and B
Trail
Active
Lead 1
See Note C
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
th(XRDYasynchL)
XREADY(Asynch)
D
E
Legend:
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE - 3 + n) tc(XTIM) - tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)
Figure 7 - 32. Write With Asynchronous XREADY Access

XRDLEAD
N/A
XRDACTIVE
XRDTRAIL
N/A
N/A
USEREADY
1
X2TIMING
0
XWRLEAD
1
XWRACTIVE
3
XWRTRAIL
1
READYMODE
1 = XREADY
(Asynch)
128
SPRS174J
7.28 XHOLD and XHOLDA

If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XZCS0AND1
XD[15:0]
XZCS2
XWE, XRD
XZCS6AND7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events. Detailed timing diagram will be released in a future revision of this data sheet.
7.29 XHOLD/XHOLDA Timing

Table 7 - 37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
SPRS174J
129
XCLKOUT
(/1 Mode)
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
td(HH-BV)
High-Impedance
Valid
High-Impedance
Valid
Valid
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.

B. Normal XINTF operation resumes.
Figure 7 - 33. External Interface Hold Waveform
130
SPRS174J
Table 7 - 38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

MIN
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
td(HH-HAH)
td(HH-BV)
MAX
UNIT
4tc(XTIM)+tc(XCO)
ns
4tc(XTIM+2tc(XCO)
ns
Delay time, XHOLD high to XHOLDA high
4tc(XTIM)
ns
Delay time, XHOLD high to Bus valid
6tc(XTIM)
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,
for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
td(HH-BV)
High-Impedance
Valid
Valid
XD[15:0]
See Note A
NOTES:
High-Impedance
Valid
High-Impedance
See Note B
A All pending XINTF accesses are completed.

B Normal XINTF operation resumes.
Figure 7 - 34. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
SPRS174J
131
7.30 On-Chip Analog-to-Digital Converter

7.30.1 Absolute Maximum Ratings
Supply voltage range,
VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG . . . . . . . . . . . . . . . . . . 0.3 V to 4.6 V

VSS1 to VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.5 V
Analog Input (ADCIN) Clamp Current, total (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V
DDA or below VSS. The continuous clamp
current per pin is 2 mA.
7.30.2 Electrical Characteristics Over Recommended Operating Conditions

Table 739. DC Specifications (See Note 1)
PARAMETER
MIN
Resolution
ADC clock (See Note 2)
TYP
MAX
UNIT
12
Bits
kHz
25
MHz
ACCURACY
INL (Integral nonlinearity) (see Note 6)
DNL (Differential nonlinearity) (see Note 6)
118.75 MHz ADC clock
1.5
TBD
TBD
LSB
LSB
Offset error (See Note 3)
40
80
LSB
Overall gain error with internal reference

(See Note 4)
120
200
LSB
Channel-to-channel offset variation
LSB
Channel-to-channel Gain variation
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(See Note 5)
ADCLO
Input capacitance
mV
0
10
Input leakage current
pF
INTERNAL VOLTAGE REFERENCE (See Note 4)

Accuracy, ADCVREFP
1.9
2.10
Accuracy, ADCVREFM
0.95
1.05
Input voltage difference, ADCREFP ADCREFM
0.95
1.05
Temperature coefficient
Reference noise
50
PPM/C
100
NOTES: 1.
2.
3.
4.
Tested at 12.5-MHz ADCCLK

If SYSCLKOUT 25 MHz, ADC clock SYSCLKOUT/2
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal band gap reference (5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these
voltages track together. The ADC converter uses the difference between these two as its reference.
The total gain error will be the combination of the gain error shown here and the voltage reference accuracy
(ADCREFP ADCREFM). A software-based calibration procedure is recommended for better accuracy. Contact TI for
application notes.
5. Voltages above VDDA + 0.3 V or below VSS 0.3 V applied to an analog input pin may temporarily affect the conversion of
another pin. To avoid this, the analog inputs should be kept within these limits.
6. INL/DNL degrades beyond 18.75 MHz. These specifications will be updated after additional characterization.
132
SPRS174J
April 2001 Revised December 2003
Table 7 - 40. AC Specifications

PARAMETER
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
62
dB
SNR
Signal-to-noise ratio
62
dB
THD (100 kHz)
Total harmonic distortion
- 68
dB
ENOB (SNR)
Effective number of bits
10.1
Bits
SFDR
Spurious free dynamic range
69
dB
7.30.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
IDDA (TYP)
IDDAIO (TYP)
IDD1 (TYP)
40 mA
1 A
0.5 mA
7 mA
1 A
1 A
ADC OPERATING MODE/CONDITIONS

Mode A (Operational Mode):
- BG and REF enabled
- PWD disabled
5 A
Mode B:
- ADC clock enabled
- BG and REF enabled
- PWD enabled
5 A
Mode C:
- ADC clock enabled
- BG and REF disabled
- PWD enabled
Mode D:
- ADC clock disabled
- BG and REF disabled
- PWD enabled
Test Conditions:
SYSCLKOUT = 150 MHz

ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
I
DDA - includes current into VDDA1 / VDDA2 and AVDDREFBG
SPRS174J
133
Rs
Source
Signal
ADCIN0
Ron
1 k
Switch
Cp
10 pF
ac
Ch
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 k
1.25 pF
10 pF
50
Figure 7 - 35. ADC Analog Input Impedance Model
7.30.4 ADC Power-Up Control Bit Timing

ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC
Conversion
Figure 7 - 36. ADC Power-Up Control Bit Timing

Table 7 - 41. ADC Power-Up Delays
td(BGR)
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.
td(PWD)
Delay time for power

power-down
down control to be stable. Bit 7 of the ADCTRL3 register
(PWDNADC) is to be set to 1 before any ADC conversions are initiated.
MIN
TYP
MAX
UNIT
10
ms
20
50
1
ms
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
134
SPRS174J
7.30.5 Detailed Description

7.30.5.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
7.30.5.2 Analog Inputs

The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a
time. These inputs are software-selectable.
7.30.5.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
7.30.5.4 Conversion Modes

The conversion can be performed in two different conversion modes:
Sequential sampling mode (SMODE = 0)

Simultaneous sampling mode (SMODE = 1)
7.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)

In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected
channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
SPRS174J
135
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADC Event Trigger

from EV or Other
Sources
tSH
Figure 7 - 37. Sequential Sampling Mode (Single-Channel) Timing

Table 7 - 42. Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event

trigger to sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/
Acquisition width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schx_n)
Delay time for first result

to appear in the Result
register
4tc(ADCCLK)
160 ns
td(schx_n+1)
Delay time for successive

results to appear in the
Result register
136
SPRS174J
(2 + Acqps) *
tc(ADCCLK)
REMARKS
Acqps value = 0 - 15
ADCTRL1[8:11]
80 ns
7.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)

In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0
to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The
Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide
(maximum).
NOTE:
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ...,
A7/B7, and not in other combinations (such as A1/B3, etc.).
Sample n
Analog Input on
Channel Ax
Analog Input on
Channel Bv
Sample n+1
Sample n+2
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tSH
ADC Event Trigger

from EV or Other
Sources
td(SH)
tdschA0_n+1
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 7 - 38. Simultaneous Sampling Mode Timing

Table 7 - 43. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event

trigger to sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/
Acquisition Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schA0_n)

to appear in Result
register
4tc(ADCCLK)
160 ns
td(schB0_n)

to appear in Result
register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for

successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
td(schB0_n+1)
Delay time for

successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
REMARKS
Acqps value = 0 - 15
ADCTRL1[8:11]
SPRS174J
137
7.30.8 Definitions of Specifications and Terminology

Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined
as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than 1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code
transitions.
Signal-to-Noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N+
(SINAD * 1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
138
SPRS174J
7.31 Multichannel Buffered Serial Port (McBSP) Timing

7.31.1 McBSP Transmit and Receive Timing
Table 7 - 44. McBSP Timing Requirements
MIN
NO.
McBSP module clock (CLKG,
(CLKG CLKX,
CLKX CLKR) range
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P-7
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
Setup time,
time external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time,
time external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time,
time DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time,
time DR valid after CLKR low
M19
tsu(FXH-CKXL)
time external FSX high before CLKX low

Setup time,
M20
th(CKXL-FXH)
Hold time,
time external FSX high after CLKX low
20
MHz
kHz
ns
1
M11
tsu(FRH-CKRL)
UNIT
50
(CLKG CLKX
McBSP module cycle time (CLKG,
CLKX, CLKR) range
M15
MAX
CLKR int
18
CLKR ext
CLKR int
CLKR ext
CLKR int
18
CLKR ext
CLKR int
CLKR ext
CLKX int
18
CLKX ext
CLKX int
CLKX ext
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
CLKSRG
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
.
(1 ) CLKGDV)
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed
limit (20 MHz).
SPRS174J
139
Table 7 - 45. McBSP Switching Characteristics

PARAMETER
NO.
MIN
MAX
UNIT
M1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D - 5
D+5
ns
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C - 5
C+5
ns
M4
td(CKRH-FRV)
Delay time,
time CLKR high to internal FSR valid
M5
td(CKXH-FXV)
time CLKX high to internal FSX valid

Delay time,
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance

following last data bit
CLKX int
CLKX ext
14
Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.
CLKX int
CLKX ext
28
CLKX int
CLKX ext
14
CLKX int
P+8
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
Only applies to first bit transmitted when in Data

Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Enable time, CLKX high to DX driven

M8
M9
M10
DXENA = 0
ten(CKXH-DX)
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Delay time, FSX high to DX valid
DXENA = 0
td(FXH-DXV)
ten(FXH-DX)

Delay 0 (XDATDLY=00b) mode.
DXENA = 1
Enable time, FSX high to DX driven
DXENA = 0
ns
CLKR int
ns
CLKR ext
27
ns
CLKX int
CLKX ext
27
CLKX ext
ns
ns
ns
P + 14
CLKX int
CLKX ext
CLKX int
CLKX ext
P+6
FSX int
ns
FSX ext
14
FSX int
P+8
FSX ext
P + 14
FSX int
FSX ext
FSX int
ns
ns
Only applies to first bit transmitted when in Data DXENA = 1

FSX ext
P+6
Delay 0 (XDATDLY=00b) mode
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
2P = 1/CLKG in ns.
C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
140
SPRS174J
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n - 1)
(n - 2)
(n - 3)
M17
(n - 4)
M18
DR
(RDATDLY=01b)
Bit (n - 1)
(n - 2)
M17
(n - 3)
M18
DR
(RDATDLY=10b)
Bit (n - 1)
(n - 2)
Figure 7 - 39. McBSP Receive Timing

M1, M11
M2, M12
M13
M3, M12
M14
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
DX
(XDATDLY=00b)
M7
M10
Bit 0
Bit (n - 1)
(n - 2)
Bit 0
Bit (n - 1)
(n - 2)
(n - 3)
M7
M6
DX
(XDATDLY=10b)
(n - 4)
M7
M8
DX
(XDATDLY=01b)
(n - 3)
M8
Bit 0
Bit (n - 1)
(n - 2)
Figure 7 - 40. McBSP Transmit Timing
SPRS174J
141
7.31.2 McBSP as SPI Master or Slave Timing

Table 7 - 46. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
NO
NO.
MIN
SLAVE
MAX
MIN
MAX
UNIT
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
P - 10
8P - 10
ns
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
P - 10
8P - 10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
M33
tc(CKX)
Cycle time, CLKX
16P
ns
2P
Table 7 - 47. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO
NO.
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following

last data bit from FSX high
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
DX
M29
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7 - 41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
142
SPRS174J
MASTER
NO
NO.
MIN
MAX
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P - 10
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P - 10
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
2P
SLAVE
MIN
UNIT
MAX
8P - 10
ns
8P - 10
ns
16P+10
ns
16P
ns
NO
NO.
MASTER
PARAMETER
MIN
MAX
SLAVE
MIN
UNIT
MAX
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit

from CLKX low
M38
td(FXL-DXV)
P+6
7P+6
ns
4P + 6
ns
2P = 1/CLKG
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
SPRS174J
143
MASTER
NO
NO.
MIN
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P - 10
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P - 10
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
8P - 10
ns
8P - 10
ns
8P+10
ns
16P
ns
2P
NO
NO.
MASTER
PARAMETER
MIN
MAX
SLAVE
MIN
MAX
UNIT
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44
td(FXL-CKXL)
Delay time, FSX low to CLKX low
ns
M47
tdis(FXH-DXHZ)

from FSX high
6P + 6
ns
M48
td(FXL-DXV)
4P + 6
ns
2P = 1/CLKG
M52
MSB
M51
LSB
CLKX
M43
M44
FSX
M47
DX
M48
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
144
SPRS174J
NO
NO.
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
P - 10
8P - 10
ns
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
P - 10
8P - 10
ns
16P +
10
ns
16P
ns
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
tc(CKX)
Cycle time, CLKX
2P
NO
NO.
MASTER
PARAMETER
MIN
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
M56
tdis(CKXH-DXHZ)

from CLKX high
M57
td(FXL-DXV)
SLAVE
MAX
MIN
MAX
UNIT
ns
2P
ns
P+6
7P + 6
ns
4P + 6
ns
2P = 1/CLKG
C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
SPRS174J
145
7.32 Flash Timing (F281x Only)

7.32.1 Recommended Operating Conditions
Nf
Flash endurance for the array (Write/erase cycles)
0C to 85C
NOTP
OTP endurance for the array (Write cycles)
0C to 85C
MIN
NOM
100
1000
MAX
UNIT
cycles
write
MAX
UNIT
Table 7 - 54. Flash Parameters at 150-MHz SYSCLKOUT

PARAMETER
MIN
Program Time
Erase Time
TYP
35
8K Sector
170
ms
16K Sector
320
ms
8K Sector
10
16-Bit Word
16K Sector
IDD3VFLP
VDD3VFL current consumption during the Erase/Program cycle
IDDP
VDD current consumption during Erase/Program cycle
IDDIOP
VDDIO current consumption during Erase/Program cycle
11
Erase
75
mA
Program
35
mA
140
mA
20
mA
Typical parameters as seen at room temperature using flash API V1 including function call overhead.
Table 7 - 55. Flash/OTP Access Timing

PARAMETER
MIN
TYP
MAX
UNIT
ta(fp)
Paged Flash access time
36
ns
ta(fr)
Random Flash access time
36
ns
ta(OTP)
OTP access time
60
ns
NOTE: For 150 MHz, PAGE WS = 5 and RANDOM WS = 5

For 135 MHz, PAGE WS = 4 and RANDOM WS = 4
Table 7 - 56. Minimum Required Wait-States at Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE
RANDOM WAIT STATE
150
6.67
120
8.33
100
10
75
13.33
50
20
30
33.33
25
40
15
66.67
250
Formulas to compute page wait state and random wait state:

Page Wait State +
Random Wait State +
t a(fp)
t c(SCO)
*1
t a(fr)
t c(SCO)
(round up to the next highest integer), or 0 whichever is larger
*1
(round up to the next highest integer), or 1 whichever is larger
Random wait state must be greater than or equal to 1
146
SPRS174J
Mechanical Data
Mechanical Data
8.1
Ball Grid Array (BGA)
GHH (S-PBGA-N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
10,40 TYP
SQ
0,80
0,40
A1 Corner
0,40
0,80
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4173504- 3/C 12/01
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
Figure 8 - 1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA

Table 8 - 1. Thermal Resistance Characteristics for 179-GHH
PARAMETER
179-GHH PACKAGE
UNIT
PsiJT
0.658
C / W
JA
42.57
C / W
JC
16.08
C / W
MicroStar BGA is a trademark of Texas Instruments.
SPRS174J
147
Mechanical Data
8.2
Low-Profile Quad Flatpacks (LQFPs)
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
0,50
0,13 NOM
176
45
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
0,25
0,05 MIN
26,20
SQ
25,80
0 - 7
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134 / B 11/96

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Figure 8 - 2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP

Table 8 - 2. Thermal Resistance Characteristics for 176-PGF
148
SPRS174J
PARAMETER
176-PGF PACKAGE
UNIT
PsiJT
0.247
C / W
JA
41.88
C / W
JC
9.73
C / W
Mechanical Data
PBK (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
0,40
96
0,07 M
65
64
97
128
33
0,13 NOM
32
Gage Plane
12,40 TYP
14,20
SQ
13,80
16,20
SQ
15,80
0,25
0,05 MIN
0 - 7
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040279-3 / C 11/96

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Figure 8 - 3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP
Table 8 - 3. Thermal Resistance Characteristics for 128-PBK

PARAMETER
128-PBK PACKAGE
UNIT
PsiJT
0.271
C / W
JA
41.65
C / W
JC
10.76
C / W
SPRS174J
149
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS174I device-specific data
sheet to make it an SPRS174J revision.
Scope:
PAGE(S)
NO.
Added one Flash deviceTMS320F2811.

Added three ROM devicesTMS320C2810, TMS320C2811, and TMS320C2812.
ADDITIONS/CHANGES/DELETIONS
Global:
- added TMS320F2811 information
- added TMS320C2810, TMS320C2811, and TMS320C2812 information
Added the following:
- Figure 3 - 3, F2811 Memory Map (p.28)
- Section 3.2.7, ROM (C281x Only) (p.34)
- Section 7.16, Low-Power Mode Wakeup Timing (p.101)
- Section 7.26, External Interface Ready-on-Read Timing With One External Wait State (p.123)
- Section 7.27, External Interface Ready-on-Write Timing With One External Wait State (p.126)
- Section 7.23, XINTF Signal Alignment to XCLKOUT (p. 119)
- Section 7.29, XHOLD/XHOLDA Timing (p.129)
- Section 7.31.2, McBSP as SPI Master or Slave Timings (p.142)
- Table 7 - 26, XINTF Clock Configurations
- Table 7 - 54, Flash Parameters at 150-MHz SYSCLKOUT (p.146)
- Table 7 - 56, Minimum Required Wait-States at Different Frequencies (p.146)
13
Table 3 - 1, Hardware Features:

- updated table with F2811 information
- updated table with C2810, C2811, and C2812 information
17
Table 3 - 2, Signal Descriptions:

- updated description of XCLKOUT
25
Added note on power up
26
Figure 3 - 1, Functional Block Diagram:

- added F2811 Flash size to Flash box
- added ROM box
- updated footnote about XINTF
30
Table 4 - 1:
- renamed table from Addresses of Flash Sectors in F2812 to Addresses of Flash Sectors in F2812 and F2811
34
Section 3.2.6, Flash (F281x Only):

- updated section to include F2811 information
119
Updated Figure 7 - 26, Relationship Between XTIMCLK and SYSCLKOUT
73
Section 4.6, Serial Communications Interface (SCI) Module:

- added Max bit rate equation
78
Figure 4 - 10, Serial Peripheral Interface Module Block Diagram (Slave Mode):
- added footnote about SPISTE
Section 6, Documentation Support
- added documents
83
Figure 5 - 1, TMS320x28x Device Nomenclature:

- updated drawing to include 2811 devices
SPRS174J
151
Revision History
PAGE(S)
NO.
152
ADDITIONS/CHANGES/DELETIONS
84
Section 6, Documentation Support

- added documents
85
Section 7.1, Absolute Maximum Ratings:

- updated footnote
86
Section 7.2, Recommended Operating Conditions:

- added MAX values for VIH
86
Section 7.3, Electrical Characteristics Over Recommended Operating Conditions:

- updated table
87
Section 7.4, Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power
Modes at 150-MHz SYSCLKOUT:
- added columns for MAX values
95
Table 7 - 4, Input Clock Frequency:

- added fl parameter
104
Table 7 - 14:
- renamed table from PWM Timing Requirements to Timer and Capture Unit Timing Requirements
- added tw(CAP) parameter
- added footnote about Maximum input frequency to the QEP
111
Figure 7 - 22, SPI Master Mode External Timing (Clock Phase = 0):
- updated footnote
113
Figure 7 - 23, SPI Master External Timing (Clock Phase = 1):

- updated footnote
123
Updated Table 7 - 32, Synchronous XREADY Timing Requirements (XCLKOUT = XTIMCLK)
123
Updated Table 7 - 33, Asynchronous XREADY Timing Requirements (XCLKOUT = XTIMCLK)
124
Updated Figure 7 - 29, Example Read With Synchronous XREADY Access
125
Updated Figure 7 - 30, Example Read With Asynchronous XREADY Access
126
Updated Table 7 - 35, Synchronous XREADY Timing Requirements (XCLKOUT = XTIMCLK)
126
Updated Table 7 - 36, Asynchronous XREADY Timing Requirements (XCLKOUT = XTIMCLK)
127
Updated Figure 7 - 31, Write With Synchronous XREADY Access
128
Updated Figure 7 - 32, Write With Asynchronous XREADY Access
129
Updated Table 7 - 37, XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
130
Updated Figure 7 - 33, External Interface Hold Waveform
131
Updated Table 7 - 38, XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
130
Updated Figure 7 - 33, External Interface Hold Waveform
131
Updated Figure 7 - 34 ,XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
146
Updated Table 7 - 55, Flash/OTP Access Timings
SPRS174J

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TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

Literature Number: SPRS174J

This document contains information on

Video & Imaging

April 2001 - Revised December 2003

April 2001 - Revised December 2003

XINTF Signal Alignment to XCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

April 2001 - Revised December 2003

April 2001 - Revised December 2003

7-15 TDIRx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

April 2001 - Revised December 2003

3-1 Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

April 2001 - Revised December 2003

7-17 Interrupt Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

April 2001 - Revised December 2003

April 2001 - Revised December 2003

- 150 MHz (6.67-ns Cycle Time)

D Three 32-Bit CPU-Timers

- Two Event Managers (EVA, EVB)

TMS320C28x is a trademark of Texas Instruments.

April 2001 - Revised December 2003

Instruction Cycle (at 150 MHz)

Single-Access RAM (SARAM)

3.3-V On-Chip Flash (16-bit word)

On-Chip ROM (16-bit word)

Code Security for

OTP ROM (1K X 16)

General-Purpose (GP) Timers

Capture (CAP)/QEP Channels

32-Bit CPU Timers

Digital I/O Pins (Shared)

April 2001 - Revised December 2003

Terminal Assignments for the GHH Package

AVDDAVSSADCREFM ADCINA5 ADCXHOLD

ADCINB3 ADCINB0 ADCINB1 ADCINA2

ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6

ADCLO ADCINA3 ADCINA7 XREADY

April 2001 - Revised December 2003

Pin Assignments for the PGF Package

Figure 2 - 2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)

April 2001 - Revised December 2003

Pin Assignments for the PBK Package

Figure 2 - 3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

April 2001 - Revised December 2003

XINTF SIGNALS (2812 ONLY)

16 bit XINTF Data Bus

April 2001 - Revised December 2003

Table 3 - 2. Signal Descriptions (Continued)

XINTF SIGNALS (2812 ONLY) (CONTINUED)

Microprocessor/Microcomputer Mode Select. Switches

External Hold Request. XHOLD, when active (low), requests

External Hold Acknowledge. XHOLDA is driven active (low)

XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active

XINTF Zone 2 Chip Select. XZCS2 is active (low) when an

XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active

Write Enable. Active-low write strobe. The write strobe

Read Enable. Active-low read strobe. The read strobe

April 2001 - Revised December 2003

Table 3 - 2. Signal Descriptions (Continued)