Celeron M Datasheet

Intel® Celeron® M Processor
Datasheet
June 2004
Order Number: 300302-003

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Copyright © 2004, Intel Corporation
2 Intel® Celeron® M Processor Datasheet

Contents
1 Introduction ...................................................................................................................... 7
1.1 Terminology ........................................................................................................... 8
1.2 References.............................................................................................................9
1.3 State of Data .......................................................................................................... 9
2 Low Power Features ...................................................................................................... 11
2.1 Clock Control and Low Power States................................................................... 11
2.1.1 Normal State ........................................................................................... 11
2.1.2 AutoHALT Power-Down State.................................................................11
2.1.3 Stop-Grant State ..................................................................................... 12
2.1.4 HALT/Grant Snoop State ........................................................................ 12
2.1.5 Sleep State..............................................................................................12
2.1.6 Deep Sleep State .................................................................................... 13
2.2 FSB Low Power Enhancements .......................................................................... 13
2.3 Processor Power Status Indicator (PSI#) Signal.................................................. 14
3 Electrical Specifications ................................................................................................ 15
3.1 FSB and GTLREF ................................................................................................ 15
3.2 Power and Ground Pins ....................................................................................... 15
3.3 Decoupling Guidelines ......................................................................................... 15
3.3.1 VCC Decoupling ...................................................................................... 16
3.3.2 FSB AGTL+ Decoupling .......................................................................... 16
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking..................................... 16
3.4 Voltage Identification............................................................................................ 16
3.5 Catastrophic Thermal Protection.......................................................................... 17
3.6 Signal Terminations and Unused Pins .................................................................18
3.7 FSB Signal Groups ..............................................................................................18
3.8 CMOS Signals ..................................................................................................... 19
3.9 Maximum Ratings ................................................................................................ 20
3.10 Processor DC Specifications................................................................................ 20
4 Package Mechanical Specifications and Pin Information .......................................... 29
4.1 Processor Pin-Out and Pin List ............................................................................ 37
4.2 Alphabetical Signals Reference ........................................................................... 56
5 Thermal Specifications and Design Considerations .................................................. 63
5.1 Thermal Specifications......................................................................................... 65
5.1.1 Thermal Diode......................................................................................... 65
5.1.2 Intel Thermal Monitor .............................................................................. 66
6 Debug Tools Specifications .......................................................................................... 69
6.1 Logic Analyzer Interface (LAI)............................................................................. 69
6.1.1 Mechanical Considerations ..................................................................... 69
6.1.2 Electrical Considerations......................................................................... 69
Intel® Celeron® M Processor Datasheet 3

Figures
1 Clock Control States...................................................................................................................11
2 Illustration of Active State VCC Static and Ripple Tolerances ...................................................22
3 Illustration of Deep Sleep VCC Static and Ripple Tolerances ....................................................24
4 Micro-FCPGA Package Top and Bottom Isometric Views .........................................................29
5 Micro-FCPGA Package - Top and Side Views ...........................................................................30
6 Micro-FCPGA Package - Bottom View .......................................................................................31
7 Intel Celeron M Processor Die Offset .........................................................................................31
8 Micro-FCBGA Package Top and Bottom Isometric Views .........................................................33
9 Micro-FCBGA Package Top and Side Views .............................................................................34
10 Micro-FCBGA Package Bottom View .........................................................................................35
11 The Coordinates of the Processor Pins as Viewed From the Top of the
Package......................................................................................................................................38

Tables
1 References ................................................................................................................................9
2 Voltage Identification Definition ...............................................................................................17
3 FSB Pin Groups.......................................................................................................................19
4 Processor DC Absolute Maximum Ratings..............................................................................20
5 Voltage and Current Specifications .........................................................................................21
6 Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V
(Active State) ...........................................................................................................................23
7 Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V
(Deep Sleep State) ..................................................................................................................24
8 Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V
(Active State) ...........................................................................................................................25
9 Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V
(Deep Sleep State) ..................................................................................................................26
10 FSB Differential BCLK Specifications ......................................................................................26
11 AGTL+ Signal Group DC Specifications ..................................................................................27
12 CMOS Signal Group DC Specifications...................................................................................27
13 Open Drain Signal Group DC Specifications ...........................................................................28
14 Micro-FCPGA Package Dimensions........................................................................................32
15 Micro-FCBGA Package Dimensions........................................................................................36
23 Pin Listing by Pin Name...........................................................................................................39
24 Pin Listing by Pin Number .......................................................................................................46
25 Signal Description....................................................................................................................56
26 Power Specifications for the Intel Celeron M Processor .........................................................64
27 Thermal Diode Interface ..........................................................................................................65
28 Thermal Diode Specifications ..................................................................................................65

Revision History
Order
Revision Description Date
Number
-001 300302 Initial release January 2004

• Added ULV 900 MHz and 1.40 GHz specs
-002 300302 April 2004
• Updated DINV[3:0]# and BPM3# pin direction
-003 300302 • Added 1.50 GHz specifications June 2004

Introduction
1 Introduction
The Intel® Celeron® M processor and the ultra low voltage (ULV) Intel® Celeron® M processor
are high-performance, low-power mobile processors with several microarchitectural enhancements
over existing mobile Intel Celeron processors.
The Intel Celeron M processor is available at the following core frequencies in the Micro-FCBGA
and Micro-FCPGA packaging technologies:
• 1.20 GHz (1.356 V)
• 1.30 GHz (1.356 V)
• 1.40 GHz (1.356 V)
• 1.50 GHz (1.356 V)
The ultra low voltage Intel Celeron M processor is available at the following frequency in the
Micro-FCBGA packaging technology:
• 800 MHz (1.004 V)
• 900 MHz (1.004 V)
The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF)
socket, which is referred to as the mPGA479M socket.
The following list provides some of the key features of this processor:
• Supports Intel architecture with dynamic execution
• Manufactured on Intel’s advanced 0.13 micron process technology with copper interconnect.
• High-performance, low-power core featuring architectural innovations like micro-ops fusion
and advanced stack management that reduce the number of micro-ops handled by the
processor.
• On-die, primary 32-kB instruction cache and 32-kB, write-back, data cache
• On-die, 512-kB second level cache with Advanced Transfer Cache architecture
• Advanced branch prediction and data prefetch logic
• Streaming SIMD extensions 2 (SSE2) that enables breakthrough levels of performance in
multimedia applications including 3D graphics, video decoding/encoding, and speech
recognition.
• 400-MHz, source-synchronous front side bus (FSB)
• Advanced power management features
• Maintained support for MMXTM technology
• Compatible with IA-32 software.
The processor also features a very advanced branch prediction architecture that significantly
reduces the number of mispredicted branches. The processor’s Data Prefetch Logic speculatively
fetches data to the L2 cache before an L1 cache request occurs, resulting in reduced bus cycle
penalties and improved performance.

Introduction
The new packed, double-precision, floating-point instructions enhance performance for

applications that require greater range and precision, including scientific and engineering
applications and advanced 3D geometry techniques, such as ray tracing.
The processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The 400-MHz
FSB uses source-synchronous transfer (SST) of address and data to improve performance by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
“double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning
Transceiver Logic (AGTL+) signal technology, a variant of GTL+ signalling technology with low
power enhancements.
Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel
products.
1.1 Terminology
Term Definition
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
#
the name does not imply an active state but describes part of a binary sequence (such as address
or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex “A”, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Front Side Bus refers to the interface between the processor and system core logic (also known as
FSB
the chipset components).

Introduction
1.2 References
The following documents may be beneficial when reading this document. Please note that
“platform design guides,” when used throughout this document, refer to the following documents:
• Intel852GM Chipset Platform Design Guide
• Intel 855GM/855GME Chipset Platform Design Guide
• Intel 855PM Chipset Platform Design Guide
Table 1. References
Document Order Number1
Intel 855PM Chipset Platform Design Guide http://developer.intel.com
Intel 855PM Chipset Design Guide Update http://developer.intel.com
Intel 855PM Chipset Datasheet http://developer.intel.com
IIntel 855GM/855GME Chipset Platform Design Guide http://developer.intel.com
Intel 855GM/855GME Chipset Datasheet http://developer.intel.com
Intel 855GM Specification Update http://developer.intel.com
Intel 852GM Chipset Datasheet http://developer.intel.com
Intel Architecture Software Developer's Manual http://developer.intel.com
Volume 1: Basic Architecture 253665

Volume 2A: Instruction Set Reference 253666
Volume 2B: Instruction Set Reference 253667
Volume 3: System Programming Guide 253668
ITP700 Debug Port Design Guide http://developer.intel.com
NOTE: Contact your Intel representative for the latest revision and order number of this document.
1.3 State of Data

The data contained within this document represents the most accurate information available by the
publication date. However, all data in this document is preliminary and subject to change.

Introduction

Low Power Features
2 Low Power Features
2.1 Clock Control and Low Power States

The Intel Celeron M processor supports the AutoHALT, Stop Grant, Sleep, and Deep Sleep states
for optimal power management. See Figure 1 for a visual representation of the processor low-
power states.
Figure 1. Clock Control States
STPCLK# asserted SLP# asserted
Stop
Normal STPCLK# de-asserted Sleep
Grant
SLP# de-asserted
STPCLK#
halt asserted snoop DPSLP# DPSLP#
break HLT snoop
serviced de-asserted asserted
instruction STPCLK# occurs
de-asserted
snoop
occurs HALT/
Deep
Auto Halt Grant
Sleep
snoop Snoop
serviced
V0001-04
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
2.1.1 Normal State

This is the normal operating state for the processor.
2.1.2 AutoHALT Power-Down State

AutoHALT is a low-power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, INIT#, LINT[1:0]
(NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately
initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal mode or
the AutoHALT Power-Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.

Low Power Features
The system can generate a STPCLK# while the processor is in the AutoHALT Power-Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Power-Down state, the processor will process bus snoops.
2.1.3 Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor issued Stop-Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven
(allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the FSB should be driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be
deasserted ten or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
FSB (see Section 2.1.4). A transition to the Sleep state (see Section 2.1.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state. Please refer to the FERR# pin description in
Section 4.2 for details on FERR# break event behavior in the Stop Grant state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
2.1.4 HALT/Grant Snoop State

The processor will respond to snoop or interrupt transactions on the FSB while in Stop-Grant state
or in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters
the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has
been serviced (whether by the processor or another agent on the FSB) or the interrupt has been
latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-
Grant state or AutoHALT Power-Down state, as appropriate.
2.1.5 Sleep State

The Sleep state is a low-power state in which the processor maintains its context, maintains the
phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered
from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon

Low Power Features
the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the
Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of
specification and may result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or
RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state by asserting the DPSLP# pin. (see Section 2.1.6.). While the processor is in the Sleep
state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.6 Deep Sleep State

Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings
on Intel 855PM/ICH4-M, Intel 855GM/ICH4-M, and Intel 852GM/ICH4-M chipset-based
platforms with the CK-408 clock chip are as follows:
• Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. CK-408 will stop/
tristate BCLK within 2 BCLKs +/- a few nanoseconds.
• Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. CK-408 will drive
BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods
later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after
DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in
Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.
2.2 FSB Low Power Enhancements

The Intel Celeron M processor incorporates the following FSB low power enhancements:
• Dynamic FSB power-down

Low Power Features
• BPRI# control for address and control input buffers

• Dynamic on-die termination disabling
• Low VCCP (I/O termination voltage)
The Intel Celeron M processor incorporates the DPWR# signal that controls the data bus input
buffers on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control input buffers to
be turned off when the BPRI# signal is inactive. The On-Die termination on the processor FSB
buffers is disabled when the signals are driven low, resulting in additional power savings. The low
I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling
low I/O switching power at all times.
2.3 Processor Power Status Indicator (PSI#) Signal

The Intel Celeron M processor incorporates the PSI# signal that is asserted when the processor is in
a low power (Deep Sleep ) state. This signal is asserted upon Deep Sleep entry and deasserted upon
exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in
platform power savings and extended battery life.

Electrical Specifications
3 Electrical Specifications
3.1 FSB and GTLREF

The Intel Celeron M processor FSB uses Advanced Gunning Transceiver Logic (AGTL+)
signalling technology, a variant of GTL+ signalling technology with low power enhancements.
This signalling technology provides improved noise margins and reduced ringing through low-
voltage swings and controlled edge rates. The termination voltage level for the Intel Celeron M
processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to data and
address bus, signal integrity and platform design methods have become more critical than with
previous processor families. Design guidelines for the Intel Celeron M processor FSB will be
detailed in the platform design guides.
The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.
Termination resistors are provided on the processor silicon and are terminated to its I/O voltage
(VCCP). Intel’s 855PM, 855GM, and 852GM chipsets will also provide on-die termination, thus
eliminating the need to terminate the bus on the system board for most AGTL+ signals.
Refer to the platform design guides for board level termination resistor requirements.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.
3.2 Power and Ground Pins

For clean on-chip power distribution, the Intel Celeron M processor will have a large number of
VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while
all VSS pins must be connected to system ground planes. Use of multiple power and ground planes
is recommended to reduce I x R drop. Please refer to the platform design guides for more details.
The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low- and full-power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in Table 5. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and design guidelines, refer to the
platform design guides.

3.3.1 VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low-power states, must be
provided by the voltage regulator solution. For more details on decoupling recommendations,
please refer to the platform design guides. Intel strongly recommends that the layout and
decoupling recommendations in the platform design guides be followed.
3.3.2 FSB AGTL+ Decoupling

Intel Celeron M processors integrate signal termination on the die as well as incorporate high-
frequency decoupling capacitance on the processor package. Decoupling must also be provided by
the system motherboard for proper AGTL+ bus operation. For more information, refer to the
platform design guides.
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the Intel Celeron M processor core frequency is a multiple of
the BCLK[1:0] frequency. In regards to processor clocking, the Intel Celeron M processor uses a
differential clocking implementation.
3.4 Voltage Identification

The processor uses six voltage identification pins, VID[5:0], to support automatic selection of
power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor
VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[5:0]. A 1 in this
refers to a high-voltage level and a 0 refers to low-voltage level.

Table 2. Voltage Identification Definition

VID VCC VID VCC
5 4 3 2 1 0 V 5 4 3 2 1 0 V
0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196
0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180
0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164
0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148
0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132
0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116
0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100
0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084
0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068
0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052
0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036
0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020
0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004
0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988
0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972
0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956
0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940
0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924
0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908
0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892
0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876
0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860
0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844
0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828
0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812
0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796
0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780
0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764
0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748
0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732
0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716
0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700
3.5 Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external
thermal sensor should also be used to protect the processor and the system against excessive
temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks
and activity, leakage current can be high enough such that the processor cannot be protected in all
conditions without the removal of power to the processor. If the external thermal sensor detects a
catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP# signal is
asserted, the VCC supply to the processor must be turned off within
500 ms to prevent permanent silicon damage due to thermal runaway of the processor.

3.6 Signal Terminations and Unused Pins

All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Intel Celeron M processors. See Section 4.1 for a pin listing of the processor and the
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (VSS). Unused outputs can be left unconnected.
For details on signal terminations, please refer to the platform design guides. TAP signal
termination requirements are also discussed in ITP700 Debug Port Design Guide.
The TEST1, TEST2, and TEST3 pins must be left unconnected but should have a stuffing option
connection to VSS separately via 1-kΩ, pull-down resistors.
3.7 FSB Signal Groups

In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the crossing of
the rising edge of BCLK0 and the falling edge of BCLK1. The second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 3 identifies which signals are common
clock, source synchronous, and asynchronous.

Table 3. FSB Pin Groups

Signal Group Type Signals1
Synchronous BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,

AGTL+ Common Clock Input
to BCLK[1:0] TRDY#
Synchronous ADS#, BNR#, BPM[3:0]#2, BR0#, DBSY#, DRDY#, HIT#,
AGTL+ Common Clock I/O
to BCLK[1:0] HITM#, LOCK#, PRDY#2
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#

Synchronous A[31:17]# ADSTB[1]#
AGTL+ Source Synchronous I/O to assoc.
strobe D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
Synchronous
AGTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
to BCLK[1:0]
A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
CMOS Input Asynchronous
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP#
CMOS Output Asynchronous PSI#, VID[5:0]
Synchronous
CMOS Input TCK, TDI, TMS, TRST#
to TCK
Synchronous
Open Drain Output TDO
to TCK
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]3
COMP[3:0], DBR#3, GTLREF, RSVD, TEST3, TEST2,
Power/Other TEST1, THERMDA, THERMDC, VCC, VCCA[3:0], VCCP,
VCCQ[1:0], VCC_SENSE, VSS, VSS_SENSE
NOTES:
1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. BPM[2:0]# and PRDY# are AGTL+ output only signals.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
3.8 CMOS Signals

CMOS input signals are shown in Table 3. Legacy output FERR#, IERR# and other non-AGTL+
signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not
have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals
are required to be asserted for at least three BCLKs in order for the chipset to recognize them. See
Section 3.10 for the DC specifications for the CMOS signal groups.

3.9 Maximum Ratings

Table 4 lists the processor’s maximum environmental stress ratings. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from electro
static discharge (ESD), system designers should always take precautions to avoid high-static
voltages or electric fields.
Table 4. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes
TSTORAGE Processor storage temperature –40 85 °C 2

Any processor supply voltage with
VCC -0.3 1.75 V 1
respect to VSS
AGTL+ buffer DC input voltage with
VinAGTL+ -0.1 1.75 V 1, 2
respect to VSS
CMOS buffer DC input voltage with
VinAsynch_CMOS -0.1 1.75 V 1, 2
respect to VSS
NOTES:
1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.
3.10 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See Table 11 for the pin signal definitions and signal pin assignments. Most of
the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are
listed in Table 11. DC specifications for the CMOS group are listed in Table 12.
Table 5 through Table 13 list the DC specifications for the Intel Celeron M processor and are valid
only while meeting specifications for junction temperature, clock frequency, and input voltages.
Active Mode load line specifications apply in all states except in the Deep Sleep state. VCC,BOOT is
the default voltage driven by the voltage regulator at power up in order to set the VID values.
Unless specified otherwise, all specifications for the Intel Celeron M processor are at Tjunction =
100 °C. Care should be taken to read all notes associated with each parameter.

Table 5. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes
Intel Celeron M processor

1.20 GHz Core VCC 1.356
VCC V 1, 2
Ultra low voltage Intel Celeron
M Processor
800 MHz Core Vcc 1.004
900 MHz Core Vcc 1.004
Default VCC Voltage for initial

VCC,BOOT 1.14 1.20 1.26 V 2, 7
power up
VCCP AGTL+ Termination Voltage 0.997 1.05 1.102 V 2
VCCA PLL supply voltage 1.71 1.8 1.89 V 2
ICC for Intel Celeron

ICCDES MProcessors 25
Recommended Design Target A 5
ICC for Mobile Intel Celeron M

processor by Frequency/
Voltage:
1.20 GHz & 1.356 V 21
1.30 GHz & 1.356 V 21
1.40 GHz & 1.356 V 21
1.50 GHz & 1.356 V 21
ICC
A 3
ICC for ultra low voltage Intel
Celeron M processor by
Frequency/Voltage:
800 MHz & 1.004V 7.4
900 MHz & 1.004V 8.0
ICC Auto-Halt & Stop-Grant at:
1.356 V (1.20 Ghz) 13.5
1.356 V (1.30 GHz) 12.9
IAH,
1.356 V (1.40 GHz) 12.3 A 4
ISGNT 1.356 V (1.50 GHz) 11.8
1.004 V (800 MHz ULV) 3.4
1.004 V (900 MHz ULV) 3.3
ICC Sleep at:

1.356 V (1.20 Ghz) 13.3
1.356 V (1.30 GHz) 12.7
ISLP 1.356 V (1.40 GHz) 12.1 A 4
1.356 V (1.50 GHz) 11.6
1.004 V (800 MHz ULV) 3.4
1.004 V (900 MHz ULV) 3.2

Table 5. Voltage and Current Specifications

ICC Deep Sleep at:

1.356 V (1.20 GHz) 12.9
1.356 V (1.30 GHz) 12.3
1.356 V (1.40 GHz) 11.7
IDSLP 1.356 V (1.50 GHz) 11.1 A 4
1.004 V (800 MHz ULV) 3.2

1.004 V (900 MHz ULV) 3
VCC power supply current slew

dICC/DT 0.5 A/ns 6, 8
rate
ICCA ICC for VCCA supply 120 mA
ICCP ICC for VCCP supply 2.5 A
NOTES:
1. The typical values shown are the VID encoded voltages. Static and Ripple tolerances (for minimum and
maximum voltages) are defined in the load line tables Table 6, Table 7, Table 8, and Table 9 .
2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-Mohm minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
3. Specified at VCC,STATIC (nominal) under maximum signal loading conditions.
4. Specified at the VID voltage.
5. The ICCDES(max) specification comprehends future processor frequencies. Platforms should be designed to
this specification.
6. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7. Measured at the bulk capacitors on the motherboard.
Figure 2. Illustration of Active State VCC Static and Ripple Tolerances
VID = 1.356V (Active State)
1.400
1.380
1.360 1.356
1.340
Vcc, V
1.320
1.300
1.280
1.260
1.240
0 5 10 15 20
STATIC Static Min Static
Icc, A Max Ripple Min Ripple Max

Table 6. Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V (Active State)
VID = 1.356 V,
Offset = 0%
Mode
STATIC Ripple
VCC, A VCC, V
Min Max Min Max
0 1.356 1.336 1.376 1.326 1.386

0.8 1.354 1.333 1.374 1.323 1.384
1.6 1.351 1.331 1.372 1.321 1.382
2.3 1.349 1.329 1.369 1.319 1.379
3.1 1.347 1.326 1.367 1.316 1.377
3.9 1.344 1.324 1.365 1.314 1.375
4.7 1.342 1.322 1.362 1.312 1.372
5.4 1.340 1.319 1.360 1.309 1.370
6.2 1.337 1.317 1.358 1.307 1.368
7.0 1.335 1.315 1.355 1.305 1.365
7.8 1.333 1.312 1.353 1.302 1.363
8.6 1.330 1.310 1.351 1.300 1.361
9.3 1.328 1.308 1.348 1.298 1.358
ACTIVE
10.1 1.326 1.305 1.346 1.295 1.356

10.9 1.323 1.303 1.344 1.293 1.354
11.7 1.321 1.301 1.341 1.291 1.351
12.4 1.319 1.298 1.339 1.288 1.349
13.2 1.316 1.296 1.337 1.286 1.347
14.0 1.314 1.294 1.334 1.284 1.344
14.8 1.312 1.291 1.332 1.281 1.342
15.6 1.309 1.289 1.330 1.279 1.340
16.3 1.307 1.287 1.327 1.277 1.337
17.1 1.305 1.284 1.325 1.274 1.335
17.9 1.302 1.282 1.323 1.272 1.333
18.7 1.300 1.280 1.320 1.270 1.330
19.4 1.298 1.277 1.318 1.267 1.328
20.2 1.295 1.275 1.316 1.265 1.326
21.0 1.293 1.273 1.313 1.263 1.323

Table 7. Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V (Deep Sleep
State)
VID =1.356 V,
Offset = 1.2%
Mode
STATIC Ripple
ICC, A VCC, V
Min Max Min Max
0.0 1.340 1.319 1.360 1.309 1.370

0.8 1.337 1.317 1.358 1.307 1.368
1.6 1.335 1.314 1.355 1.304 1.365
2.5 1.332 1.312 1.353 1.302 1.363
3.3 1.330 1.310 1.350 1.300 1.360
4.1 1.327 1.307 1.348 1.297 1.358
4.9 1.325 1.305 1.345 1.295 1.355
Deep Sleep
5.7 1.323 1.302 1.343 1.292 1.353

6.6 1.320 1.300 1.340 1.290 1.350
7.4 1.318 1.297 1.338 1.287 1.348
8.2 1.315 1.295 1.335 1.285 1.345
9.0 1.313 1.292 1.333 1.282 1.343
9.8 1.310 1.290 1.331 1.280 1.341
10.7 1.308 1.287 1.328 1.277 1.338
11.5 1.305 1.285 1.326 1.275 1.336
12.3 1.303 1.282 1.323 1.272 1.333
Figure 3. Illustration of Deep Sleep VCC Static and Ripple Tolerances
VID = 1.356V (Deep Sleep)
1.380
1.360
1.340 1.340
Vcc, V
1.320
1.300
1.280
1.260
0.0 2.0 4.0 6.0 8.0 10.0 12.0
Icc, A
STATIC Static Min Static Max Ripple Min Ripple Max

Table 8. Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V (Active
State)
VID = 1.004 V,
Offset = 0%
Mode
STATIC Ripple
VCC, A VCC, V
Min Max Min Max
0 1.004 0.989 1.019 0.979 1.029

0.3 1.003 0.988 1.018 0.978 1.028
0.5 1.002 0.987 1.017 0.977 1.027
0.8 1.002 0.986 1.017 0.976 1.027
1.1 1.001 0.986 1.016 0.976 1.026
1.4 1.000 0.985 1.015 0.975 1.025
1.6 0.999 0.984 1.014 0.974 1.024
1.9 0.998 0.983 1.013 0.973 1.023
2.2 0.997 0.982 1.012 0.972 1.022
2.5 0.997 0.982 1.012 0.972 1.022
2.7 0.996 0.981 1.011 0.971 1.021
3.0 0.995 0.980 1.010 0.970 1.020
3.3 0.994 0.979 1.009 0.969 1.019
ACTIVE
3.6 0.993 0.978 1.008 0.968 1.018

3.8 0.992 0.977 1.008 0.967 1.018
4.1 0.992 0.977 1.007 0.967 1.017
4.4 0.991 0.976 1.006 0.966 1.016
4.7 0.990 0.975 1.005 0.965 1.015
4.9 0.989 0.974 1.004 0.964 1.014
5.2 0.988 0.973 1.003 0.963 1.013
5.5 0.988 0.972 1.003 0.962 1.013
5.8 0.987 0.972 1.002 0.962 1.012
6.0 0.986 0.971 1.001 0.961 1.011
6.3 0.985 0.970 1.000 0.960 1.010
6.6 0.984 0.969 0.999 0.959 1.009
6.9 0.983 0.968 0.999 0.958 1.009
7.1 0.983 0.968 0.998 0.958 1.008
7.4 0.982 0.967 0.997 0.957 1.007

Table 9. Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V (Deep
Sleep State)
VID =1.004 V,
Offset = 1.2%
Mode
STATIC Ripple
ICC, A VCC, V
Min Max Min Max
0.0 0.992 0.977 1.007 0.967 1.017

0.2 0.991 0.976 1.006 0.966 1.016
0.4 0.991 0.976 1.006 0.966 1.016
0.6 0.990 0.975 1.005 0.965 1.015
0.9 0.989 0.974 1.004 0.964 1.014
1.1 0.989 0.974 1.004 0.964 1.014
1.3 0.988 0.973 1.003 0.963 1.013
Deep Sleep
1.5 0.987 0.972 1.003 0.962 1.013

1.7 0.987 0.972 1.002 0.962 1.012
1.9 0.986 0.971 1.001 0.961 1.011
2.1 0.986 0.970 1.001 0.960 1.011
2.3 0.985 0.970 1.000 0.960 1.010
2.6 0.984 0.969 0.999 0.959 1.009
2.8 0.984 0.969 0.999 0.959 1.009
3.0 0.983 0.968 0.998 0.958 1.008
3.2 0.982 0.967 0.997 0.957 1.007
Table 10. FSB Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Notes1
VL Input Low Voltage 0 V

VH Input High Voltage 0.660 0.710 0.850 V
VCROSS Crossing Voltage 0.25 0.35 0.55 V 2
Range of Crossing Points N/A N/A 0.140 V 6

∆VCROSS
VTH Threshold Region VCROSS -0.100 VCROSS+0.100 V 3
ILI Input Leakage Current ± 100 µA 4
Cpad Pad Capacitance 1.8 2.3 2.75 pF 5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
4. For Vin between 0 V and VH.
5. Cpad includes die capacitance only. No package parasitics are included.
6. ∆VCROSS is defined as the total variation of all crossing voltages as defined in note 2.

Table 11. AGTL+ Signal Group DC Specifications

VCCP I/O Voltage 0.997 1.05 1.102 V

2/3 VCCP - 2/3 VCCP +
GTLREF Reference Voltage 2/3 VCCP V 6
2% 2%
VIH Input High Voltage GTLREF+0.1 VCCP+0.1 V 3,4,6
VIL Input Low Voltage -0.1 GTLREF-0.1 V 2
VOH Output High Voltage VCCP 4,6
RTT Termination Resistance 47 55 63 W 7
RON Buffer On Resistance 17.7 24.7 32.9 W 5
ILI Input Leakage Current ± 100 µA 8
NOTES:
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications in Chapter 4.
5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured
at 0.31 x VCCP. RON (min) = 0.38 x RTT, RON (typ) = 0.45 x RTT, RON (max) = 0.52 x RTT.
6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP.
7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31 x
VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
8. Specified with on die RTT and RON are turned off.
Table 12. CMOS Signal Group DC Specifications

VCCP I/O Voltage 0.997 1.05 1.102 V

Input Low Voltage
VIL -0.1 0.3 x VCCP V 2, 3
CMOS
VIH Input High Voltage 0.7 x VCCP VCCP+0.1 V 2
VOL Output Low Voltage -0.1 0 0.1 x VCCP V 2
VOH Output High Voltage 0.9 x VCCP VCCP VCCP+0.1 V 2
IOL Output Low Current 1.49 4.08 mA 4
IOH Output High Current 1.49 4.08 mA 5
ILI Leakage Current ± 100 µA 6
NOTES:
2. The VCCP referred to in these specifications refers to instantaneous VCCP.
3. Refer to the processor I/O Buffer Models for I/V characteristics.
4. Measured at 0.1 x VCCP.

5. Measured at 0.9 x VCCP.

6. For Vin between 0V and VCCP. Measured when the driver is tristated.
Table 13. Open Drain Signal Group DC Specifications

VOH Output High Voltage VCCP V 3

VOL Output Low Voltage 0 0.20 V
IOL Output Low Current 16 50 mA 2
ILO Leakage Current ± 200 µA 4
NOTES:
2. Measured at 0.2 V.
3. VOH is determined by value of the external pull-up resistor to VCCP. Please refer to platform RDDP for
details.
4. For Vin between 0 V and VOH.

Package Mechanical Specifications and Pin Information
4 Package Mechanical
Specifications and Pin Information
The processor is available in 478-pin Micro-FCPGA and 479 ball Micro-FCBGA packages.
Different views of the Micro-FCPGA package are shown in Figure 4 through Figure 6. Package
dimensions are shown in Table 14. Different views of the Micro-FCBGA package are shown in
Figure 8 through Figure 10. Package dimensions are shown in Table 15. The Intel Celeron M
processor die offset is illustrated in Figure 7.
The Micro-FCBGA may have capacitors placed in the area surrounding the die. Because the die-
side capacitors are electrically conductive, and only slightly shorter than the die height, care should
be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may
short the capacitors, and possibly damage the device or render it inactive. The use of an insulating
material between the capacitors and any thermal solution should be considered to prevent capacitor
shorting.
Figure 4. Micro-FCPGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE
LABEL
TOP VIEW BOTTOM VIEW

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 14 for details.

Figure 5. Micro-FCPGA Package - Top and Side Views

SUBSTRATE KEEPO UT ZO NE 0.286
7 (K 1)
8 places DO NOT CONTACT PACKAGE
IN S ID E T H IS L IN E
5 (K)
A
4 places
1.25 M A X
(A 3)
D1 35 (D )
Ø 0.32 (B )
478 places
E1 A2
2.03 ± 0.08
35 (E) P IN A 1 C OR N ER (A 1)

Figure 6. Micro-FCPGA Package - Bottom View

14 (K3)
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P 14 (K3 )
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25
25X 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26
(e)
2 5X 1.27
(e)
Figure 7. Intel Celeron M Processor Die Offset
(G )
D1
(F )
E1

Table 14. Micro-FCPGA Package Dimensions

Symbol Parameter Min Max Unit
A Overall height, top of die to package seating plane 1.88 2.02 mm
Overall height, top of die to PCB surface, including

- socket (Refer to Note 1) 4.74 5.16 mm
A1 Pin length 1.95 2.11 mm
A2 Die height 0.82 mm
A3 Pin-side capacitor height - 1.25 mm
B Pin diameter 0.28 0.36 mm
D Package substrate length 34.9 35.1 mm
E Package substrate width 34.9 35.1 mm
D1 Die length 10.56 mm
E1 Die width 7.84 mm
F To Package Substrate Center 17.5 mm
G Die Offset from Package Center 1.133 mm
e Pin pitch 1.27 mm
K Package edge keep-out 5 mm
K1 Package corner keep-out 7 mm
K3 Pin-side capacitor boundary 14 mm
- Pin tip radial true position <=0.254 mm
N Pin count 478 each
Pdie Allowable pressure on the die for thermal solution - 689 kPa
W Package weight 4.5 g
Package Surface Flatness 0.286 mm

NOTE: Overall height with socket is based on design dimensions of the Micro-FCPGA package with no thermal
solution attached. Values are based on design specifications and tolerances. This dimension is subject
to change based on socket design, OEM motherboard design or OEM SMT process.

Figure 8. Micro-FCBGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
LABEL DIE
TOP VIEW BOTTOM VIEW

Figure 9. Micro-FCBGA Package Top and Side Views

7 (K1) SUBSTRATE KEEPOUT ZONE
8 places DO NOT CONTACT PACKAGE 0.20
INSIDE THIS LINE
5 (K)
A
4 places
A2
D1 35 (D)
Ø 0.78 (b)
479 places
E1 K2
35 (E) PIN A1 CORNER

Figure 10. Micro-FCBGA Package Bottom View

1.625 (S)
4 places
AF
AE
AD
AC
AB 1.625 (S)
AA 4 places
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25
25X 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26
(e)
25X 1.27
(e)
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 15 for details

Table 15. Micro-FCBGA Package Dimensions

Symbol Parameter Min Max Unit
A Overall height, as delivered (Refer to Note 1) 2.60 2.85 mm
A2 Die height 0.82 mm
b Ball diameter 0.78 mm
D Package substrate length 34.9 35.1 mm
E Package substrate width 34.9 35.1 mm
D1 Die length 10.56 mm
E1 Die width 7.84 mm
F To Package Substrate Center 17.5 mm
G Die Offset from Package Center 1.133 mm
e Ball pitch 1.27 mm
K Package edge keep-out 5 mm
K1 Package corner keep-out 7 mm
K2 Die-side capacitor height - 0.7 mm
S Package edge to first ball center 1.625 mm
N Ball count 479 each
- Solder ball coplanarity 0.2 mm
Pdie Allowable pressure on the die for thermal solution - 689 kPa
W Package weight 4.5 g

NOTE: Overall height as delivered. Values are based on design specifications and tolerances. This dimension
is subject to change based on OEM motherboard design or OEM SMT process.

4.1 Processor Pin-Out and Pin List

Figure 11 on the next page shows the top view pinout of the Intel Celeron M processor. The pin list
is arranged in two different formats, shown in Table 23 and Table 24.

Figure 11. The Coordinates of the Processor Pins as Viewed From the Top of the Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A A
ITP_CLK ITP_CLK THER
VSS IGNNE# IERR# VSS SLP# DBR# VSS BPM[2]# PRDY# VSS TDO TCK VSS VSS D[0]# VSS D[6]# D[2]# VSS D[4]# D[1]# VSS
[1] [0] MDC
B B
BPM PROC THER
VCCA[1] RSVD VSS SMI# INIT# VSS DPSLP# VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 VSS VSS D[7]# D[3]# VSS D[13]# D[9]# VSS D[5]#
[1]# HOT# MDA
C C
STP BPM BPM THERM DSTBP DSTBN
VSS A20M# RSVD VSS TEST1 VSS VSS TMS TDI VSS RSVD VSS TEST3 VSS DPWR# D[8]# VSS VSS D[15]# D[12]#
CLK# [0]# [3]# TRIP# [0]# [0]#
D D
DINV
LINT0 VSS FERR# LINT1 VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[10]# VSS
[0]#
E E
PWR
PSI# VID[0] VSS VCC VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[14]# D[11]# VSS RSVD
GOOD
F F
VSS VID[1] VID[2] VSS VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC TEST2 VSS D[21]# VCCA[0]
G G
RSVD VSS VID[3] VID[4] VCC VSS VCC VSS VSS D[22]# D[17]# VSS
H H
RS[0]# DRDY# VSS VID[5] VSS VCC VSS VCC D[16]# D[20]# VSS D[29]#
J J
DINV
VSS LOCK# BPRI# VSS VCC VSS VCC VSS D[23]# VSS D[25]#
[1]#
K K
RS[1]# VSS HIT# HITM# VSS VCCP VSS VCC VSS DSTBN D[31]# VSS
[1]#
L L
BNR# RS[2]# VSS DEFER# VCCP VSS VCCP VSS D[18]# DSTBP VSS D[26]#
[1]#
M M
VSS DBSY# TRDY# VSS VSS VCCP VSS VCCP D[24]# VSS D[28]# D[19]#
N N
P
VCCA[2] ADS# VSS BR0# VCCP VSS
TOP VIEW VCCP VSS VSS D[27]# D[30]# VSS
P
REQ REQ COMP COMP
VSS A[3]# VSS VCCP VSS VCCP VCCQ[0] VSS
[3]# [1]# [0] [1]
R R
REQ VSS VCCP
VSS A[6]# VSS VCCP VSS D[39]# D[37]# VSS D[38]#
[0]#
T T
REQ REQ DINV D[34]#
VSS A[9]# VSS VCCP VSS VCCP VSS VSS
[4]# [2]# [2]#
U U
ADSTB
A[13]# VSS A[4]# VCC VSS VCCP VSS D[35]# VSS D[43]# D[41]#
[0]#
V V
VSS A[7]# A[5]# VSS VSS VCC VSS VCC D[36]# D[42]# VSS D[44]#
W W
VCC DSTBP DSTBN
A[8]# A[10]# VSS VCCQ[1] VCC VSS VSS VSS VSS
[2]# [2]#
Y Y
A[12]# VSS A[15]# A[11]# VSS VCC VSS VCC D[45]# VSS D[47]# D[32]#
AA AA
VSS A[16]# A[14]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[40]# D[33]# VSS D[46]#
AB AB
COMP COMP
VSS A[24]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[50]# D[48]# VSS
[3] [2]
AC AC
RSVD VSS A[20]# A[18]# VSS A[25]# A[19]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[51]# VSS D[52]# D[49]# VSS D[53]# VCCA[3]
AD AD
DINV
VSS A[23]# A[21]# VSS A[26]# A[28]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[60]# VSS D[54]# D[57]# VSS GTLREF
[3]#
AE AE
DSTBN DSTBP
A[30]# A[27]# VSS A[22]# ADSTB VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[59]# D[55]# VSS VSS
[1]# SENSE [3]# [3]#
AF AF
A[31]# VSS A[29]# A[17]# VSS VSS RSVD VCC VSS VCC VSS VCC vss VCC VSS VCC VSS VCC VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]#
SENSE
A[31]#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VSS VCC Other Pin B2 is depopulated on the Micro-FCPGA package

Table 23. Pin Listing by Pin Name
Table 23. Pin Listing by Pin Name Pin Signal Buffer

Pin Name Direction
Number Type
Pin Signal Buffer
Pin Name Direction ADSTB[0]# U3 Source Synch Input/Output
Number Type
ADSTB[1]# AE5 Source Synch Input/Output
A[3]# P4 Source Synch Input/Output
BCLK[0] B15 Bus Clock Input
A[4]# U4 Source Synch Input/Output
BCLK[1] B14 Bus Clock Input
A[5]# V3 Source Synch Input/Output
BNR# L1 Common Clock Input/Output
A[6]# R3 Source Synch Input/Output
BPM[0]# C8 Common Clock Output
A[7]# V2 Source Synch Input/Output
BPM[1]# B8 Common Clock Output
A[8]# W1 Source Synch Input/Output
BPM[2]# A9 Common Clock Output
A[9]# T4 Source Synch Input/Output
BPM[3]# C9 Common Clock Input/Output
A[10]# W2 Source Synch Input/Output
BPRI# J3 Common Clock Input
A[11]# Y4 Source Synch Input/Output
BR0# N4 Common Clock Input/Output
COMP[0] P25 Power/Other Input/Output
A[13]# U1 Source Synch Input/Output
COMP[1] P26 Power/Other Input/Output
A[14]# AA3 Source Synch Input/Output
COMP[2] AB2 Power/Other Input/Output
COMP[3] AB1 Power/Other Input/Output
A[16]# AA2 Source Synch Input/Output
D[0]# A19 Source Synch Input/Output
A[17]# AF4 Source Synch Input/Output
A[18]# AC4 Source Synch Input/Output
D[3]# B21 Source Synch Input/Output
A[21]# AD3 Source Synch Input/Output
A[22]# AE4 Source Synch Input/Output
A[24]# AB4 Source Synch Input/Output
D[8]# C20 Source Synch Input/Output
D[10]# D24 Source Synch Input/Output
D[11]# E24 Source Synch Input/Output
D[14]# E23 Source Synch Input/Output
A20M# C2 CMOS Input
D[16]# H23 Source Synch Input/Output
ADS# N2 Common Clock Input/Output

Table 23. Pin Listing by Pin Name Table 23. Pin Listing by Pin Name
Pin Signal Buffer Pin Signal Buffer

Pin Name Direction Pin Name Direction
Number Type Number Type
D[17]# G25 Source Synch Input/Output D[49]# AC23 Source Synch Input/Output
D[18]# L23 Source Synch Input/Output D[50]# AB24 Source Synch Input/Output
D[19]# M26 Source Synch Input/Output D[51]# AC20 Source Synch Input/Output
D[20]# H24 Source Synch Input/Output D[52]# AC22 Source Synch Input/Output
D[21]# F25 Source Synch Input/Output D[53]# AC25 Source Synch Input/Output
D[22]# G24 Source Synch Input/Output D[54]# AD23 Source Synch Input/Output
D[23]# J23 Source Synch Input/Output D[55]# AE22 Source Synch Input/Output
D[24]# M23 Source Synch Input/Output D[56]# AF23 Source Synch Input/Output
D[25]# J25 Source Synch Input/Output D[57]# AD24 Source Synch Input/Output
D[26]# L26 Source Synch Input/Output D[58]# AF20 Source Synch Input/Output
D[27]# N24 Source Synch Input/Output D[59]# AE21 Source Synch Input/Output
D[28]# M25 Source Synch Input/Output D[60]# AD21 Source Synch Input/Output
D[29]# H26 Source Synch Input/Output D[61]# AF25 Source Synch Input/Output
D[30]# N25 Source Synch Input/Output D[62]# AF22 Source Synch Input/Output
D[31]# K25 Source Synch Input/Output D[63]# AF26 Source Synch Input/Output
D[32]# Y26 Source Synch Input/Output DBR# A7 CMOS Output
D[33]# AA24 Source Synch Input/Output DBSY# M2 Common Clock Input/Output
D[34]# T25 Source Synch Input/Output DEFER# L4 Common Clock Input
D[35]# U23 Source Synch Input/Output DINV[0]# D25 Source Synch Input/Output
D[36]# V23 Source Synch Input/Output DINV[1]# J26 Source Synch Input/Output
D[37]# R24 Source Synch Input/Output DINV[2]# T24 Source Synch Input/Output
D[38]# R26 Source Synch Input/Output DINV[3]# AD20 Source Synch Input/Output
D[39]# R23 Source Synch Input/Output DPSLP# B7 CMOS Input
D[40]# AA23 Source Synch Input/Output DPWR# C19 Common Clock Input
D[41]# U26 Source Synch Input/Output DRDY# H2 Common Clock Input/Output
D[42]# V24 Source Synch Input/Output DSTBN[0]# C23 Source Synch Input/Output
D[43]# U25 Source Synch Input/Output DSTBN[1]# K24 Source Synch Input/Output
D[44]# V26 Source Synch Input/Output DSTBN[2]# W25 Source Synch Input/Output
D[45]# Y23 Source Synch Input/Output DSTBN[3]# AE24 Source Synch Input/Output
D[46]# AA26 Source Synch Input/Output DSTBP[0]# C22 Source Synch Input/Output
D[47]# Y25 Source Synch Input/Output DSTBP[1]# L24 Source Synch Input/Output
D[48]# AB25 Source Synch Input/Output DSTBP[2]# W24 Source Synch Input/Output


DSTBP[3]# AE25 Source Synch Input/Output RSVD E26 Reserved
FERR# D3 Open Drain Output RSVD G1 Reserved
GTLREF AD26 Power/Other Input RSVD AC1 Reserved
HIT# K3 Common Clock Input/Output SLP# A6 CMOS Input
HITM# K4 Common Clock Input/Output SMI# B4 CMOS Input
IERR# A4 Open Drain Output STPCLK# C6 CMOS Input
IGNNE# A3 CMOS Input TCK A13 CMOS Input
INIT# B5 CMOS Input TDI C12 CMOS Input
ITP_CLK[0] A16 CMOS input TDO A12 Open Drain Output
ITP_CLK[1] A15 CMOS input TEST1 C5 Test
LINT0 D1 CMOS Input TEST2 F23 Test
LINT1 D4 CMOS Input TEST3 C16 Test
LOCK# J2 Common Clock Input/Output THERMDA B18 Power/Other
PRDY# A10 Common Clock Output THERMDC A18 Power/Other
PREQ# B10 Common Clock Input THERMTRI

C17 Open Drain Output
P#
PROCHOT
B17 Open Drain Output
# TMS C11 CMOS Input
PSI# E1 CMOS Output TRDY# M3 Common Clock Input
PWRGOOD E4 CMOS Input TRST# B13 CMOS Input
REQ[0]# R2 Source Synch Input/Output VCC D6 Power/Other
REQ[1]# P3 Source Synch Input/Output VCC D8 Power/Other
REQ[2]# T2 Source Synch Input/Output VCC D18 Power/Other
REQ[3]# P1 Source Synch Input/Output VCC D20 Power/Other
REQ[4]# T1 Source Synch Input/Output VCC D22 Power/Other
RESET# B11 Common Clock Input VCC E5 Power/Other
RS[0]# H1 Common Clock Input VCC E7 Power/Other
RS[1]# K1 Common Clock Input VCC E9 Power/Other
RS[2]# L2 Common Clock Input VCC E17 Power/Other
RSVD AF7 Reserved VCC E19 Power/Other
RSVD B2 Reserved VCC E21 Power/Other
RSVD C14 Reserved VCC F6 Power/Other
RSVD C3 Reserved VCC F8 Power/Other


VCC F18 Power/Other VCC AB18 Power/Other
VCC G5 Power/Other VCC AC9 Power/Other
VCC G21 Power/Other VCC AC11 Power/Other
VCC H6 Power/Other VCC AC13 Power/Other
VCC H22 Power/Other VCC AC15 Power/Other
VCC J5 Power/Other VCC AC17 Power/Other
VCC J21 Power/Other VCC AC19 Power/Other
VCC K22 Power/Other VCC AD8 Power/Other
VCC U5 Power/Other VCC AD10 Power/Other
VCC V6 Power/Other VCC AD12 Power/Other
VCC V22 Power/Other VCC AD14 Power/Other
VCC W5 Power/Other VCC AD16 Power/Other
VCC W21 Power/Other VCC AD18 Power/Other
VCC Y6 Power/Other VCC AE9 Power/Other
VCC Y22 Power/Other VCC AE11 Power/Other
VCC AA5 Power/Other VCC AE13 Power/Other
VCC AA13 Power/Other VCC AF8 Power/Other
VCC AB6 Power/Other VCC AF18 Power/Other
VCC AB8 Power/Other VCCA[0] F26 Power/Other
VCC AB10 Power/Other VCCA[1] B1 Power/Other
VCC AB12 Power/Other VCCA[2] N1 Power/Other
VCC AB14 Power/Other VCCA[3] AC26 Power/Other
VCC AB16 Power/Other VCCP D10 Power/Other


VCCP D12 Power/Other VID[4] G4 CMOS Output
VCCP D14 Power/Other VID[5] H4 CMOS Output
VCCP D16 Power/Other VSS A2 Power/Other
VCCP E11 Power/Other VSS A5 Power/Other
VCCP F10 Power/Other VSS A14 Power/Other
VCCP K6 Power/Other VSS A26 Power/Other
VCCP L5 Power/Other VSS B3 Power/Other
VCCP L21 Power/Other VSS B6 Power/Other
VCCP M6 Power/Other VSS B9 Power/Other
VCCP M22 Power/Other VSS B12 Power/Other
VCCP N5 Power/Other VSS B16 Power/Other
VCCP N21 Power/Other VSS B19 Power/Other
VCCP P6 Power/Other VSS B22 Power/Other
VCCP P22 Power/Other VSS B25 Power/Other
VCCP R5 Power/Other VSS C1 Power/Other
VCCP R21 Power/Other VSS C4 Power/Other
VCCP T6 Power/Other VSS C7 Power/Other
VCCP T22 Power/Other VSS C10 Power/Other
VCCP U21 Power/Other VSS C13 Power/Other
VCCQ[0] P23 Power/Other VSS C15 Power/Other
VCCQ[1] W4 Power/Other VSS C18 Power/Other
VCCSENS VSS C21 Power/Other

AE7 Power/Other Output
E
VSS C24 Power/Other
VID[0] E2 CMOS Output
VSS D2 Power/Other
VID[1] F2 CMOS Output
VSS D5 Power/Other
VID[2] F3 CMOS Output
VSS D7 Power/Other
VID[3] G3 CMOS Output
VSS D9 Power/Other


VSS D11 Power/Other VSS G6 Power/Other
VSS D19 Power/Other VSS H3 Power/Other
VSS E3 Power/Other VSS J1 Power/Other
VSS E14 Power/Other VSS K2 Power/Other
VSS E25 Power/Other VSS L3 Power/Other
VSS F1 Power/Other VSS L6 Power/Other
VSS F7 Power/Other VSS M1 Power/Other
VSS F17 Power/Other VSS N3 Power/Other
VSS G2 Power/Other VSS N26 Power/Other


VSS P2 Power/Other VSS AA1 Power/Other
VSS R1 Power/Other VSS AA10 Power/Other
VSS T3 Power/Other VSS AA20 Power/Other
VSS T23 Power/Other VSS AB3 Power/Other
VSS T26 Power/Other VSS AB5 Power/Other
VSS U2 Power/Other VSS AB7 Power/Other
VSS V1 Power/Other VSS AB15 Power/Other
VSS W3 Power/Other VSS AB26 Power/Other
VSS W6 Power/Other VSS AC2 Power/Other
VSS Y2 Power/Other VSS AC12 Power/Other


VSS AC21 Power/Other VSS AF21 Power/Other
VSS AC24 Power/Other VSS AF24 Power/Other
VSS AD1 Power/Other VSSSENSE AF6 Power/Other Output
VSS AD4 Power/Other

Table 24. Pin Listing by Pin Number
VSS AD7 Power/Other
Pin Signal Buffer
VSS AD9 Power/Other Pin Name Direction
Number Type
VSS AD11 Power/Other
A2 VSS Power/Other
A3 IGNNE# CMOS Input
A4 IERR# Open Drain Output
A5 VSS Power/Other
A6 SLP# CMOS Input
A7 DBR# CMOS Output
A8 VSS Power/Other
VSS AE3 Power/Other
A9 BPM[2]# Common Clock Output
VSS AE6 Power/Other
A10 PRDY# Common Clock Output
VSS AE8 Power/Other
A11 VSS Power/Other
VSS AE10 Power/Other
A12 TDO Open Drain Output
A13 TCK CMOS Input
A14 VSS Power/Other
A15 ITP_CLK[1] CMOS input
A16 ITP_CLK[0] CMOS input
A17 VSS Power/Other
A18 THERMDC Power/Other
Input/
A19 D[0]# Source Synch
VSS AF2 Power/Other Output
VSS AF5 Power/Other A20 VSS Power/Other
VSS AF9 Power/Other Input/

Output
VSS AF11 Power/Other
Input/
VSS AF13 Power/Other Output
VSS AF15 Power/Other A23 VSS Power/Other
VSS AF17 Power/Other Input/

Output
VSS AF19 Power/Other

Table 24. Pin Listing by Pin Number Table 24. Pin Listing by Pin Number

Input/ Input/
A25 D[1]# Source Synch AB1 COMP[3] Power/Other
Output Output
A26 VSS Power/Other Input/

AB2 COMP[2] Power/Other
Output
AA1 VSS Power/Other
AB3 VSS Power/Other
Input/
AA2 A[16]# Source Synch
Output Input/
AB4 A[24]# Source Synch
Output
Input/
AA3 A[14]# Source Synch
Output AB5 VSS Power/Other
AA4 VSS Power/Other AB6 VCC Power/Other
AA5 VCC Power/Other AB7 VSS Power/Other
AA22 VSS Power/Other Input/

AB24 D[50]# Source Synch
Output
Input/
AA23 D[40]# Source Synch
Output Input/
AB25 D[48]# Source Synch
Output
Input/
Output AB26 VSS Power/Other
AA25 VSS Power/Other AC1 RSVD Reserved
Input/ AC2 VSS Power/Other

Output
Input/
AC3 A[20]# Source Synch
Output


Input/ Input/
AC4 A[18]# Source Synch AD5 A[26]# Source Synch
Output Output
AC5 VSS Power/Other Input/

AD6 A[28]# Source Synch
Output
Input/
Output AD7 VSS Power/Other
Input/ AD8 VCC Power/Other

Output
AD9 VSS Power/Other
AC8 VSS Power/Other
AD10 VCC Power/Other
AC9 VCC Power/Other
AD11 VSS Power/Other
AC10 VSS Power/Other
AC11 VCC Power/Other
Input/
AD20 DINV[3]# Source Synch
AC19 VCC Power/Other Output
Input/ Input/
AC20 D[51]# Source Synch AD21 D[60]# Source Synch
Output Output
AC21 VSS Power/Other AD22 VSS Power/Other
Input/ Input/
Output Output
Input/ Input/
Output Output
AC24 VSS Power/Other AD25 VSS Power/Other
Input/ AD26 GTLREF Power/Other

AC25 D[53]# Source Synch
Output
Input/
AE1 A[30]# Source Synch
AC26 VCCA[3] Power/Other Output
AD1 VSS Power/Other Input/

AE2 A[27]# Source Synch
Output
Input/
AD2 A[23]# Source Synch
Output AE3 VSS Power/Other
Input/ Input/
AD3 A[21]# Source Synch AE4 A[22]# Source Synch
Output Output
AD4 VSS Power/Other Input/

AE5 ADSTB[1]# Source Synch
Output


AE6 VSS Power/Other AF8 VCC Power/Other
AE7 VCCSENSE Power/Other Output AF9 VSS Power/Other
AE9 VCC Power/Other AF11 VSS Power/Other
AE18 VSS Power/Other Input/

AF20 D[58]# Source Synch
Output
AE19 VCC Power/Other
AF21 VSS Power/Other
AE20 VSS Power/Other
Input/
Input/ Output
AE21 D[59]# Source Synch
Output
Input/
Input/ Output
AE22 D[55]# Source Synch
Output
AF24 VSS Power/Other
Input/
Input/ Output
AE24 DSTBN[3]# Source Synch
Output
Input/
Input/ Output
AE25 DSTBP[3]# Source Synch
Output
B1 VCCA[1] Power/Other
B2 RSVD Reserved
Input/
AF1 A[31]# Source Synch
Output B3 VSS Power/Other
AF2 VSS Power/Other B4 SMI# CMOS Input
Input/ B5 INIT# CMOS Input

Output
B6 VSS Power/Other
Input/
Output B7 DPSLP# CMOS Input
AF5 VSS Power/Other B8 BPM[1]# Common Clock Output
AF6 VSSSENSE Power/Other Output B9 VSS Power/Other
AF7 RSVD Reserved B10 PREQ# Common Clock Input


B11 RESET# Common Clock Input C14 RSVD Reserved
B12 VSS Power/Other C15 VSS Power/Other
B13 TRST# CMOS Input C16 TEST3 Test
B14 BCLK[1] Bus Clock Input THERMTRIP

C17 Open Drain Output
#
B15 BCLK[0] Bus Clock Input
C18 VSS Power/Other
B16 VSS Power/Other
C19 DPWR# Common Clock Input
B17 PROCHOT# Open Drain Output
Input/
C20 D[8]# Source Synch
B18 THERMDA Power/Other Output
Input/ Input/
B20 D[7]# Source Synch C22 DSTBP[0]# Source Synch
Output Output
Input/ Input/
B21 D[3]# Source Synch C23 DSTBN[0]# Source Synch
Output Output
Input/ Input/
B23 D[13]# Source Synch C25 D[15]# Source Synch
Output Output
Input/ Input/
B24 D[9]# Source Synch C26 D[12]# Source Synch
Output Output
B25 VSS Power/Other D1 LINT0 CMOS Input
Input/ D2 VSS Power/Other

B26 D[5]# Source Synch
Output
D3 FERR# Open Drain Output
C1 VSS Power/Other
D4 LINT1 CMOS Input
C2 A20M# CMOS Input
D5 VSS Power/Other
C3 RSVD Reserved
D6 VCC Power/Other
C4 VSS Power/Other
D7 VSS Power/Other
C5 TEST1 Test
D8 VCC Power/Other
C6 STPCLK# CMOS Input
D9 VSS Power/Other
C7 VSS Power/Other
D10 VCCP Power/Other
C8 BPM[0]# Common Clock Output
D11 VSS Power/Other
Input/
C9 BPM[3]# Common Clock
Output D12 VCCP Power/Other
C10 VSS Power/Other D13 VSS Power/Other
C11 TMS CMOS Input D14 VCCP Power/Other
C12 TDI CMOS Input D15 VSS Power/Other
C13 VSS Power/Other D16 VCCP Power/Other


D17 VSS Power/Other E22 VSS Power/Other
D18 VCC Power/Other Input/

E23 D[14]# Source Synch
Output
D19 VSS Power/Other
Input/
E24 D[11]# Source Synch
D20 VCC Power/Other Output
D21 VSS Power/Other E25 VSS Power/Other
D22 VCC Power/Other E26 RSVD Reserved
D23 VSS Power/Other F1 VSS Power/Other
Input/ F2 VID[1] CMOS Output

D24 D[10]# Source Synch
Output
F3 VID[2] CMOS Output
Input/
D25 DINV[0]# Source Synch
Output F4 VSS Power/Other
D26 VSS Power/Other F5 VSS Power/Other
E1 PSI# CMOS Output F6 VCC Power/Other
E2 VID[0] CMOS Output F7 VSS Power/Other
E3 VSS Power/Other F8 VCC Power/Other
E4 PWRGOOD CMOS Input F9 VSS Power/Other
E5 VCC Power/Other F10 VCCP Power/Other
E6 VSS Power/Other F11 VSS Power/Other
E11 VCCP Power/Other F16 VCCP Power/Other
E13 VCCP Power/Other F18 VCC Power/Other
E15 VCCP Power/Other F20 VCC Power/Other
E17 VCC Power/Other F22 VCC Power/Other
E18 VSS Power/Other F23 TEST2 Test
E19 VCC Power/Other F24 VSS Power/Other
E20 VSS Power/Other Input/

F25 D[21]# Source Synch
Output
E21 VCC Power/Other


F26 VCCA[0] Power/Other J4 VSS Power/Other
G1 RSVD Reserved J5 VCC Power/Other
G2 VSS Power/Other J6 VSS Power/Other
G3 VID[3] CMOS Output J21 VCC Power/Other
G4 VID[4] CMOS Output J22 VSS Power/Other
G5 VCC Power/Other Input/

J23 D[23]# Source Synch
Output
G6 VSS Power/Other
J24 VSS Power/Other
G21 VCC Power/Other
Input/
J25 D[25]# Source Synch
G22 VSS Power/Other Output
G23 VSS Power/Other Input/

J26 DINV[1]# Source Synch
Output
Input/
G24 D[22]# Source Synch
Output K1 RS[1]# Common Clock Input
Input/ K2 VSS Power/Other

G25 D[17]# Source Synch
Output
Input/
K3 HIT# Common Clock
G26 VSS Power/Other Output
H1 RS[0]# Common Clock Input Input/

K4 HITM# Common Clock
Output
Input/
H2 DRDY# Common Clock
Output K5 VSS Power/Other
H3 VSS Power/Other K6 VCCP Power/Other
H4 VID[5] CMOS Output K21 VSS Power/Other
H5 VSS Power/Other K22 VCC Power/Other
H6 VCC Power/Other K23 VSS Power/Other
H21 VSS Power/Other Input/

K24 DSTBN[1]# Source Synch
Output
H22 VCC Power/Other
Input/
K25 D[31]# Source Synch
Input/ Output
H23 D[16]# Source Synch
Output
K26 VSS Power/Other
Input/
Output Input/
L1 BNR# Common Clock
Output
H25 VSS Power/Other
L2 RS[2]# Common Clock Input
Input/
Output L3 VSS Power/Other
J1 VSS Power/Other L4 DEFER# Common Clock Input
Input/ L5 VCCP Power/Other

J2 LOCK# Common Clock
Output
L6 VSS Power/Other
J3 BPRI# Common Clock Input
L21 VCCP Power/Other


L22 VSS Power/Other Input/

N25 D[30]# Source Synch
Output
Input/
L23 D[18]# Source Synch
Output N26 VSS Power/Other
Input/ Input/
L24 DSTBP[1]# Source Synch P1 REQ[3]# Source Synch
Output Output
L25 VSS Power/Other P2 VSS Power/Other
Input/ Input/
L26 D[26]# Source Synch P3 REQ[1]# Source Synch
Output Output
M1 VSS Power/Other Input/

P4 A[3]# Source Synch
Output
Input/
M2 DBSY# Common Clock
Output P5 VSS Power/Other
M3 TRDY# Common Clock Input P6 VCCP Power/Other
M4 VSS Power/Other P21 VSS Power/Other
M5 VSS Power/Other P22 VCCP Power/Other
M6 VCCP Power/Other P23 VCCQ[0] Power/Other
M21 VSS Power/Other P24 VSS Power/Other
M22 VCCP Power/Other Input/

P25 COMP[0] Power/Other
Output
Input/
M23 D[24]# Source Synch
Output Input/
P26 COMP[1] Power/Other
Output
M24 VSS Power/Other
R1 VSS Power/Other
Input/
Output Input/
R2 REQ[0]# Source Synch
Output
Input/
Output Input/
R3 A[6]# Source Synch
Output
N1 VCCA[2] Power/Other
R4 VSS Power/Other
Input/
N2 ADS# Common Clock
Output R5 VCCP Power/Other
N3 VSS Power/Other R6 VSS Power/Other
Input/ R21 VCCP Power/Other

N4 BR0# Common Clock
Output
R22 VSS Power/Other
N5 VCCP Power/Other
Input/
R23 D[39]# Source Synch
N6 VSS Power/Other Output
N21 VCCP Power/Other Input/

Output
N22 VSS Power/Other
R25 VSS Power/Other
N23 VSS Power/Other
Input/
Input/ Output
N24 D[27]# Source Synch
Output


Input/ Input/
T1 REQ[4]# Source Synch V3 A[5]# Source Synch
Output Output
Input/ V4 VSS Power/Other

T2 REQ[2]# Source Synch
Output
V5 VSS Power/Other
T3 VSS Power/Other
V6 VCC Power/Other
Input/
T4 A[9]# Source Synch
Output V21 VSS Power/Other
T5 VSS Power/Other V22 VCC Power/Other
T6 VCCP Power/Other Input/

V23 D[36]# Source Synch
Output
T21 VSS Power/Other
Input/
V24 D[42]# Source Synch
T22 VCCP Power/Other Output
T23 VSS Power/Other V25 VSS Power/Other
Input/ Input/
T24 DINV[2]# CMOS V26 D[44]# Source Synch
Output Output
Input/ Input/
T25 D[34]# Source Synch W1 A[8]# Source Synch
Output Output
T26 VSS Power/Other Input/

W2 A[10]# Source Synch
Output
Input/
U1 A[13]# Source Synch
Output W3 VSS Power/Other
U2 VSS Power/Other W4 VCCQ[1] Power/Other
Input/ W5 VCC Power/Other

U3 ADSTB[0]# Source Synch
Output
W6 VSS Power/Other
Input/
U4 A[4]# Source Synch
Output W21 VCC Power/Other
U5 VCC Power/Other W22 VSS Power/Other
U6 VSS Power/Other W23 VSS Power/Other
U21 VCCP Power/Other Input/

W24 DSTBP[2]# Source Synch
Output
U22 VSS Power/Other
Input/
W25 DSTBN[2]# Source Synch
Input/ Output
U23 D[35]# Source Synch
Output
W26 VSS Power/Other
U24 VSS Power/Other
Input/
Y1 A[12]# Source Synch
Input/ Output
Output
Y2 VSS Power/Other
Input/
Output Input/
Output
V1 VSS Power/Other
Input/
Input/ Output
V2 A[7]# Source Synch
Output

Table 24. Pin Listing by Pin Number
Pin Signal Buffer

Pin Name Direction
Number Type
Y5 VSS Power/Other
Y6 VCC Power/Other
Y21 VSS Power/Other
Y22 VCC Power/Other
Input/
Y23 D[45]# Source Synch
Output
Y24 VSS Power/Other
Input/
Output
Input/
Output

4.2 Alphabetical Signals Reference
Table 25. Signal Description (Sheet 1 of 7)
Name Type Description
32
A[31:3]# (Address) define a 2 -byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
Input/
A[31:3]# must connect the appropriate pins of both agents on the Intel Celeron M
Output
processor FSB. A[31:3]# are source synchronous signals and are latched into
the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which
are sampled before RESET# is deasserted.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is
A20M# Input only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
Input/
ADS# activation to begin parity checking, protocol checking, address decode, internal
Output
snoop, or deferred reply ID match operations associated with the new
transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
Input/ Signals Associated Strobe

ADSTB[1:0]#
Output
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB
agents must receive these signals to drive their outputs and latch their inputs.
BCLK[1:0] Input
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
Input/
BNR# unable to accept new bus transactions. During a bus stall, the current bus owner
Output
cannot issue any new transactions.
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
BPM[2:0]# Output
performance. BPM[3:0]# should connect the appropriate pins of all Intel Celeron
BPM[3] Input/ M processor FSB agents.This includes debug or performance monitoring tools.
Output
Please refer to the platform design guides and ITP700 Debug Port Design Guide
for more detailed information.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It
must connect the appropriate pins of both FSB agents. Observing BPRI# active
(as asserted by the priority agent) causes the other agent to stop issuing new
BPRI# Input
requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0# is used by the processor to request the bus. The arbitration is done
Input/
BR0# between the Intel Celeron M processor (Symmetric Agent) and MCH-M (High
Output
Priority Agent) of the Intel 852GM, Intel 855PM, and Intel 855GM chipsets.

COMP[3:0] must be terminated on the system board using precision (1%

COMP[3:0] Analog tolerance) resistors. Refer to the platform design guides for more details on
implementation.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the FSB agents, and must connect the appropriate pins on both agents.
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
DSTBN#/
Input/ Data Group DINV#
D[63:0]# DSTBP#
Output
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
Furthermore, the DINV# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DINV# signal. When the DINV#
signal is active, the corresponding data group is inverted and therefore sampled
active high.
DBR# (Data Bus Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port interposer
DBR# Output
so that an in-target probe can drive system reset. If a debug port is implemented
in the system, DBR# is a no connect. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
Input/ the FSB to indicate that the data bus is in use. The data bus is released after
DBSY#
Output DBSY# is deasserted. This signal must connect the appropriate pins on both
FSB agents.
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
DEFER# Input
responsibility of the addressed memory or Input/Output agent. This signal must
connect the appropriate pins of both FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the
polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the
data on the data bus is inverted. The bus agent will invert the data bus signals if
more than half the bits, within the covered group, would change level in the next
cycle.
DINV[3:0]# Assignment To Data Bus

Input/
DINV[3:0]# Bus Signal Data Bus Signals
Output
DINV[3]# D[63:48]#
DINV[2]# D[47:32]#
DINV[1]# D[31:16]#
DINV[0]# D[15:0]#

DPSLP# when asserted on the platform causes the processor to transition from
the Sleep State to the Deep Sleep state. In order to return to the Sleep State,
DPSLP# Input DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the MCH-M component of the Intel 855PM, Intel 855GM, or
852GM chipset.
DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used
DPWR# Input
to reduce power on the Intel Celeron M processor data bus input buffers.
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
Input/ indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY#
Output DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both FSB agents.
Data strobe used to latch in D[63:0]#.
Input/ D[15:0]#, DINV[0]# DSTBN[0]#

DSTBN[3:0]#
Output
D[31:16]#, DINV[1]# DSTBN[1]#
D[47:32]#, DINV[2]# DSTBN[2]#
D[63:48]#, DINV[3]# DSTBN[3]#
Data strobe used to latch in D[63:0]#.
Input/ D[15:0]#, DINV[0]# DSTBP[0]#

DSTBP[3:0]#
Output
D[31:16]#, DINV[1]# DSTBP[1]#
D[47:32]#, DINV[2]# DSTBP[2]#
D[63:48]#, DINV[3]# DSTBP[3]#
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed

signal and its meaning is qualified with STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
FERR#/PBE# Output processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event. For additional information on the pending break event
functionality, including identification of support of the feature and enable/disable
information, refer to Volume 3 of the Intel Architecture Software Developer’s
Manual and the Intel Processor Identification and CPUID Instruction application
note.
For termination requirements please refer to the platform design guides.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine
GTLREF Input
if a signal is a logical 0 or logical 1. Please refer to the platform design guides for
details on GTLREF implementation.

Input/
HIT# Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Either FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# Input/ HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the FSB. This transaction may optionally be converted to an external error
IERR# Output signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted
until the assertion of RESET#, BINIT#, or INIT#.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# Input IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure recognition of
INIT# Input this signal following an Input/Output Write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
ITP_CLK[1:0] Input used as BCLK[1:0] references for a debug port implemented on an interposer. If
a debug port is implemented in the system, ITP_CLK[1:0] are no connects.
These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those
®
LINT[1:0] Input names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of both FSB agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
Input/ transaction to the end of the last transaction.
LOCK#
Output When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.

Probe Ready signal used by debug tools to determine processor debug

readiness.
PRDY# Output
Please refer to the ITP700 Debug Port Design Guide and the platform design
guides for more implementation details.
Probe Request signal used by debug tools to request debug operation of the
processor.
PREQ# Input
guides for more implementation details.
PROCHOT# (Processor Hot) will go active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
PROCHOT# Output has been activated, if enabled. See Chapter 5 for more details.
This signal may require voltage translation on the motherboard. Please refer to
the platform design guides for more details.
Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep ). See Section 2.1.4 for more details.
PSI# Output Please refer to the IMVP-IV Mobile Processor and Mobile Chipset Voltage
Regulation with Power Status Indicator (PSI) Specification for more details on
the PSI# signal.
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven inactive at
PWRGOOD Input any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
Input/
REQ[4:0]# agents. They are asserted by the current bus owner to define the currently active
Output
transaction type. These signals are source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least two milliseconds after
VCC and BCLK have reached their proper specifications. On observing active
RESET#, both FSB agents will deassert their outputs within two clocks. All
RESET# Input processor straps must be valid within the specified setup time before RESET# is
deasserted.
guides for termination requirements and implementation details. There is a 55
ohm (nominal) on die pull-up resistor on this signal.
RS[2:0]# (Response Status) are driven by the response agent (the agent
RS[2:0]# Input responsible for completion of the current transaction), and must connect the
These pins are RESERVED and must be left unconnected on the board.
Reserved/
However, it is recommended that routing channels to these pins on the board be
RSVD No
kept open for possible future use. Please refer to the platform design guides for
Connect
more details.

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, deassertion of SLP#, and
SLP# Input
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units. If DPSLP# is asserted while in
the Sleep state, the processor will exit the Sleep state and transition to the Deep
Sleep state.
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
SMI# Input Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate
its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
STPCLK# Input
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TCK Input
guides for termination requirements and implementation details.
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDI Input
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG* specification support.
TDO Output
TEST1, TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing
TEST2, Input option connection to VSS separately using 1-k, pull-down resistors. Please refer
TEST3 to the platform design guides for more details.
THERMDA Other Thermal Diode Anode.
THERMDC Other Thermal Diode Cathode.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
to ensure that there are no false trips. The processor will stop all execution when
THERMTRIP# Output the junction temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TMS Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

TRDY# Input receive a write or implicit writeback data transfer. TRDY# must connect the
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. Please refer to the ITP700 Debug Port
TRST# Input
Design Guide and the platform design guides for termination requirements and
implementation details.
VCC Input Processor core power supply.
VCCA provides isolated power for the internal processor core PLLs. Refer to the
VCCA[3:0] Input
platform design guides for complete implementation details.
VCCP Input Processor I/O power supply.
Quiet power supply for on die COMP circuitry. These pins should be connected
VCCQ[1:0] Input to VCCP on the motherboard. However, these connections should enable addition
of decoupling on the VCCQ lines if necessary.
VCCSENSE is an isolated low impedance connection to processor core power
(VCC). It can be used to sense or measure power near the silicon with little noise.
VCCSENSE Output
Please refer to the platform design guides for termination recommendations and
more details.
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (Vcc). Unlike some previous generations of processors, these
are CMOS signals that are driven by the Intel Celeron M processor. The voltage
supply for these pins must be valid before the VR can supply Vcc to the
VID[5:0] Output processor. Conversely, the VR output must be disabled until the voltage supply
for the VID pins becomes valid. The VID pins are needed to support the
processor voltage specification variations. See Table 2 for the encoding of these
pins. The VR must supply the voltage that is requested by the pins, or disable
itself.
VSSSENSE is an isolated low impedance connection to processor core VSS. It can
be used to sense or measure ground near the silicon with little noise. Please
VSSSENSE Output
refer to the platform design guides for termination recommendations and more
details.

Thermal Specifications and Design Considerations
5 Thermal Specifications and

Design Considerations
The Intel Celeron M processor requires a thermal solution to maintain temperatures within
operating limits. A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions include active or passive heatsinks or
heat exchangers attached to the processor exposed die. The solution should make firm contact with
the die while maintaining processor mechanical specifications such as pressure. A typical system
level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally
coupled to the processor using a heat pipe or direct die attachment. A secondary fan or air from the
processor fan may also be used to cool other platform components or lower the internal ambient
temperature within the system. The processor must remain within the minimum and maximum
junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value
listed in Table 26. The maximum junction temperature is defined by an activation of the Intel
Thermal Monitor in the processor.
Refer to Section 5.1.2 for more details. Analysis indicates that real applications are unlikely to
cause the processor to consume the theoretical maximum power dissipation for sustained time
periods. Intel recommends that complete thermal solution designs target the TDP indicated in
Table 26. The Intel® Thermal Monitor feature is designed to help protect the processor in the
unlikely event that an application exceeds the TDP recommendation for a sustained period of time.
For more details on the usage of this feature, refer to Section 5.1.2. In all cases the Intel Thermal
Monitor feature must be enabled for the processor to remain within specification.

Table 26. Power Specifications for the Intel Celeron M Processor
Core Frequency
Symbol Thermal Design Power Unit Notes
& Voltage
1.20 GHz & 1.356 V 24.5

1.30 GHz & 1.356 V 24.5
1.40 GHz & 1.356 V 24.5
1.50 GHz & 1.356 V 24.5 At 100 °C, Notes 1,
TDP W
4
ULV Intel Celeron Mprocessor
800 MHz and 1.004 V 7
900 MHz and 1.004 V 7
Auto Halt, Stop Grant Power

at:
1.356 V (1.20 GHz) 9.9
1.356 V (1.30 GHz) 9.5
PAH, 9.1
1.356 V (1.40 GHz) W At 50 °C, Note 2
PSGNT 1.356 V (1.50 GHz) 8.7
1.004 V (800 MHz ULV) 2.0
1.004 V (900 MHz ULV) 2.0
Sleep Power at:

1.356 V (1.20 GHz) 9.7
1.356 V (1.30 GHz) 9.3
1.356 V (1.40 GHz) 8.9
PSLP 1.356 V (1.50 GHz) 8.5 W At 50 °C, Note 2
1.004 V ( 800 MHz ULV) 1.9
1.004 V ( 900 MHz ULV) 1.9
Deep Sleep Power at:

1.356 V (1.20 GHz) 7.7
1.356 V (1.30 GHz) 7.3
1.356 V (1.40 GHz) 6.9
PDSLP 1.356 V (1.50 GHz) 6.6 W At 35 °C, Note 2
1.004 V ( 800 MHz ULV) 1.5
1.004 V ( 900 MHz ULV) 1.4
TJ Junction Temperature 0 100 °C Notes 3, 4
NOTES:
1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum
theoretical power the processor can dissipate.
2. Not 100% tested. These power specifications are determined by characterization of the processor currents at
higher temperatures and extrapolating the values for the temperature indicated.
3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to
indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.

5.1 Thermal Specifications
5.1.1 Thermal Diode

The Intel Celeron M processor incorporates two methods of monitoring die temperature, the Intel
Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must
be used to determine when the maximum specified processor junction temperature has been
reached. The second method, the thermal diode, can be read by an off-die analog/digital converter
(a thermal sensor) located on the motherboard, or a standalone measurement kit. The thermal diode
may be used to monitor the die temperature of the processor for thermal management or
instrumentation purposes but cannot be used to indicate that the maximum TJ of the processor has
been reached. Please see Section 5.1.2 for thermal diode usage recommendation when the
PROCHOT# signal is not asserted.
Table 27 and Table 28 provide the diode interface and specifications.
Note: The reading of the external thermal sensor (on the motherboard) connected to the processor
thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die.
This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the
location of the thermal diode and the hottest location on the die, and time based variations in the die
temperature measurement. Time based variations can occur when the sampling rate of the thermal
diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change.
The offset between the thermal diode based temperature reading and the Intel Thermal Monitor
reading may be characterized using the Intel Thermal Monitor’s automatic mode activation of
thermal control circuit. This temperature offset must be taken into account when using the
processor thermal diode to implement power management events.
Table 27. Thermal Diode Interface
Signal Name Pin/Ball Number Signal Description
THERMDA B18 Thermal diode anode
THERMDC A18 Thermal diode cathode
Table 28. Thermal Diode Specifications
IFW Forward Bias Current 5 300 µA 1
n Diode Ideality Factor 1.00151 1.00220 1.00289 2, 3, 4
RT Series Resistance 3.06 ohms 2, 3, 5
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not
support or recommend operation of the thermal diode when the processor power supplies are not within their
specified tolerance range.
2. Characterized at 100 °C.
3. Not 100% tested. Specified by design/characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:

IFW=Is x (e(qVD/nkT) -1)

Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant,
and T = absolute temperature (Kelvin).
5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction
temperature. RT as defined includes the pins of the processor but does not include any socket resistance or
board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by
remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Another application is that a temperature offset can be manually calculated and programmed into an offset
register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT x (N-1) x IFWmin]/[(no/q) x ln N]
5.1.2 Intel Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the
processor silicon reaches its maximum operating temperature. The temperature at which the Intel
Thermal Monitor activates the thermal control circuit (TCC) is not user configurable and is not
software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched
(and serviced during the time that the clocks are on) while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the TCC would
only be activated for very short periods of time when running the most power intensive
applications. The processor performance impact due to these brief periods of TCC activation is
expected to be so minor that it would not be detectable. An under-designed thermal solution that is
not able to prevent excessive activation of the TCC in the anticipated ambient environment may
cause a noticeable performance loss, and may affect the long-term reliability of the processor. In
addition, a thermal solution that is significantly underdesigned may not be capable of cooling the
processor even when the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting and
stopping) the processor core clocks when the processor silicon reaches its maximum operating
temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and
On-Demand mode. If both modes are activated, automatic mode takes precedence. The Intel
Thermal Monitor Automatic Mode must be enabled via BIOS for the processor to be operating
within specifications.This mode is selected by writing values to the Model Specific Registers
(MSRs) of the processor. After the automatic mode is enabled, the TCC will activate only when the
internal die temperature reaches the maximum allowed value for operation.
When Intel Thermal Monitor is enabled, and a high temperature situation exists, the clocks will be
modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are
processor speed dependent and will decrease linearly as processor core frequencies increase. After
the temperature has returned to a non-critical level, modulation ceases and the TCC goes inactive.
A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the
TCC when the processor temperature is near the trip point. The duty cycle is factory configured
and cannot be modified. Also, the automatic mode does not require any additional hardware,
software drivers or interrupt handling routines. Processor performance will be decreased by the
same amount as the duty cycle when the TCC is active, however, with a properly designed and
characterized thermal solution the TCC most likely will never be activated, or will be activated
only briefly during the most power intensive applications.
The TCC may also be activated using On-Demand mode. If bit 4 of the ACPI Intel Thermal
Monitor Control register is written to a "1", the TCC will be activated immediately, independent of
the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of
the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor
Control Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, in On-Demand
mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in

12.5% increments. On-Demand mode can be used at the same time automatic mode is enabled,
however, if the system tries to enable the TCC via On-Demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its
temperature is above the thermal trip point. Bus snooping and interrupt latching are also active
while the TCC is active.
Note: PROCHOT# will not be asserted when the processor is in the Stop-Grant, Sleep, and Deep Sleep
low power states (internal clocks stopped), hence the thermal diode reading must be used as a
safeguard to maintain the processor junction temperature within the 100 °C (maximum)
specification. If the platform thermal solution is not able to maintain the processor junction
temperature within the maximum specification, the system must initiate an orderly shutdown to
prevent damage. If the processor enters one of the above low power states with PROCHOT#
already asserted, PROCHOT# will remain asserted until the processor exits the low power state
and the processor junction temperature drops below the thermal trip point.
If automatic mode is disabled the processor will be operating out of specification. Whether the
automatic or On-Demand modes are enabled or not, in the event of a catastrophic cooling failure,
the processor will automatically shut down when the silicon has reached a temperature of
approximately 125 °C. At this point the FSB signal THERMTRIP# will go active. THERMTRIP#
activation is independent of processor activity and does not generate any bus cycles. When
THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified
in Chapter 3.


Debug Tools Specifications
6 Debug Tools Specifications

Please refer to the ITP700 Debug Port Design Guide and the platform design guides for
information regarding debug tools specifications.
6.1 Logic Analyzer Interface (LAI)

Intel is working with logic analyzer vendors to provide LAIs for use in debugging Intel Celeron M
processor systems. The following information is general in nature. Specific information must be
obtained from the logic analyzer vendor.
Due to the complexity of Intel Celeron M processor-based systems, the LAI is critical in providing
the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind
when designing a Intel Celeron M processor-based system that can make use of an LAI:
mechanical and electrical.
6.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the Intel Celeron M processor. The LAI pins
plug into the socket, while the Intel Celeron M processor pins plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection between the
Intel Celeron M processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be obtained from the
logic analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system.
6.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that their tool will work in the system. Contact the logic analyzer vendor for electrical
specifications and load models for the LAI solution they provide.

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Intel® Celeron® M Processor

Order Number: 300302-003

2 Intel® Celeron® M Processor Datasheet

Intel® Celeron® M Processor Datasheet 3

4 Intel® Celeron® M Processor Datasheet

Intel® Celeron® M Processor Datasheet 5

-001 300302 Initial release January 2004

6 Intel® Celeron® M Processor Datasheet

Intel® Celeron® M Processor Datasheet 7

The new packed, double-precision, floating-point instructions enhance performance for

8 Intel® Celeron® M Processor Datasheet

Intel 855PM Chipset Platform Design Guide http://developer.intel.com

Intel 855PM Chipset Design Guide Update http://developer.intel.com

Intel 855PM Chipset Datasheet http://developer.intel.com

IIntel 855GM/855GME Chipset Platform Design Guide http://developer.intel.com

Intel 855GM/855GME Chipset Datasheet http://developer.intel.com

Intel 855GM Specification Update http://developer.intel.com

Intel 852GM Chipset Datasheet http://developer.intel.com

Intel Architecture Software Developer's Manual http://developer.intel.com

Volume 1: Basic Architecture 253665

1.3 State of Data

Intel® Celeron® M Processor Datasheet 9

10 Intel® Celeron® M Processor Datasheet

2 Low Power Features

2.1 Clock Control and Low Power States

STPCLK# asserted SLP# asserted

2.1.1 Normal State

2.1.2 AutoHALT Power-Down State

Intel® Celeron® M Processor Datasheet 11

2.1.3 Stop-Grant State

2.1.4 HALT/Grant Snoop State

2.1.5 Sleep State

12 Intel® Celeron® M Processor Datasheet

2.1.6 Deep Sleep State

2.2 FSB Low Power Enhancements

Intel® Celeron® M Processor Datasheet 13

• BPRI# control for address and control input buffers

2.3 Processor Power Status Indicator (PSI#) Signal

14 Intel® Celeron® M Processor Datasheet

3.1 FSB and GTLREF

3.2 Power and Ground Pins

3.3 Decoupling Guidelines

Intel® Celeron® M Processor Datasheet 15

3.3.1 VCC Decoupling

3.3.2 FSB AGTL+ Decoupling

3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking

3.4 Voltage Identification

16 Intel® Celeron® M Processor Datasheet

Table 2. Voltage Identification Definition

3.5 Catastrophic Thermal Protection

Intel® Celeron® M Processor Datasheet 17

3.6 Signal Terminations and Unused Pins

3.7 FSB Signal Groups

18 Intel® Celeron® M Processor Datasheet

Table 3. FSB Pin Groups

Synchronous BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]#

3.8 CMOS Signals