Department Of

Electronics & Communication

Engineering

LABORATORY MANUAL
FOR

VLSI LABORATORY II
VLSI FRONT END DESIGN PROGRAMS
M.Tech I Year II Sem
M.Tech VLSI DESIGN

Dept. of Electronics & Communication Engineering

BALAJI INSTITUTE OF ENGINEERING &

SCIENCES
Laknepally, Narsampet, Warangal

Dept. of Electronics & Communication Engineering

VLSI LABORATORY II
VLSI BACK END DESIGN PROGRAMS
M.Tech VLSI DESIGN I Year II Sem.
LIST OF EXPERIMENTS
VLSI BACK END DESIGN PROGRAMS:
1. Introduction to layout design rules
2. CMOS inverter
3. CMOS NAND/NOR gates
4. CMOS XOR gates
5. CMOS 1-bit full adder
6. Latch
7. Layout of any combinational circuit (complex CMOS logic
gate)-Learning about data paths
Grey code to Binary code converter
8. Static/ Dynamic logic circuits (register cell) - SRAM

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(1) INTRODUCTION TO LAYOUT DESIGN RULES

1. The physical mask layout of any circuit to be manufactured using a particular process
must conform to a set of geometric constraints or rules, which are generally called
layout design rules.
2. These rules usually specify the minimum allowable line widths for physical objects onchip such as metal and polysilicon interconnects or diffusion areas, minimum feature
dimensions, and inimum allowable separations between two such features.

3. These rules usually specify the minimum allowable line widths for physical objects onchip such as metal and polysilicon interconnects or diffusion areas, minimum feature
dimensions, and inimum allowable separations between two such features.
4. The main objective of design rules is to achieve a high overall yield and reliability
while using the mallest possible silicon area, for any circuit to be manufactured with a
particular process.
5. The layout design rules which are specified for a particular fabrication process
normally represent a reasonable optimum point in terms of yield and density.

6. A layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all specified
design rules may result in a circuit Which is not functional and/or has very low yield.
7. To summarize, we can say, in general, that observing the layout design rules
significantly increases the probability of fabricating a successful product with high
yield.

8. The design rules are usually described in two ways :

(I)

(II)

MICRON RULES, in which the layout constraints such as minimum feature sizes
and minimum allowable feature separations, are stated in terms of absolute
dimensions in micrometers, OR
LAMBDA RULES, which specify the layout constraints in terms of a single
parameter and, thus, allow linear, proportional scaling of all geometrical
constraints.

9. Lambda-based layout design rules were originally devised to simplify the

industrystandard micron-based design rules and to allow scaling capability for various
processes. It must be emphasized, however, that most of the submicron CMOS process
design rules do not lend themselves to straightforward linear scaling. The use of
lambda-based design rules must therefore be handled with caution in sub-micron

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geometries. In the following, we present a sample set of the lambda-based layout design
rules devised for the MOSIS CMOS process.

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CADENCE LAYOUT DESIGN RULES

RULE NUMBER

DESCRIPTION

L-RULE

R1

Minimum active area width

3L

R2

Minimum active area spacing

R3

Minimum poly width

R4

Minimum poly spacing

R5

Minimum gate extension of poly over active

2L

R6

Minimum poly-active edge spacing

1L

3L
2L
2L

(poly outside active area)

R7

Minimum poly-active edge spacing

3L

(poly inside active area)

R8

Minimum metal width

3L

R9

Minimum metal spacing

3L

R10

Poly contact size

2L

R11

Minimum poly contact spacing

2L

R12

Minimum poly contact to poly edge spacing

R13

Minimum poly contact to metal edge spacing

R14

Minimum poly contact to active edge spacing 3 L

R15

Active contact size

2L

R16

Minimum active contact spacing

2L

1L
1L

(on the same active region)

R17

Minimum active contact to active edge spacing

1L

R18

Minimum active contact to metal edge spacing

1L

R19

Minimum active contact to poly edge spacing 3 L

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R20

Minimum active contact spacing 6 L

(on different active regions)

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Interconnect Layout Example

Basic Gate Design

Both the power supply and ground are routed using the Metal layer
n+ and p+ regions are denoted using the same fill pattern. The only
difference is the n-well
Contacts are needed from Metal to n+ or p+
The CMOS NOT Gate
Contact Cut

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CMOS Process Layers

Intra-Layer Design Rules

Vias and Contacts

2
4

Via
1

Metalto
PolyContact

Metalto
1
ActiveContact

A CMOS Inverter
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A CMOS NAND Gate

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A CMOS NOR Gate

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HOW TO START THE CADENCE SERVER :

(I)

FOR CADENCE SERVER:

FOR STUDENTS : LOGIN

:root
: root (same for bits and bies)

Log in
Password

: cadence bits (for BIES PWD: cadence)

user123

PASSWORD :

#csh
#source cshrc
#cd C Licence_80455_001CC08782D6_11_13_2012.txt (for BIES)
cd C Licence_80455_BITS host server ID_11_13_2012.txt (for BITS)
#/etc/init.d/nfs
#/etc/init.d/nfs
#/etc/init.d/nfs restart
#/etc/init.d/nfs restart
#cd cadence_ms_labs_614
#virtuoso &
(II)
FOR CLIENT SYSTEM(STUDENTS):
right click and open the terminal and then root@localhost
then type and follow the procedure to open cadence files

window opens,

#mount -a
#csh
#cd cadence_db/
#source cshrc
#cd cadence_ms_labs_614
#virtuoso &
(IiI) IF CLIENT OPENS THE SYSTEM BEFORE TO SERVER THEN(STUDENTS):
#mount -a
#source /mnt/cadence/script
Then press Y to start cadence
#csh
#source cshrc
#cd cadence_ms_labs_614
#virtuoso &
WHEN YOU ENTER TO CADENCE THE FOLLOWING TWO WINDOWS WILL OPEN
WHEN YOU ENTER TO CADENCE THE FOLLOWING TWO WINDOWS WILL OPEN
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Window (1)

This is the main window where we use the tools from this only. So keep this open.

Window (2)

OUT OF THESE TWO WINDOWS CUT THE ABOVE WINDOW I.e. whats new in
6.1.3.500.

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(2).

CMOS INVERTER DESIGN, SIMULATION AND LAYOUT

(1). circuit design, pin and wire connections, setting input values, DC analysis,
Transient analysis, I/O
characteristics for CMOS INVERTER.
(1)
File
new
library
an existing technology
OK library

Bitsname
111 click on

click on

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attach to

(2)
Select gpdk180
window

OK on
click

again click on OK on previous small

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(3)
File
new
cell view-here another window opens, here select the
previous given file name in library which is bits 111 i. e, library
Now type the experiment name in the cell as cell

OK

press

Note: here a new window opens i.e., Virtuoso schematic editor. Now maximize this.
Here we have to design the circuit.

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DESIGN OF CMOS INVERTER :(A): DESIGN OF pMOS PULL-UP TRANSISTOR:

(4) in schematic editor window

create
instance
library
select gpdk180 in library
pmos in cell
select symbol in view and click on it
now
close
the library browser window
click on
Hide
, this is a new window opened called add instance.

select

Now keep the cursor on schematic editor window and click the mouse of left and
release the finger and then press ESC button on keyboard.

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(B): DESIGN OF nMOS PULL-DOWN TRANSISTOR:

(5)
create
instance
library
select gpdk180 in library
nmos in cell
select symbol in view and click on it
now
close
the library browser window
click on
Hide
, this is a new window opened called add instance.

select

Now keep the cursor on schematic editor window and click the mouse of left and
release the finger and then press ESC button on keyboard.

(C): CREATING PINS TO THE CMOS INVERTER:

(6) Create pins for Vdd, Vss, Vin and V

out

(a) creating pin of Vin to the both connected gates of pmos pull-up & nmos pulldown
Vin
create
pin
in the window add pin and write the pin name as
, the pin appears like
also chose the direction as
input in the
Hide
window and then click on
.

here the pin symbol comes along with mouse cursor, now place pin at the
appropriate position as the option chosen by you (whether Vin, V out , Vdd or Vss)

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(b) creating pin of Vout to the both connected drains pmos pull-

up & nmos pull-down

Vo
create
pin
in the window add pin and write the pin name as
, the pin appears like
also chose the direction as out in the
Hide
window and then click on
.

(c) creating pin of Vdd to the pmos pull-up source only

Vd pin name as
pin
in the window add pin and write the
, the pin appears like
also chose the direction as input t in the
Hide
window and then click on
.
create

(d) creating pin of Vss to the nmos pull-down source only

create

pin
in the window add pin and write the
Vs pin name as
, the pin appears like
also chose the direction as out in the window
Hide
and then click on
.

(D): CREATING WIRES TO INTERCONNECT THE COMPONENTS AND

THE PINS OF CMOS INVERTER:

(7) Connecting pmos, nmos, pins using wires
(a) create

narrow wire;

Here the wire symbol starts along with mouse cursor. Now just click on where and
what components you want to connect. First you just click the left mouse and
release the mouse button, now the wire follows the cursor on the screen.
(b) Connect both the gates and to the Vin pin
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(c) Connect both the drains and to the Vout pin

(d) Connect pmos source to Vdd pin.
(e) Connect nmos source to Vss pin.
(f) Connect pull-up pmos bulk (or substrate) to source.
(g) Connect pull-down nmos bulk (or substrate) to source.

(E): CHECK AND SAVE OR ANY ERRORS OF CMOS INVERTER:

(7) Now press the button check and save
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DC ANALYSES:
CREATION OF SYMBOL for DC analysis:
Create
name (inverter)

cell view
OK ok

from cell view

library(library name)

cell

Then another window opens for symbol generation options.

left pin [Vin ], right pin [Vout], bottom pin [Vss], top pin [Vdd] then
OK press
now symbol editor opens

now delete inner rectangular shape.

Now create

shape

line

Now create

shape

circle

Now press on check and save button

and close the window

Now go to virtuoso main editor we have to create new cell view to use inverter as in
library.
File
new
presss ok

cell view

library(name)

cell(inverter_test)

FLOW STEPS TO SET UP FOR DC ANALYSES:

a. In the Analyses section, select dc.
b. In the DC Analyses section, turn on Save DC Operating Point.
c. Turn on the Component Parameter.
d. Double click the Select Component, Which takes you to the schematic window.
e. Select input signal vpulse source in the test schematic window.
f. Select DC Voltage in the Select Component Parameter form and click OK.
f. In the analysis form type start and stop voltages as 0 to 1.8 respectively.
g. Check the enable button and then click Apply.

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Now press the button check and save

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Dept. of Electronics & Communication Engineering

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II : LAY OUT DESIGN

Launch

Layout XL

Connectivity

startup opens
generate

click OK

OKfile
new

all from OK
source

CREATING LAYOUT VIEW OF INVERTER

1. From the Inverter schematic window menu execute Launch Layout XL. A
Startup Option form
appears.
2. Select Create New option. This gives a New Cell View Form
3. Check the Cellname (Inverter), Viewname (layout).
4. Click OK from the New Cellview form.
LSW and a blank layout window appear along with schematic window.

ADDING COMPONENTS TO LAYOUT

1. Execute Connectivity Generate All from Source or click the icon in the
layout editor window, Generate Layout form appears.

2. Click OK which imports the schematic components in to the Layout window

automatically.

Re arrange the components with in PR-Boundary as shown in the next page.

To rotate a component, Select the component and execute Edit Properties. Now

3. select the degree of rotation from the property edit form.

4. To Move a component, Select the component and execute Edit -Move command.

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MAKING INTERCONNECTION
1. Execute Connectivity Nets Show/Hide selected Incomplete Nets or click
the icon in the Layout Menu.
2. Move the mouse pointer over the device and click LMB to get the connectivity
information, which shows the guide lines (or flight lines) for the inter
connections of
the components.
3. From the layout window execute Create Shape Path/ Create wire or Create
Shape Rectangle (for vdd and gnd bar) and select the appropriate Layers
from the
LSW window and Vias for making the inter connections

Creating Contacts/Vias
You will use the contacts or vias to make connections between two different
layers.
1. Execute Create Via or select command to place different Contacts, as given
in below table

ONNECTION

CONTACT TYPE

For Metal1- Poly Connection

Metal1-Poly

For Metal1-Psubstrate

Metal1-Psub

For Metal1- Nwell

Metal1-Nwell

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Saving the design

1. Save your design by selecting File Save or click to save the layout, and layout
should appear as below.

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PHYSICAL VERIFICATION
ASSURA DRC - RUNNING A DRC
1. Open the Inverter layout form the CIW or library manger if you have closed that.
Press shift f in the layout window to display all the levels.
2. Select Assura - Run DRC from layout window. The DRC form appears. The
Library and Cellname are
taken from the current design window, but rule file
may be missing.
Select the Technology as gpdk180. This automatically loads the rule file. Your DRC
form should appear like this
3. Click OK to start DRC.
4. A Progress form will appears. You can click on the watch log file to see the log
file.
5. When DRC finishes, a dialog box appears asking you if you want to view your
DRC results, and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
7. Click View Summary in the ELW to find the details of errors.
8. You can refer to rule file also for more information, correct all the DRC errors and
Re run the DRC.
9. If there are no errors in the layout then a dialog box appears with No DRC
errors found written in it, click on close to terminate the DRC run.

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Running RCX
1. From the layout window execute Assura Run RCX.
2. Change the following in the Assura parasitic extraction form. Select output type
under Setup tab of the form.
(3)ASSURA RCX - RUNNING RCX
1. From the layout window execute Assura Run RCX.
2. Change the following in the Assura parasitic extraction form. Select output type
under Setup tab of the form.

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4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter
Ground
Nets as gnd

5. Click OK in the Assura parasitic extraction form when done. The RCX progress
form appears, in the progress form click Watch log file to see the output log file.
5. When RCX completes, a dialog box appears, informs you that Assura RCX run
Completed successfully.
6. You can open the av_extracted view from the library manager and view the
parasitic.

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Dept. of Electronics & Communication Engineering

(3) CMOS NAND GATE:

CMOS NAND GATE SCHEMATIC ENTRY:

components for building the schematic of NAND GATE
Library name

Cell Name

Properties/Comments

gpdk180

Pmos

Model Name = pmos1,pmos2

gpdk180

Nmos

Model Name =nmos1,nmos2;

Type the following in the ADD pin form in the exact order leaving space between the
pin names.
Pin Names
Vin1, vin2
vout
vdd vss

Direction
Input
Output
Input

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CREATION OF THE SYMBOL OF NAND GATE:

TO BUILD NAND_TEST DESIGN CIRCUIT USING YOUR NAND GATE

Using the component list and Properties/Comments in the table, build the csamplifier_test schematic as shown below
Library

Cellview name

Properties/Comments

myDesignLib
analogLib

cmos_nand
vpulse

Symbol

analogLib

vdd,vss,gnd

name
v1=0, v2=1.8,td=0 tr=tf=1ns, ton=10n,
T=20n
vdd=1.8 ; vss= 1.8

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To set up and run simulations on the NAND gate design:

The simulation of NAND gate, ADE window and waveform should look like below.

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CREATING A LAYOUT VIEW OF NAND GATE:

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(4).

CMOS XOR GATE:

SCHEMATIC DESIGN OF XOR GATE:

components for building the XOR gate schematic:

components for building the schematic of NAND GATE
Library name

Cell Name

gpdk180

Pmos

gpdk180

Nmos

Properties/Comments
Model Name = pmos1,pmos2,
,pmos3,pmos4;
Model Name =nmos1,nmos2;
,nmos3,nmos4;

Type the following in the ADD pin form in the exact order leaving space between the
pin names.
Pin Names
Vin1, vin2
vout
Vdd, vss

Direction
Input
Output
Input
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TO CREATE A SYMBOL FOR XOR GATE:

TO BUILD XOR_TEST DESIGN CIRCUIT:

Using the component list and Properties/Comments in the table, build the csamplifier_test schematic as shown below
Library name

Cellview

Properties/Comments

name
myDesignLib
analogLib

cmos_XOR
vpulse

Symbol

v1=0, v2=1.8,td=0 tr=tf=1ns,

ton=10n, T=20n

analogLib

vdd,vss,gnd

vdd=1.8 ; vss= 1.8

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set up and run simulations on the XOR gate design:

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CREATING LAYOUT VIEW FOR XOR GATE:

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(5) .

FULL ADDER:
SCHEMATIC DESIGN OF FULL ADDER:

components for building the schematic of FULL ADDER:

Library name

Cell Name

gpdk180

Pmos

gpdk180

Nmos

Properties/Comments
Model Name = pmos1,pmos2,
,pmos3,pmos4;
Model Name =nmos1,nmos2;
,nmos3,nmos4;

Type the following in the ADD pin form in the exact order leaving space between the
pin names.
Pin Names
Vin1, vin2
vout
Vdd, vss

Direction
Input
Output
Input
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TO CREATE A SYMBOL FOR FULL ADDER:

TO BUILD FULL ADDER TEST CIRCUIT DESIGN USING YOUR FULL ADDER:
Using the component list and Properties/Comments in the table, build the csamplifier_test schematic as shown below
Library

Cellview name

Properties/Comments

myDesignLib

cmos_FULL

Symbol

analogLib

ADDER
vpulse

v1=0, v2=1.8,td=0 tr=tf=1ns, ton=10n,

name

T=20n
analogLib

vdd,vss,gnd

vdd=1.8 ; vss= 1.8

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To set up and run simulations on the FULL ADDER design:

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CREATING A LAYOUT VIEW OF FULL ADDER:

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(6)

LATCH:
SCHEMATIC DESIGN OF LATCH:

components for building the schematic of LATCH:

Library name

Cell Name

Properties/Comments

gpdk180

Pmos

Model Name = pmos1,pmos2 ,pmos3,pmos4.

gpdk180

Nmos

Model Name = nmos1,nmos2 ,nmos3,nmos4.

Type the following in the ADD pin form in the exact order leaving space between the pin names.
Pin Names
Vin1, vin2
vout
Vdd, vss

Direction
Input
Output
Input

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Dept. of Electronics & Communication Engineering

CREATE A SYMBOL FOR THE LATCH:

TO BUILD LATCH TEST CIRCUIT DESIGN USING YOUR LATCH:

Using the component list and Properties/Comments in the table, build the
latch_test
schematic as shown below
Library name

Cellview name

Properties/Comments

myDesignLib
analogLib

cmos_FULL ADDER
vpulse

Symbol

analogLib

vdd,vss,gnd

v1=0, v2=1.8,td=0 tr=tf=1ns,

ton=10n, T=20n
vdd=1.8 ; vss= 1.8

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TO SET UP AND RUN SIMULATIONS ON THE LATCH DESIGN:

the simulation of LATCH, ADE window and waveform should look like below.

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CREATING A LAYOUT VIEW OF LATCH:

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(7)

GREY TO BINARY CODE CONVERTER:

SCHEMATIC DESIGN OF GREY TO BINARY CONVERTER:

components for building the schematic of GREY TO BINARY CODE CONVERTER:

Library name

Cell Name

Properties/Comments

gpdk180

Pmos

Model Name = pmos1,pmos2 ,pmos3,pmos4.

gpdk180

Nmos

Model Name = nmos1,nmos2 ,nmos3,nmos4.

Type the following in the ADD pin form in the exact order leaving space between the
pin names.
Pin Names
Vin1, vin2
vout
Vdd, vss

Direction
Input
Output
Input

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Dept. of Electronics & Communication Engineering

Create a symbol for the GREY TO BINARY CODE CONVERTER:

Create a layout view for GREY TO BINARY CODE CONVERTER:

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(8)

SRAM
SCHEMATIC DESIGN OF SRAM:

components for building the schematic of SRAM:

Library name

Cell Name

Properties/Comments

gpdk180

Pmos

Model Name = pmos1,pmos2 ,pmos3,pmos4.

gpdk180

Nmos

Model Name = nmos1,nmos2 ,nmos3,nmos4.

Type the following in the ADD pin form in the exact order leaving space between the pin names.
Pin Names
Vin1, vin2
vout
Vdd, vss

Direction
Input
Output
Input

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TO CREATE A SYMBOL FOR THE SRAM:

CREATING A LAYOUT VIEW OF SRAM:

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