One-Hot State Machine
One-Hot State Machine
One-Hot State Machine
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Finite state machine (FSM) is one of the first topics taught in any digital
design course, yet coding one is not as easy as first meets the eye. There are
Moore and Mealy state machines, encoded and one-hot state encoding, one
or two or three always block coding styles. Recently I was reviewing a
coworkers RTL code and came across a SystemVerilog one-hot state machine
coding style that I was not familiar with. Needless to say, it became a mini
research topic resulting in this blog post.
When coding state machines in Verilog or SystemVerilog, there are a few
general guidelines that can apply to any state machine:
1. If coding in Verilog, use parameters to define state encodings instead
of define macro definition. Verilog define macros have global scope;
a macro defined in one module can easily be redefined by a macro
with the same name in a different module compiled later, leading to
macro redefinition warnings and unexpected bugs.
2. If coding in SystemVerilog, use enumerated types to define state
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3.
4.
5.
6.
encodings.
Always define a parameter or enumerated type value for each state so
you dont leave it to the synthesis tool to choose a value for you.
Otherwise it can make for a very difficult ECO when it comes time to
reverse engineer the gate level netlist.
Make curr_state and next_state declarations right after the parameter or
enumerated type assignments. This is simply clean coding style.
Code all sequential always block using nonblocking assignments (<=).
This helps guard against simulation race conditions.
Code all combinational always block using blocking assignments (=).
This helps guard against simulation race conditions.
typedef enum {
IDLE = 2'b00,
ACTIVE = 2'b01,
DONE = 2'b10,
XX = 'x
} state_t;
state_t curr_state, next_state;
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enum {
IDLE = 0,
READ = 1,
DLY= 2,
DONE = 3
} state, next;
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enum {
IDLE =
READ =
DLY=
DONE =
} state,
4'b0001,
4'b0010,
4'b0100,
4'b1000
next;
According to Cliff Cummings 2003 paper, this coding style yields poor
performance because the Design Compiler infers a full 4-bit comparison
against the state vector, in effect defeating the speed advantage of a one-hot
state machine. However, the experiments conducted in this paper were done
in 2003, and I suspect synthesis tools have become smarter since then.
State machines may look easy on paper, but are often not so easy in practice.
Given how frequently state machines appear in designs, it is important for
every RTL designer to develop a consistent and efficient style for coding
them. One-hot state machines are generally preferred in applications that
can trade-off area for a speed advantage. This article demonstrated how they
can be coded in Verilog and SystemVerilog using a unique and very efficient
reverse case statement coding style. It is a technique that should be in
every RTL designers arsenal.
What are your experiences with coding one-hot state machines? Do you have
another coding style or synthesis results to share? Leave a comment below!
References
Synthesizable Finite State Machine Design Techniques Using the New
SystemVerilog 3.0 Enhancements
About LatestPosts
Jason Yu
SoC Design Engineer
at Intel Corporation
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