Unit5 Verilog HDL

VLSI DESIGN
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Preface
The India Semiconductor Association (ISA), an Indian semiconductor industry organization, has briefed growth, trends and forecasts for the Indian semiconductor market in collaboration with a U.S. consulting company Frost & Sullivan. The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor Market Update." According to the report, total semiconductor consumption in India (total value of semiconductors used for devices marketed in India) was $2.69 billion (USD) in 2006. The $2.69 billion represents 1.09% of the global semiconductor market. Of the total semiconductor consumption in India, consumption by local Indian set manufacturers accounted for $1.26 billion. The overall Indian semiconductor consumption will grow at an average rate of 26.7% per year in 2006 through 2009. Based on the actual consumption in 2006, the overall Indian semiconductor consumption is forecast to be $5.49 billion in 2009. This represents 1.62% of the global semiconductor market in 2009. Semiconductor consumption by local Indian set manufacturers is predicted to increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion in 2009. This material is the result of the Verilog Course Teams practical experience both in Design/Verification and Training. Many of the examples illustrated throughout the material are real designs models. With Verilog Course Teams training experience has led to step by step presentation, which addresses common mistakes and hard-to-understand concepts in a way that eases learning. Verilog Course Team invites suggestion and feedbacks from both students and faculty community to improve the quality, content and presentation of the material.
VLSI DESIGN UNIT 5 VERILOG HDL

5 HISTORY OF VERILOG 5.1 BASIC CONCEPTS 5.1.1 Hardware Description Language 5.1.2 VERILOG Introduction 5.1.3 VERILOG Features 5.1.4 Design Flow 5.2 Design Hierarchies 5.2.1 Bottom up Design 5.2.2 Top-Down Design 5.2.3 Lexical Conventions 5.2.4 Whitespace 5.2.5 Comments 5.2.6 Identifiers and Keywords 5.2.7 Escaped Identifiers 5.2.8 Numbers in Verilog 5.2.8.1 Integer Numbers 5.2.8.2 Real Numbers 5.2.8.3 Signed and Unsigned Numbers 5.9 Strings 5.10 Data types 5.10.1 Data Types Value set 5.10.2 Nets 5.10.3 Vectors 5.10.4 Integer, Real and Time Register Data Types 5.10.5 Arrays 5.10.6 Memories 1 1 1 1 2 2 2 5 5 6 6 7 7 7 8 8 8 9 9 10 10 10 11 11 12 12 www.verilogcourseteam.com
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5.10.7 Parameters 5.10.8 Strings 5.3 MODULES 5.3.1 Instances 5.4 PORTS 5.4.1 Port Declaration 5.4.2 Port Connection Rules 5.4.3 Ports Connection to External Signals 5.5 MODELING CONCEPTS 5.5 GATE LEVEL MODELING 5.5.1 Gate Types 5.6 DATA FLOW AND BEHAVIORAL MODELING 5.6.a Continuous Assignment Statements 5.6.b Propagation Delay 5.6.1 Operators 5.6.1.1 Arithmetic Operators 5.6.1.2 Relational Operators 5.6.1.3 Bit-wise Operators 5.6.1.4 Logical Operators 5.6.1.5 Reduction Operators 5.6.1.6 Shift Operators 5.6.1.7 Concatenation Operator 5.6.1.8 Replication Operator 5.6.1.9 Conditional Operator 5.6.1.10 Equality Operators 5.6.1.11 Operator Precedence 5.6.2 Timing controls 5.6.2.1 Delay-based timing control 13 13 13 14 15 15 15 16 17 18 18 24 25 26 26 26 27 28 29 30 32 33 33 34 35 36 36 36 www.verilogcourseteam.com
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5.6.2.2 Regular delay control 5.6.2.3 Intra assignment delay control 5.6.2.4 Event based timing control 5.6.3 Level-Sensitive Timing Control 5.6.4 Procedural Blocks 5.6.5 Procedural Assignment Statements 5.6.6 Procedural Assignment Groups 5.6.7 Sequential Statement Groups 5.6.8 Parallel Statement Groups 5.6.9 Blocking and Nonblocking assignment 5.6.10 assign and deassign 5.6.11 force and release 5.6.12 Conditional Statements 5.6.12.1 The Conditional Statement if-else 5.6.12.2 The Case Statement 5.6.12.3 The casez and casex statement 5.6.13 Looping Statements 5.6.13.1 The forever statement 5.6.13.2 The repeat statement 5.6.13.3 The while loop statement 5.6.13.4 The for loop statement 5.7 TASK and FUCNTIONS EXAMPLES 2 to 4 Decoder Comparator D-latch D Flip Flop Half adder 37 38 39 41 41 42 43 44 44 45 46 46 47 47 48 49 51 51 51 52 53 53 56 56 56 58 58 59 www.verilogcourseteam.com
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Full adder Ripple Carry Adder 59 60
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VLSI DESIGN UNIT 5 5. HISTORY OF VERILOG
VERILOG HDL
Verilog was started in the year 1984 by Gateway Design Automation Inc as a proprietary hardware modeling language. It is rumored that the original language was designed by taking features from the most popular HDL language of the time, called HiLo, as well as from traditional computer languages such as C. At that time, Verilog was not standardized and the language modified itself in almost all the revisions that came out within 1984 to 1990. Verilog simulator first used in 1985 and extended substantially through 1987. The implementation of Verilog simulator sold by Gateway. The first major extension of Verilog is Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which is a very efficient method for doing gate-level simulation. Later 1990, Cadence Design System, whose primary product at that time included thin film process simulator, decided to acquire Gateway Automation System, along with other Gateway products., Cadence now become the owner of the Verilog language, and continued to market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the top-down design methodology, using Verilog. This was a powerful combination. In 1990, Cadence organized the Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog Hardware Description Language. This was the event which "opened" the language.
5.1 Overview of Digital Design with Verilog HDL

5.1.1 Hardware Description Language Two things distinguish an HDL from a linear language like C: Concurrency: The ability to do several things simultaneously i.e. different code-blocks can run concurrently. Timing: Ability to represent the passing of time and sequence events accordingly 5.1.2 VERILOG Introduction Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a language used to describe a digital system; one may describe a digital system at several levels. An HDL might describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i.e., the switch level. It might describe the logical gates and flip flops in a digital system, i.e., the gate level. An even higher level describes the registers and the transfers of vectors of information between registers. This is called the Register Transfer Level (RTL). Verilog supports all of these levels. www.verilogcourseteam.com
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VERILOG HDL
A powerful feature of the Verilog HDL is that you can use the same language for describing, testing and debugging your system.
5.1.3 VERILOG Features Strong Background: Supported by OVI, and standardized in 1995 as IEEE std 1364 Industrial support: Fast simulation and effective synthesis (85% were used in ASIC foundries by EE TIMES) Universal : Allows entire process in one design environment (including analysis and verification) Extensibility : Verilog PLI that allows for extension of Verilog capabilities
5.1.4 Design Flow The typical design flow is shown in figure 5.1,
Figure 5.1 VLSI Design Flow
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Design Specification
VERILOG HDL
Specifications are written first-Requirement/needs about the project Describe the functionality overall architecture of the digital circuit to be designed. Specification: Word processor like Word, Kwriter, AbiWord and for drawing waveform use tools like wave former or test bencher or Word.
RTL Description Conversation of Specification in coding format using CAD Tools. Coding Styles: Gate Level Modeling Data Flow Modeling Behavioral Modeling RTL Coding Editor : Vim, Emacs, conTEXT, HDL TurboWriter
I0 I1 I2 I3 S0 S1 Figure 5.2 Black Box View of 4:1 MUX Functional Verification &Testing Comparing the coding with the specifications. Testing the Process of coding with corresponding inputs and outputs. If testing fails once again check the RTL Description. Simulation: Modelsim, VCS, Verilog-XL,Xilinx. Out
Figure 5.3 Simulation Output View of 4:1 MUX Using Modelsim Wave form Viewer
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VERILOG HDL
Logic Synthesis Conversation of RTL description into Gate level -Net list form. Description of the circuit in terms of gates and connections. Synthesis: Design Compiler, FPGA Compiler, Synplify Pro, Leonardo Spectrum, Altera and Xilinx.
Figure 5.4 Synthesis of 4:1 MUX Using Leonardo Spectrum Logical Verification and Testing Functional Checking of HDL coding by simulation and synthesis. If fails check the RTL description. Floor Planning Automatic Place and Route Creation of Layout with the corresponding gate level Net list. Arrange the blocks of the net list on the chip Place & Route: For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic Physical Layout Physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. Layout Verification Verifying the physical layout structure. If any modification once again check Floor Planning Automatic Place and Route and RTL Description. Implementation Final stage in the design process. Implementation of coding and RTL in the form of IC.
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VERILOG HDL
Figure 5.5 Layout view of a system
5.2 DESIGN HIERARCHIES

5.2.1 Bottom up Design The Traditional method of electronic design is bottom up. Each design is performed at the gate level using the standard gates .With increasing complexity of new designs this approach is nearly impossible to maintain. It gives way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity
Figure 5.6 Bottom Up Design 5.2.2 Top-Down Design A real top down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are mix of both the methods. Implementing some key elements of both design styles
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VERILOG HDL
Figure 5.7 Top-Down Design 5.2.3 Lexical Conventions The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords. Verilog HDL is a case-sensitive language. All keywords are in lower case. 5.2.4 Whitespace White space can contain the characters for blanks, tabs, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings. White space characters are: Blank spaces (\b) Tabs(\t) Carriage returns(\r) New-line (\n) Form-feeds (\a) Example
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5.2.5 Comments
VERILOG HDL
Comments can be inserted in the code for readability and documentation. There are two forms to introduce comments. Single line comments begin with the token // and end with a carriage return Multi line comments begin with the token /* and end with the token */ Example
5.2.6 Identifiers and Keywords Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description. Keywords are reserved to define the language constructs. Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ ) Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ ) Identifiers can be up to 1024 characters long. Keywords are in lowercase. Examples of legal identifiers data_input mu clk_input my$clk i386 Examples of keywords always begin end
5.2.7 Escaped Identifiers Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal). Escaped identifiers begin with the back slash ( \ ) Entire identifier is escaped by the back slash. Escaped identifier is terminated by white space (Characters such as
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VERILOG HDL
Commas, parentheses, and semicolons become part of the escaped identifier unless preceded by a white space) Terminate escaped identifiers with white space, otherwise characters that should follow the identifier are considered as part of it.
5.2.8 Numbers in Verilog Numbers in Verilog can be specified constant numbers in decimal, hexadecimal, octal, or binary format. Negative numbers are represented in 2's complement form. When used in a number, the question mark (?) character is the Verilog alternative for the z character. The underscore character (_) is legal anywhere in a number except as the first character, where it is ignored. 5.2.8.1 Integer Numbers Verilog HDL allows integer numbers can be specified as

Sized or unsized numbers (Unsized size is 32 bits) In a radix of binary, octal, decimal, or hexadecimal Radix and hex digits (a,b,c,d,e,f) are case insensitive Spaces are allowed between the size, radix and value
Integer numbers are represented as <size><base format> <number> <size> is wrriten only in decimal and specifies the number of bits in the number. Legal base formats are decimal (d or D), hexadecimal(h or H), binary (b or B) and octal (o or O). the number is specified as consecutive digits from 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular base. Uppercase letters are legal for number specification. 4b1111 this is a 4-bit binary number 12habc this is a 12-bit hexadecimal number 16d255 this is a 16-bit decimal number 8o44-this is 8 bit octal number 5.2.8.2 Real Numbers

Verilog supports real constants and variables Verilog converts real numbers to integers by rounding Real Numbers can not contain 'Z' and 'X' Real numbers may be specified in either decimal or scientific notation < value >.< value > < mantissa >E< exponent > Real numbers are rounded off to the nearest integer when assigning to an integer.
Example Real Number 1.2 0.6 3.5E6 Decimal notation 1.2 0.6 3,500000.0 www.verilogcourseteam.com
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5.2.8.3 Signed and Unsigned Numbers
VERILOG HDL
Verilog supports both types of numbers, but with certain restrictions. Like in C language Verilog don't have int and unint types to say if a number is signed integer or unsigned integer. Any number that does not have negative sign prefix is a positive number. Or indirect way would be "Unsigned". Negative numbers can be specified by putting a minus sign before the size for a constant number, thus they become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic. Example Number 32'hDEAD_BEEF -14'h1234 Example
module signed_number; reg [31:0] a; initial begin a = 14'h1234; $display ("Current Value of a = h", a); a = -14'h1234; $display ("Current Value of a = h", a); a = 32'hDEAD_BEEF; $display ("Current Value of a = h", a); a = -32'hDEAD_BEEF; $display ("Current Value of a = h", a); #10 $finish; end endmodule
Description Unsigned or signed positive number Signed negative number
5.9 Strings A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines, Strings are treated as a sequence of one-byte ASCII values. Examples
hello Verilog world a/b aa+a
5.10 Data types Every signal has a data type associated with it: Explicitly declared with a declaration in your Verilog code. www.verilogcourseteam.com
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VERILOG HDL
Implicitly declared with no declaration when used to connect structural building blocks in your code. Implicit declaration is always a net type "wire" and is one bit wide.
5.10.1 Data Types Value set Verilog supports four values and eight strengths to model the functionality of real hardware. The four levels are listed in table Value level 0 1 x z 5.10.2 Nets Nets represent connections between hardware elements. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to. Types of Nets Each net type has a functionality that is used to model different types of hardware (such as PMOS, NMOS, CMOS, etc) Example Net Data Type wire, tri wor, trior wand, triand tri0, tri1 supply0, supply1 Trireg Register Data Types

Condition in hardware circuits logic zero, false condition logic one, true condition unknown value High impedance, floating state
Functionality Interconnecting wire - no special resolution function Wired outputs OR together (models ECL) Wired outputs AND together (models opencollector) Net pulls-down or pulls-up when not driven Net has a constant logic 0 or logic 1 (supply strength) Retains last value, when driven by z (tristate).
Registers store the last value assigned to them until another assignment statement changes their value. Registers represent data storage constructs. You can create regs arrays called memories. Register data types are used as variables in procedural blocks. A register data type is required if a signal is assigned a value within a procedural block Procedural blocks begin with keyword initial and always.
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Example Data Types reg integer time real 5.10.3 Vectors Functionality Unsigned variable
VERILOG HDL
Signed variable - 32 bits Unsigned integer - 64 bits Double precision floating point variable
Nets or reg data types can be declared as vectors. If bit width is not specified, the default is scalar (1-bit).Vectors can be declared at [high#: low#] or [low#: high#], but the left number in the squared brackets is always the most significant bit of the vector. Examples
wire a // scalar net variable default wire [7:0]bus; // 8-bit bus wire [31:0] busA, busB, busC; // 3 buses of 32-bit width reg clock // scalar register busA[7]; // bit #7 of vector busA bus [2:0] // three least significant bits of vector bus
5.10.4 Integer, Real and Time Register Data Types Integer An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer. Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation specific but is at least 32 bits. Registers declared as data type reg store values as unsigned quantities, whereas integers store value as signed quantities. Example
integer counter; // general purpose variable used as a counter initial counter=-1; // A negative one is stored in the counter
Real Real number constants and real register data types are declared with the keyword real. They can be specified in decimal notation (e.g., 5.12) or in scientific notation (e.g., 5e6, which is 5x10^6). Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer.
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Example
real delta; // define a real variable called delta initial begin delta=4e10; // delta is assigned in scientific notation delta=2.13 ; // delta is assigned a value 2.13 end integer i; // define an integer i
VERILOG HDL
Time Verilog simulation is done with respect to simulation time. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation specific but is at least 64 bits. The system function $time is invoked to get the current simulation time. Example
time save_sim_time; // define a time variable save_sim_time initial save_sim_time=$time; // save the current simulation time
5.10.5 Arrays Arrays are allowed in Verilog for reg, integer, time and vector register data types. Arrays are not allowed for real variables. Arrays are accessed by <array_name>[<subscript>]. Multidimensional arrays not permitted in Verilog. Example
integer count[7:0]; // an array of 8 count variables reg bool[31:0]; // array of 32 one-bit Boolean register variables integer matrix[4:0][4:0]; // illegal declaration Multidimensional array
5.10.6 Memories In digital simulation, one often needs to model register files, RAMs and ROMs. Memories are modeled in Verilog simply as an array of registers. Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register. A particular word in memory is obtained by using the address as a memory array subscript. Example
reg mem1bit[0:1023]; // memory mem1bit with 1K 1-bit words reg [7:0]membyte[0:1023]; // memory membyte with 1K 8-bit words
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5.10.7 Parameters
VERILOG HDL
Verilog allows constants to be defined in a module by the keyword parameter. Parameters cannot be used as variables. Parameter values for each module instance can be overridden individually at compile time. This allows the module instances to be customized. Example
parameter port_id = 5; //Defines a constant port_id parameter cache_line_width= 256; // Constant defines width of cache line
5.10.8 Strings Strings can be stored in reg. The width of the register variables must be large enough to hold the string. Each character in the string takes up 8 bits (1 byte). If the width of the register is greater than the size of the string, Verilog fills bits to left of the string with zeros. If the register width is smaller than the string width, Verilog truncates the leftmost bits of the string. It is always safe to declare that is slightly wider than necessary. Example
reg [8*81:1] string_value; // declare a variable that is 18 bytes wide initial string_value=hello Verilog course team; // string can be stored in variable
5.3 MODULES A module in Verilog consists of distinct parts as shown in figure 5.8. A module definition always begins with the keyword module. The module name, port list, port declarations, and optional parameters must come first in a module definition. Port list and port declarations are present only if the module has any ports to interact with the external environment. The five components within a module are; variable declarations, dataflow statements instantiation of lower modules behavioral blocks tasks or functions.
These components can be in any order and at any place in the module definition. The endmodule statement must always come last in a module definition. All components except module, module name, and endmodule are optional and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined in a single file. The modules can be defined in any order in the file.
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VERILOG HDL
Figure 5.8 Components of Verilog Module Example Module Structure : module <module name>(<module_terminals_list>); .. <module internals> . Endmodule 5.3.1 Instances A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. In Example below, the top-level block creates four instances from the Tflip-flop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate. Each Instance must be given a unique name. Example
// Define the top-level module called ripple carry // counter. It instants 4 T-filpflops. // four instances of the module T_FF are created. Each has a unique name. // each instance is passed a set of signals module ripple_carry_counter(q,clk,reset); output [3:0]q; input clk,reset; T_FF tff0(q[0],clk,reset); T_FF tff1(q[1],q[0],reset); T_FF tff2(q[2],q[1],reset); T_FF tff3(q[3],q[2],reset); endmodule
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// define the module T_FF. it instantiates a D-filpflop. module T_FF(q,clk,reset); output q; input clk,reset; wire d; D_FF dff0(q,d,clk,reset); not n1(d,q); endmodule
VERILOG HDL
5.4 PORTS
Ports provide the interface by which a module can communicate with its environment. For example, the input/output pins of an IC chip are its ports. The environment can interact with the module only through its ports. The internals of the module are not visible to the environment. This provides a very powerful flexibility to the designer. The internals of the module can be changed without affecting the environment as long as the interface is not modified. Ports are also referred to as terminals. 5.4.1 Port Declaration All ports in the list of ports must be declared in the module. Ports can be declared as follows Verilog Keyword input output inout Type of Port Input port Output port Bidirectional port
Each port in the port list is defined as input, output, or inout, based on the direction of the port signal. 5.4.2 Port Connection Rules One can visualize a port as consisting of two units, one unit that is internal to the module another that is external to the module. The internal and external units are connected. There are rules governing port connections when modules are instantiated within other modules. The Verilog simulator complains if any port connection rules are violated. These rules are summarized in figure 1.9.
Figure 5.9 Port connection Rules Inputs: Internally must be of net data type (e.g. wire) Externally the inputs may be connected to a reg or net data type www.verilogcourseteam.com
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Outputs: Inouts: Internally may be of net or reg data type Externally must be connected to a net data type
VERILOG HDL
Internally must be of net data type (tri recommended) Externally must be connected to a net data type (tri recommended)
5.4.3 Ports Connection to External Signals There are two methods of making connections between signals specified in the module instantiation and ports in a module definition. The two methods cannot be mixed. Port by order list Port by name
Port by order list Connecting port by order list is the most intuitive method for most beginners. The signals to be connected must appear in the module instantiation in the same order as the ports in the ports list in the module definition. Syntax for instantiation with port order list:
module_name instance_name (signal, signal...);
From the below example, notice that the external signals a, b, out appear in exactly the same order as the ports a, b, out in the module defined in adder below. Example
Port by name For larger designs where the module have ,say 5o ports , remembering the order of the ports in the module definition is impractical and error prone. Verilog provided the capability to connect external signals to ports by the port names, rather than by position. Syntax for instantiation with port name:
module_name instance_name (.port_name(signal), .port_name (signal) );
From the below example, note that the port connections in any order as long as the port name in the module definition correctly matches the external signal.
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Example
VERILOG HDL
Another advantage of connecting ports by name is that as long as the port name is not changed, the order of ports in the port list of a module can be rearranged without changing the port connections in the module instantiations.
5.5 MODELING CONCEPTS

Verilog is both a behavioral and a structural language. Internals of each module to be defined at four levels of abstraction, depending on the needs of the design. The module behaves identically with the external environment irrespective of the level of abstraction at which the module is described. The internals of the module hidden from the environment. Thus, the level of abstraction to describe a module can be changed without any change in the environment. The levels are defined below Behavioral or algorithmic level This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming Dataflow level At this level the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design. Gate level The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gate-level logic diagram. Switch level This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switch-level implementation details. Verilog allows the designer to mix and match all four levels of abstractions in a design. In the digital design community, the term register transfer level (RTL) is frequently used for a Verilog description that uses a combination of behavioral and dataflow constructs and is acceptable to logic synthesis tools.
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VERILOG HDL
If a design contains four modules, Verilog allows each of the modules to be written at a different level of abstraction. As the design matures, most modules are replaced with gate-level implementations.
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Normally, the higher the level of abstraction, the more flexible and technology Independent the design. As one goes lower toward switch-level design, the design becomes technology dependent and inflexible. A small modification can cause a significant number of changes in the design. Comparing the analogy with C programming and assembly language programming. It is easier to program in higherlevel language such as C. The program can be easily ported to any machine. However, if the design at the assembly level, the program is specific for that machine and cannot be easily ported to another machine.
GATE LEVEL MODELING

Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in design (RTL Coding), but are used in post synthesis world for modeling the ASIC/FPGA cells; these cells are then used for gate level simulation. Also the output netlist format from the synthesis tool, which is imported into the place and route tool, is also in Verilog gate level primitives. 5.5.1 Gate Types A logic circuit can be designed by use of logic gates. Verilog supports logic gates as predefined primitives. Theses primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition. All circuit can be designed by using basic gates. There are two classes of basic gates: and/or gates and buf/not gates. And/Or Gates and/or gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs. The output of a gate is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog are shown below.
and or nand nor xor xnor
The corresponding logic symbols for these gates are shown in figure 1.18. We consider gates with two inputs. These gates are instantiated to build logic circuits in Verilog. Examples of gate Instantiations are shown below. In the below example, for all instances, OUT is connected to the output out, and IN1 and IN2 are connected to the two inputs i1 and i2 of the gate primitives.
Figure 5.18 Gates symbol
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The instance name does not need to be specified for primitives. More than two inputs can be specified in gate instantiation Gates with more two inputs are instantiated by simply adding more ports in the gate instantiation. Verilog automatically instantiates the appropriate gate. Example Gate Instantiation of And/Or gates
The truth tables for these gates are given below, assuming two inputs. Outputs of gates with more than two inputs are computed by applying the truth table iteratively. Buf/Bufif1/Bufif0/Not/Notfif1/Notfif0 Gates Buf/not gates have one scalar input and one or more scalar output. The lasts terminal in the port list is connected to the input. Other terminals are connected the outputs. Bufif1, Bufif0, Notif1, Notifo gates propagate only if their control signal is asserted. Such a situation is applicable when multiple drivers drive the signal. These drivers are designed to drive the signal on mutually exclusive control. They propagate z if their control signal is deasserted.
buf bufif1 bufif1 not notfif1 bufif0
__________________________________________ Figure 5.19 Gates But, Not, Bufif1, Bufif0, Notif1, Notifo
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VERILOG HDL
Table 5.6Truth Table Example Gate Instantiation of Buf/Not gates
From the above example, notice that theses gates can have multiple outputs but exactly one inputs, which is the last terminal in the port list. The truth tables for these gates are shown below.
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VERILOG HDL
Examples AND Gate from NAND Gate
Figure 5.20 Structural model of AND gate from two NANDS

module and_from_nand(); reg X, Y; wire F, W; // Two instantiations of the module NAND nand U1(W,X, Y); nand U2(F, W, W); // Testbench Code initial begin $monitor ("X = %b Y = %b F = %b", X, Y, F); X = 0; Y = 0; #1 X = 1;
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#1 Y = 1; #1 X = 0; #1 $finish; end endmodule Simulation Output X=0Y=0F=0 X=1Y=0F=0 X=1Y=1F=1 X=0Y=1F=0
VERILOG HDL
D-Flip flop from NAND Gate
Figure 5.21 Structural model of D Flip-flop from NAND Gate

module dff_from_nand(); wire Q,Q_BAR; reg D,CLK; nand U1 (X,D,CLK) ; nand U2 (Y,X,CLK) ; nand U3 (Q,Q_BAR,X); nand U4 (Q_BAR,Q,Y); // Test bench initial begin $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR); CLK = 0; D = 0; #3 D = 1; #3 D = 0; #3 $finish; end always #2 CLK = ~CLK; endmodule Simulation Output CLK = 0 D = 0 Q = x Q_BAR = x CLK = 1 D = 0 Q = 0 Q_BAR = 1 CLK = 1 D = 1 Q = 1 Q_BAR = 0 CLK = 0 D = 1 Q = 1 Q_BAR = 0
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VLSI DESIGN
CLK = 1 D = 0 Q = 0 Q_BAR = 1 CLK = 0 D = 0 Q = 0 Q_BAR = 1
VERILOG HDL
Multiplex from Primitives
Figure 5.22 Structural model of Multiplex from Primitives

module mux_from_gates (); reg c0,c1,c2,c3,A,B; wire Y; //Invert the sel signals not (a_inv, A); not (b_inv, B); // 3-input AND gate and (y0,c0,a_inv,b_inv); and (y1,c1,a_inv,B); and (y2,c2,A,b_inv); and (y3,c3,A,B); // 4-input OR gate or (Y, y0,y1,y2,y3); // Test bench initial begin $monitor ( "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b", c0, c1, c2, c3, A, B, Y); c0 = 0; c1 = 0; c2 = 0; c3 = 0; A = 0; B = 0; #1 A = 1; #2 B = 1; #4 A = 0; #8 $finish; end
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always #1 c0 = ~c0; always #2 c1 = ~c1; always #3 c2 = ~c2; always #4 c3 = ~c3; endmodule Simulation Output c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 0 Y = 0 c0 = 1 c1 = 0 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0 c0 = 0 c1 = 1 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0 c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 1 B = 1 Y = 0 c0 = 0 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1 c0 = 1 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1 c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 1 B = 1 Y = 1 c0 = 1 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1 c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 1 Y = 0 c0 = 1 c1 = 0 c2 = 1 c3 = 0 A = 0 B = 1 Y = 0 c0 = 0 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1 c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1 c0 = 0 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0 c0 = 1 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0 c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1
VERILOG HDL
5.6 DATA FLOW AND BEHAVIORAL MODELING

For small circuits, the gate-level modeling approach works very well because the number of gates is limited and the designer can instantiate and connects every gate individually. Also, gate-level modeling is very intuitive to a designer with a basic knowledge of digital logic design. However, in complex designs the number of gates is very large. Thus, designers can design more effectively if they concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. Dataflow modeling has become a popular design approach as logic synthesis tools have become sophisticated. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. For maximum flexibility in the design process, designers typically use a Verilog description style that combines the concepts of gate-level, dataflow, and behavioral design. In the digital design community, the term RTL (Register Transfer Level) design is commonly used for a combination of dataflow modeling and behavioral modeling.
BEHAVIORAL MODELING
Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of abstraction. Design at this level resembles C programming more than it resembles
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VERILOG HDL
digital circuit design. Behavioral Verilog constructs are similar to C language constructs in many ways. Verilog is rich in behavioral constructs that provide the designer with a great amount of flexibility. 5.6.a Continuous Assignment Statements A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level abstraction. A continuous assignment statement starts with the keyword assign. They represent structural connections.

They are used for modeling Tri-State buffers. They can be used for modeling combinational logic. They are outside the procedural blocks (always and initial blocks). The continuous assign overrides any procedural assignments. The left-hand side of a continuous assignment must be net data type.
Syntax: assign (strength, strength) #(delay) net = expression; Example - One bit Adder design using continuous assignment statement
module adder_using_assign (); reg a, b; wire sum, carry; assign #5 {carry,sum} = a+b; initial begin $monitor (" A = %b B = %b CARRY = %b SUM = %b",a,b,carry,sum); #10 a = 0; b = 0; #10 a = 1; #10 b = 1; #10 a = 0; #10 b = 0; #10 $finish; end endmodule
Example - Tri-state buffer using continuous assignment statement

module tri_buf_using_assign(); reg data_in, enable; wire pad; assign pad = (enable) ? data_in : 1'bz; initial begin $monitor ("TIME = %g ENABLE = %b DATA : %b PAD %b", $time, enable, data_in, pad); #1 enable = 0; #1 data_in = 1; #1 enable = 1; #1 data_in = 0; #1 enable = 0;
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#1 $finish; end endmodule
VERILOG HDL
5.6.b Propagation Delay Continuous Assignments may have a delay specified; only one delay for all transitions may be specified. A minimum: typical: maximum delay range may be specified. Example - Tri-state buffer
module tri_buf_using_assign_delays(); reg data_in, enable; wire pad; assign #(1:2:3) pad = (enable) ? data_in : 1'bz; initial begin $monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad); #10 enable = 0; #10 data_in = 1; #10 enable = 1; #10 data_in = 0; #10 enable = 0; #10 $finish; end endmodule
5.6.1 Operators Verilog provided many different operators types. Operators can be, Arithmetic Operators Relational Operators Bit-wise Operators Logical Operators Reduction Operators Shift Operators Concatenation Operator Replication Operator Conditional Operator Equality Operator 5.6.1.1 Arithmetic Operators These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y) operators. Binary: +, -, *, /, % (the modulus operator) Unary: +, - (This is used to specify the sign) Integer division truncates any fractional part The result of a modulus operation takes the sign of the first operand
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VERILOG HDL
If any operand bit value is the unknown value x, then the entire result value is x Register data types are used as unsigned values (Negative numbers are stored in two's complement form) Example
module arithmetic_operators(); initial begin $display (" 5 + 10 = %d", 5 + 10); $display (" 5 - 10 = %d", 5 - 10); $display (" 10 - 5 = %d", 10 - 5); $display (" 10 * 5 = %d", 10 * 5); $display (" 10 / 5 = %d", 10 / 5); $display (" 10 / -5 = %d", 10 / -5); $display (" 10 %s 3 = %d","%", 10 % 3); $display (" +5 = %d", +5); $display (" -5 = %d", -5); #10 $finish; end endmodule Simulation Output 5 + 10 = 15 5 - 10 = -5 10 - 5 = 5 10 * 5 = 50 10 / 5 = 2 10 / -5 = -2 10 % 3 = 1 +5 = 5 -5 = -5
5.6.1.2 Relational Operators Relational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators. Wire and reg variables are positive Thus (3b001) = = 3b111 and (-3d001)>3d1 10, however for integers -1< 6 Operator a<b a>b a <= b a >= b

Description a less than b a greater than b a less than or equal to b
a greater than or equal to b The result is a scalar value (example a < b) 0 if the relation is false (a is bigger than b) 1 if the relation is true ( a is smaller than b) x if any of the operands has unknown x bits (if a or b contains X) www.verilogcourseteam.com
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Verilog Course Team

VLSI DESIGN
Example
module relational_operators(); initial begin $display (" 5 <= 10 = %b", (5 <= 10)); $display (" 5 >= 10 = %b", (5 >= 10)); $display (" 1'bx <= 10 = %b", (1'bx <= 10)); $display (" 1'bz <= 10 = %b", (1'bz <= 10)); #10 $finish; end endmodule Simulation Output 5 <= 10 = 1 5 >= 10 = 0 1'bx <= 10 = x 1'bz <= 10 = x
VERILOG HDL
Note: If any operand is x or z, then the result of that test is treated as false (0)
5.6.1.3 Bit-wise Operators Bitwise operators perform a bit wise operation on two operands. This take each bit in one operand and perform the operation with the corresponding bit in the other operand. If one operand is shorter than the other, it will be extended on the left side with zeroes to match the length of the longer operand. Operator ~ & | ^ ^~ or ~^

Description negation and inclusive or exclusive or exclusive nor (equivalence)
Computations include unknown bits, in the following way: -> ~x = x -> 0&x = 0 -> 1&x = x&x = x -> 1|x = 1 -> 0|x = x|x = x -> 0^x = 1^x = x^x = x -> 0^~x = 1^~x = x^~x = x When operands are of unequal bit length, the shorter operand is zero-filled in the most significant bit positions. Example
module bitwise_operators();
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initial begin // Bit Wise Negation $display (" ~4'b0001 = %b", (~4'b0001)); $display (" ~4'bx001 = %b", (~4'bx001)); $display (" ~4'bz001 = %b", (~4'bz001)); // Bit Wise AND $display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001)); $display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001)); $display (" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001)); // Bit Wise OR $display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001)); $display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001)); $display (" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001)); // Bit Wise XOR $display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001)); $display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001)); $display (" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001)); // Bit Wise XNOR $display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001)); $display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001)); $display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001)); #10 $finish; end endmodule Simulation Output ~4'b0001 = 1110 ~4'bx001 = x110 ~4'bz001 = x110 4'b0001 & 4'b1001 = 0001 4'b1001 & 4'bx001 = x001 4'b1001 & 4'bz001 = x001 4'b0001 | 4'b1001 = 1001 4'b0001 | 4'bx001 = x001 4'b0001 | 4'bz001 = x001 4'b0001 ^ 4'b1001 = 1000 4'b0001 ^ 4'bx001 = x000 4'b0001 ^ 4'bz001 = z000 4'b0001 ~^ 4'b1001 = 0111 4'b0001 ~^ 4'bx001 = x111 4'b0001 ~^ 4'bz001 = x111
VERILOG HDL
5.6.1.4 Logical Operators Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They can work on expressions, integers or groups of bits, and treat all values that are nonzero as 1. Logical operators are typically used in conditional (if ... else) statements since they work with expressions.
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Operator ! && ||

VERILOG HDL
Description logic negation logical and logical or
Expressions connected by && and || are evaluated from left to right Evaluation stops as soon as the result is known The result is a scalar value: -> 0 if the relation is false -> 1 if the relation is true -> x if any of the operands has x (unknown) bits
Example
module logical_operators(); initial begin // Logical AND $display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1)); $display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0)); $display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx)); // Logical OR $display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0)); $display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0)); $display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx)); // Logical Negation $display ("! 1'b1 = %b", (! 1'b1)); $display ("! 1'b0 = %b", (! 1'b0)); #10 $finish; end endmodule Simulation Output 1'b1 && 1'b1 = 1 1'b1 && 1'b0 = 0 1'b1 && 1'bx = x 1'b1 || 1'b0 = 1 1'b0 || 1'b0 = 0 1'b0 || 1'bx = x ! 1'b1 =0 ! 1'b0 =1
5.6.1.5 Reduction Operators Reduction operators operate on all the bits of an operand vector and return a singlebit value. These are the unary (one argument) form of the bit-wise operators.
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Operator & ~& | ~| ^ ^~ or ~^

VERILOG HDL
Description and nand or nor xor xnor
Reduction operators are unary. They perform a bit-wise operation on a single operand to produce a single bit result. Reduction unary NAND and NOR operators operate as AND and OR respectively, but with their outputs negated. -> Unknown bits are treated as described before
Example
module reduction_operators(); initial begin // Bit Wise AND reduction $display (" & 4'b1001 = %b", (& 4'b1001)); $display (" & 4'bx111 = %b", (& 4'bx111)); $display (" & 4'bz111 = %b", (& 4'bz111)); // Bit Wise NAND reduction $display (" ~& 4'b1001 = %b", (~& 4'b1001)); $display (" ~& 4'bx001 = %b", (~& 4'bx001)); $display (" ~& 4'bz001 = %b", (~& 4'bz001)); // Bit Wise OR reduction $display (" | 4'b1001 = %b", (| 4'b1001)); $display (" | 4'bx000 = %b", (| 4'bx000)); $display (" | 4'bz000 = %b", (| 4'bz000)); // Bit Wise OR reduction $display (" ~| 4'b1001 = %b", (~| 4'b1001)); $display (" ~| 4'bx001 = %b", (~| 4'bx001)); $display (" ~| 4'bz001 = %b", (~| 4'bz001)); // Bit Wise XOR reduction $display (" ^ 4'b1001 = %b", (^ 4'b1001)); $display (" ^ 4'bx001 = %b", (^ 4'bx001)); $display (" ^ 4'bz001 = %b", (^ 4'bz001)); // Bit Wise XNOR $display (" ~^ 4'b1001 = %b", (~^ 4'b1001)); $display (" ~^ 4'bx001 = %b", (~^ 4'bx001)); $display (" ~^ 4'bz001 = %b", (~^ 4'bz001)); #10 $finish; end endmodule
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Simulation Output & 4'b1001 = 0 & 4'bx111 = x & 4'bz111 = x ~& 4'b1001 = 1 ~& 4'bx001 = 1 ~& 4'bz001 = 1 | 4'b1001 = 1 | 4'bx000 = x | 4'bz000 = x ~| 4'b1001 = 0 ~| 4'bx001 = 0 ~| 4'bz001 = 0 ^ 4'b1001 = 0 ^ 4'bx001 = x ^ 4'bz001 = x ~^ 4'b1001 = 1 ~^ 4'bx001 = x ~^ 4'bz001 = x
VERILOG HDL
5.6.1.6 Shift Operators Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension). Operator Description << left shift >> right shift

The left operand is shifted by the number of bit positions given by the right operand. The vacated bit positions are filled with zeroes
Example
module shift_operators(); initial begin // Left Shift $display (" 4'b1001 << 1 = %b", (4'b1001 << 1)); $display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1)); $display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1)); // Right Shift $display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1)); $display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1)); $display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1)); #10 $finish; end endmodule
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Simulation Output 4'b1001 << 1 = 0010 4'b10x1 << 1 = 0x10 4'b10z1 << 1 = 0z10 4'b1001 >> 1 = 0100 4'b10x1 >> 1 = 010x 4'b10z1 >> 1 = 010z
VERILOG HDL
5.6.1.7 Concatenation Operator The concatenation operator combines two or more operands to form a larger vector. Concatenations are expressed using the brace characters { and }, with commas separating the expressions within. ->Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24 bits Unsized constant numbers are not allowed in concatenations. Example
module concatenation_operator(); initial begin // concatenation $display (" {4'b1001,4'b10x1} = %b", {4'b1001,4'b10x1}); #10 $finish; end endmodule Simulation Output {4'b1001,4'b10x1} = 100110x1
5.6.1.8 Replication Operator Replication operator is used to replicate a group of bits n times. Say you have a 4 bit variable and you want to replicate it 4 times to get a 16 bit variable: then we can use the replication operator. Operator Description {n{m}} Replicate value m, n times

Repetition multipliers (must be constants) can be used: -> {3{a}} // this is equivalent to {a, a, a} Nested concatenations and replication operator are possible: -> {b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}
Example
module replication_operator(); initial begin
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VLSI DESIGN
// replication $display (" {4{4'b1001}} = %b", {4{4'b1001}}); // replication and concatenation $display (" {4{4'b1001,1'bz}} = %b", {4{4'b1001,1'bz}}); #10 $finish; end endmodule Simulation Output {4{4'b1001} = 1001100110011001 {4{4'b1001,1'bz} = 1001z1001z1001z1001z
VERILOG HDL
5.6.1.9 Conditional Operator Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX). ->cond_expr ? true_expr : false_expr The true_expr or the false_expr is evaluated and used as a result depending on what cond_expr evaluates to (true or false). Example
module conditional_operator(); wire out; reg enable,data; // Tri state buffer assign out = (enable) ? data : 1'bz; initial begin $display ("time\t enable data out"); $monitor ("%g\t %b %b %b",$time,enable,data,out); enable = 0; data = 0; #1 data = 1; #1 data = 0; #1 enable = 1; #1 data = 1; #1 data = 0; #1 enable = 0; #10 $finish; end endmodule Simulation Output time 0 1 2 enable data out 0 0 z 0 1 z 0 0 z
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VLSI DESIGN
3 4 5 6 1 1 1 0 0 0 1 1 0 0 0 z
VERILOG HDL
5.6.1.10 Equality Operators There are two types of Equality operators. Case Equality and Logical Equality. Operator a === b a !== b a == b a != b
Description a equal to b, including x and z (Case equality) a not equal to b, including x and z (Case inequality) a equal to b, result may be unknown (logical equality) a not equal to b, result may be unknown (logical equality)
Operands are compared bit by bit, with zero filling if the two operands do not have the same length Result is 0 (false) or 1 (true) For the == and != operators, the result is x, if either operand contains an x or a z For the === and !== operators, bits with x and z are included in the comparison and must match for the result to be true Note: The result is always 0 or 1 Example
module equality_operators(); initial begin // Case Equality $display (" 4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001)); $display (" 4'bx0x1 === 4'bx001 = %b", (4'bx0x1 === 4'bx001)); $display (" 4'bz0x1 === 4'bz0x1 = %b", (4'bz0x1 === 4'bz0x1)); $display (" 4'bz0x1 === 4'bz001 = %b", (4'bz0x1 === 4'bz001)); // Case Inequality $display (" 4'bx0x1 !== 4'bx001 = %b", (4'bx0x1 !== 4'bx001)); $display (" 4'bz0x1 !== 4'bz001 = %b", (4'bz0x1 !== 4'bz001)); // Logical Equality $display (" 5 == 10 = %b", (5 == 10)); $display (" 5 == 5 = %b", (5 == 5)); // Logical Inequality $display (" 5 != 5 = %b", (5 != 5)); $display (" 5 != 6 = %b", (5 != 6)); #10 $finish; end endmodule
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VLSI DESIGN
Simulation Output 4'bx001 === 4'bx001 = 1 4'bx0x1 === 4'bx001 = 0 4'bz0x1 === 4'bz0x1 = 1 4'bz0x1 === 4'bz001 = 0 4'bx0x1 !== 4'bx001 = 1 4'bz0x1 !== 4'bz001 = 1 5 == 10 =0 5 == 5 =1 5 != 5 =0 5 != 6 =1
VERILOG HDL
5.6.1.11 Operator Precedence Operator Unary, Multiply, Divide, Modulus Add, Subtract, Shift Relation, Equality Reduction Logic Conditional 5.6.2 Timing controls Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements, the simulation time does not advance. Timing controls provide a way to specify the simulation time at which procedural statements will execute. There are three methods of timing control: Delay based timing control Event based timing control Level-sensitive timing control 5.6.2.1 Delay-based timing control Delay-based timing control in an expression specifies the time duration between when the statement is encountered and when it is executed. Delays are specified by the symbol #. Syntax for the delay-based timing control statement is shown below
<delay> ::= #<NUMBER> ||= #<identifier> ||= #<mintypmax_expression> <,<mintypmax_expression>>*)
Symbols !, ~, *, /, % +, - , <<, >> <,>,<=,>=,==,!=,===,!== &, !&,^,^~,|,~| &&, || ?:
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VLSI DESIGN
VERILOG HDL
Delay-based timing control can be specified by a number, identifier, or a mintypmax_expression. There are three types of delay control for procedural assignments Regular delay control Intra-assignment delay control Zero delay control 5.6.2.2 Regular delay control Regular delay control is used when a non-zero delay is specified to the left of a procedural assignment. Usage of regular delay control is shown below example,
module clk_gen (); reg clk, reset; initial begin $monitor ("TIME = %g RESET = %b CLOCK = %b", $time, reset, clk); clk = 0; reset = 0; #2 reset = 1; #5 reset = 0; #10 $finish; end always #1 clk = !clk; endmodule Simulation Output TIME = 0 RESET = 0 CLOCK = 0 TIME = 1 RESET = 0 CLOCK = 1 TIME = 2 RESET = 1 CLOCK = 0 TIME = 3 RESET = 1 CLOCK = 1 TIME = 4 RESET = 1 CLOCK = 0 TIME = 5 RESET = 1 CLOCK = 1 TIME = 6 RESET = 1 CLOCK = 0 TIME = 7 RESET = 0 CLOCK = 1 TIME = 8 RESET = 0 CLOCK = 0 TIME = 9 RESET = 0 CLOCK = 1 TIME = 10 RESET = 0 CLOCK = 0 TIME = 11 RESET = 0 CLOCK = 1 TIME = 12 RESET = 0 CLOCK = 0 TIME = 13 RESET = 0 CLOCK = 1 TIME = 14 RESET = 0 CLOCK = 0 TIME = 15 RESET = 0 CLOCK = 1 TIME = 16 RESET = 0 CLOCK = 0
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VLSI DESIGN
5.6.2.3 Intra-assignment delay control
VERILOG HDL
Instead of specifying delay control to the left of the assignment, it is possible to assign a delay to the right of the assignment operator. Usage of intra-assignment delay control is shown in below example,
module intra_assign(); reg a, b; initial begin $monitor("TIME = %g A = %b B = %b",$time, a , b); a = 1; b = 0; a = #10 0; b = a; #20 $display("TIME = %g A = %b B = %b",$time, a , b); $finish; end endmodule Simulation output TIME = 0 A = 1 B = 0 TIME = 10 A = 0 B = 0 TIME = 30 A = 0 B = 0
Difference between the intra-assignment delay and regular delay Regular delays defer the execution of the entire assignment. Intra-assignment delays compute the right-hand-side expression at the current time and defer the assignment of the computed value to the left-hand-side variable. Intra-assignment delays are like using regular delays with a temporary variable to store the current value of a right-hand-side expression. Zero delay control Zero delay control is a method to ensure that a statement is executed last, after all other statements in that simulation in that simulation time are executed. This is used to eliminate race conditions. However, if there are multiple zero delay statements, the order between them is nondeterministic. Usage of zero delay control is shown in below example,
initial begin x=0; y=0; end initial begin #0 x=1; #0 y=1; End
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VERILOG HDL
Above four statements x=0,y=0,x=1,y=1 are to be executed at simulation time 0. However since x=1 and y=1 have #0, they will be executed last. Thus, at the end of time 0,x will have value 1 and y will have value 1. 5.6.2.4 Event based timing control An event is the change in the value on a register or a net. Events can be utilized to trigger execution of a statement or a block of statements. There are four types of event-based timing control Regular event control Named event control Event OR control Level-sensitive timing control
Regular event control The @ symbol is used to specify an event control. Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The keyword posedge is used for a negative transition as shown in below example,
module edge_wait_example(); reg enable, clk, trigger; always @ (posedge enable) begin trigger = 0; // Wait for 5 clock cycles repeat (5) begin @ (posedge clk) ; end trigger = 1; end //Test bench initial begin $monitor ("TIME : %g CLK : %b ENABLE : %b TRIGGER : %b", $time, clk,enable,trigger); clk = 0; enable = 0; #5 enable = 1; #1 enable = 0; #10 enable = 1; #1 enable = 0; #10 $finish; end always #1 clk = ~clk; Endmodule
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VLSI DESIGN
Simulation Output TIME : 0 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 1 CLK : 1 ENABLE : 0 TRIGGER : x TIME : 2 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 3 CLK : 1 ENABLE : 0 TRIGGER : x TIME : 4 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 5 CLK : 1 ENABLE : 1 TRIGGER : 0 TIME : 6 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 7 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 8 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 9 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 10 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 11 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 12 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 13 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 14 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 15 CLK : 1 ENABLE : 0 TRIGGER : 1 TIME : 16 CLK : 0 ENABLE : 1 TRIGGER : 0 TIME : 17 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 18 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 19 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 20 CLK : 0 ENABLE : 0 TRIGGER : 0
VERILOG HDL
Named event control Verilog provides the capability to declare an event and then trigger and recognize the occurrence of that event. The event does not hold any data. A named event is declared by the keyword event. An event is triggered by the symbol . The triggering of the event is recognized by the symbol @. Example
event received_data; always @(posedge clock) begin if (last_data_packet) received_data; end always @(received_data) data_buf={data_pkt[0],data_pkt[1]};
Event OR control Sometimes a transition on any one of multiple signals or events can trigger the execution of a statement or a block of statements. This is expressed as an OR of events or signals. The list of events or signals expressed as an OR is also known as a sensitivity list. The keyword or is used to specify multiple triggers as shown in below example,
always @(reset or clock or d) begin
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if(reset) q=1b0; else if (clock) q=d; end
VERILOG HDL
5.6. 3 Level-Sensitive Timing Control Verilog allows a level-sensitive timing control, that is, the ability to wait for a certain condition to be true before a statement or a block of statements is executed. The keyword wait is used for level-sensitive constructs. Example
always wait (count_enable) #20 count=count+1;
From the above example, the value of count_enable is monitored continuously. If count_enable is 0, the statement is not entered. If it is logical 1, the statement count=count+1 is executed after 20 time units. If count_enable stays at 1, count will be incremented every 20 time units. 5.6.4 Procedural Blocks Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also exist outside procedure blocks. We can see this in detail as we make progress. There are two types of procedural blocks in Verilog:

initial: initial blocks execute only once at time zero (start execution at time zero). always: always blocks loop to execute over and over again; in other words, as the name suggests, it executes always.
Example initial
module initial_example(); reg clk,reset,enable,data; initial begin clk = 0; reset = 0; enable = 0; data = 0; end endmodule
In the above example, the initial block execution and always block execution starts at time 0. Always block waits for the event, here positive edge of clock, whereas initial block just executed all the statements within begin and end statement, without waiting.
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Example always
module always_example(); reg clk,reset,enable,q_in,data; always @ (posedge clk) if (reset) begin data <= 0; end else if (enable) begin data <= q_in; end endmodule
VERILOG HDL
In an always block, when the trigger event occurs, the code inside begin and end is executed; then once again the always block waits for next event triggering. This process of waiting and executing on event is repeated till simulation stops. 5.6.5 Procedural Assignment Statements

Procedural assignment statements assign values to reg, integer, real, or time variables and cannot assign values to nets (wire data types) You can assign to a register (reg data type) the value of a net (wire), constant, another register, or a specific value.
Example - Bad procedural assignment

module initial_bad(); reg clk,reset; wire enable,data; initial begin clk = 0; reset = 0; enable = 0; data = 0; end endmodule
Example - Good procedural assignment

module initial_bad(); reg clk,reset; wire enable,data; initial begin clk = 0; reset = 0; enable = 0; data = 0; end endmodule
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VLSI DESIGN
5.6.6 Procedural Assignment Groups
VERILOG HDL
If a procedure block contains more than one statement, those statements must be enclosed within Sequential begin - end block Parallel fork - join block When using begin-end, we can give name to that group. This is called named blocks. Example - "begin-end"
module initial_begin_end(); reg clk,reset,enable,data; initial begin $monitor( "%g clk=%b reset=%b enable=%b data=%b", $time, clk, reset, enable, data); #1 clk = 0; #10 reset = 0; #5 enable = 0; #3 data = 0; #1 $finish; end endmodule
Begin : clk gets 0 after 1 time unit, reset gets 0 after 11 time units, enable after 16 time units, data after 19 units. All the statements are executed sequentially. Simulator Output
0 clk=x reset=x enable=x data=x 1 clk=0 reset=x enable=x data=x 11 clk=0 reset=0 enable=x data=x 16 clk=0 reset=0 enable=0 data=x 19 clk=0 reset=0 enable=0 data=0
Example - "fork-join"
module initial_fork_join(); reg clk,reset,enable,data; initial begin $monitor("%g clk=%b reset=%b enable=%b data=%b", $time, clk, reset, enable, data); fork #1 clk = 0; #10 reset = 0; #5 enable = 0; #3 data = 0; join #1 $display ("%g Terminating simulation", $time); $finish; end
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endmodule
VERILOG HDL
Fork: clk gets its value after 1 time unit, reset after 10 time units, enable after 5 time units, data after 3 time units. All the statements are executed in parallel. Simulator Output
0 clk=x reset=x enable=x data=x 1 clk=0 reset=x enable=x data=x 3 clk=0 reset=x enable=x data=0 5 clk=0 reset=x enable=0 data=0 10 clk=0 reset=0 enable=0 data=0 11 Terminating simulation
5.6.7 Sequential Statement Groups The begin - end keywords: Group several statements together. Cause the statements to be evaluated sequentially (one at a time) -> Any timing within the sequential groups is relative to the previous statement. -> Delays in the sequence accumulate (each delay is added to the previous delay) -> Block finishes after the last statement in the block. Example sequential
module sequential(); reg a; initial begin $monitor ("%g a = %b", $time, a); #10 a = 0; #11 a = 1; #12 a = 0; #13 a = 1; #14 $finish; end endmodule Simulator Output 0a=x 10 a = 0 21 a = 1 33 a = 0 46 a = 1
5.6.8 Parallel Statement Groups The fork - join keywords:

Group several statements together. Cause the statements to be evaluated in parallel (all at the same time). -> Timing within parallel group is absolute to the beginning of the group. www.verilogcourseteam.com
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VLSI DESIGN
VERILOG HDL
-> Block finishes after the last statement completes (Statement with highest delay, it can be the first statement in the block).
Example Parallel
module parallel(); reg a; initial fork $monitor ("%g a = %b", $time, a); #10 a = 0; #11 a = 1; #12 a = 0; #13 a = 1; #14 $finish; join endmodule Simulator Output 0a=x 10 a = 0 11 a = 1 12 a = 0 13 a = 1
5.6.9 Blocking and Nonblocking assignment Blocking assignments are executed in the order they are coded, hence they are sequential. Since they block the execution of next statement, till the current statement is executed, they are called blocking assignments. Assignment are made with "=" symbol. Example a = b; Nonblocking assignments are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called nonblocking statement. Assignments are made with "<=" symbol. Example a <= b; Note: Correct way to spell 'nonblocking' is 'nonblocking' and not 'non-blocking'. Example - blocking and nonblocking
module blocking_nonblocking(); reg a,b,c,d; // Blocking Assignment initial begin #10 a = 0; #11 a = 1; #12 a = 0; #13 a = 1; end initial begin
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VLSI DESIGN
#10 b <= 0; #11 b <= 1; #12 b <= 0; #13 b <= 1; end initial begin c = #10 0; c = #11 1; c = #12 0; c = #13 1; end initial begin d <= #10 0; d <= #11 1; d <= #12 0; d <= #13 1; end
VERILOG HDL
initial begin $monitor("TIME = %g A = %b B = %b C = %b D = %b",$time, a, b, c, d); #50 $finish; end endmodule Simulator Output TIME = 0 A = x B = x C = x D = x TIME = 10 A = 0 B = 0 C = 0 D = 0 TIME = 11 A = 0 B = 0 C = 0 D = 1 TIME = 12 A = 0 B = 0 C = 0 D = 0 TIME = 13 A = 0 B = 0 C = 0 D = 1 TIME = 21 A = 1 B = 1 C = 1 D = 1 TIME = 33 A = 0 B = 0 C = 0 D = 1 TIME = 46 A = 1 B = 1 C = 1 D = 1
5.6.10 assign and deassign The assign and deassign procedural assignment statements allow continuous assignments to be placed onto registers for controlled periods of time. The assign procedural statement overrides procedural assignments to a register. The deassign procedural statement ends a continuous assignment to a register. 5.6.11 force and release Another form of procedural continuous assignment is provided by the force and release procedural statements. These statements have a similar effect on the assign-deassign pair, but a force can be applied to nets as well as to registers. One can use force and release while doing gate level simulation to work around reset connectivity problems. Also can be used insert single and double bit errors on data read from memory.
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5.6.12 Conditional Statements 5.6.12.1 The Conditional Statement if-else
VERILOG HDL
if - else statement controls the execution of other statements. In programming language like c, if - else controls the flow of program. When more than one statement needs to be executed for an if condition, then we need to use begin and end as seen in earlier examples. Syntax : if if (condition) statements; Syntax : if-else if (condition) statements; else statements; Syntax : nested if-else-if if (condition) statements; else if (condition) statements; ................ ................ else statements; Example- simple if
module simple_if(); reg latch; wire enable,din; always @ (enable or din) if (enable) begin latch <= din; end endmodule
Example- if-else
module if_else(); reg dff; wire clk,din,reset; always @ (posedge clk) if (reset) begin dff <= 0; end else begin dff <= din; end endmodule
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VLSI DESIGN
Example- nested-if-else-if
module nested_if(); reg [3:0] counter; reg clk,reset,enable, up_en, down_en; always @ (posedge clk) // If reset is asserted if (reset == 1'b0) begin counter <= 4'b0000; // If counter is enable and up count is asserted end else if (enable == 1'b1 && up_en == 1'b1) begin counter <= counter + 1'b1; // If counter is enable and down count is asserted end else if (enable == 1'b1 && down_en == 1'b1) begin counter <= counter - 1'b1; // If counting is disabled end else begin counter <= counter; // Redundant code end
VERILOG HDL
5.6.12.2 The Case Statement The case statement compares an expression to a series of cases and executes the statement or statement group associated with the first matching case: case statement supports single or multiple statements. Group multiple statements using begin and end keywords. Syntax of a case statement is given below, case () < case1 > : < statement > < case2 > : < statement > ..... default : < statement > endcase Example- case
module mux (a,b,c,d,sel,y); input a, b, c, d; input [1:0] sel; output y; reg y; always @ (a or b or c or d or sel) case (sel) 0 : y = a; 1 : y = b; 2 : y = c; 3 : y = d;

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default : $display("Error in SEL"); endcase endmodule
VERILOG HDL
Example- case without default

module mux_without_default (a,b,c,d,sel,y); input a, b, c, d; input [1:0] sel; output y; reg y; always @ (a or b or c or d or sel) case (sel) 0 : y = a; 1 : y = b; 2 : y = c; 3 : y = d; 2'bxx,2'bx0,2'bx1,2'b0x,2'b1x, 2'bzz,2'bz0,2'bz1,2'b0z,2'b1z : $display("Error in SEL"); endcase endmodule
Example- case with x and z

module case_xz(enable); input enable; always @ (enable) case(enable) 1'bz : $display ("enable is floating"); 1'bx : $display ("enable is unknown"); default : $display ("enable is %b",enable); endcase endmodule
5.6.12.3 The casez and casex statement Special versions of the case statement allow the x ad z logic values to be used as "don't care": casez : Treats z as don't care. casex : Treats x and z as don't care.
Example- casez
module casez_example(); reg [3:0] opcode; reg [1:0] a,b,c;
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VLSI DESIGN
reg [1:0] out;
VERILOG HDL
always @ (opcode or a or b or c) casez(opcode) 4'b1zzx : begin // Don't care about lower 2:1 bit, bit 0 match with x out = a; $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode); end 4'b01?? : begin out = b; // bit 1:0 is don't care $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode); end 4'b001? : begin // bit 0 is don't care out = c; $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode); end default : begin $display("@%0dns default is selected, opcode %b",$time,opcode); end endcase Simulation Output - casez @0ns default is selected, opcode 0000 @2ns 4'b1zzx is selected, opcode 101x @4ns 4'b01?? is selected, opcode 0101 @6ns 4'b001? is selected, opcode 0010 @8ns default is selected, opcode 0000
Example- casex module casex_example(); reg [3:0] opcode; reg [1:0] a,b,c; reg [1:0] out; always @ (opcode or a or b or c) casex(opcode) 4'b1zzx : begin // Don't care 2:0 bits out = a; $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode); end 4'b01?? : begin // bit 1:0 is don't care
out = b; $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode); end 4'b001? : begin // bit 0 is don't care out = c; $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode); end default : begin
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VERILOG HDL
$display("@%0dns default is selected, opcode %b",$time,opcode); end endcase Simulation Output - casex @0ns default is selected, opcode 0000 @2ns 4'b1zzx is selected, opcode 101x @4ns 4'b01?? is selected, opcode 0101 @6ns 4'b001? is selected, opcode 0010 @8ns default is selected, opcode 0000
5.6.13 Looping Statements Looping statements appear inside procedural blocks only; Verilog has four looping statements like any other programming language.

forever repeat while for
5.6.13.1 The forever statement The keyword forever is used to express this loop. The loop does not contain any expression and executes continually, until the $finish task is encountered. Normally we use forever statements in initial blocks. Syntax: forever < statement > One should be very careful in using a forever statement: if no timing construct is present in the forever statement, simulation could hang. The code below is one such application, where a timing construct is included inside a forever statement. Example
module forever_example (); reg clk; initial begin #1 clk = 0; forever begin #5 clk = !clk; end end initial begin $monitor ("Time = %d clk = %b",$time, clk); #100 $finish; end endmodule
5.6.13.2 The repeat statement The keyword repeat is used for thi sloop. The repeat construct executes the loop a fixed number of times. A repeat construct cannot be used to loop on a general
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VLSI DESIGN
VERILOG HDL
logical expression. The repeat loop executes < statement > a fixed < number > of times. Syntax: repeat (< number >) < statement > Example- repeat
module repeat_example(); reg [3:0] opcode; reg [15:0] data; reg temp; always @ (opcode or data) begin if (opcode == 10) begin // Perform rotate repeat (8) begin #1 temp = data[15]; data = data << 1; data[0] = temp; end end end // Simple test code initial begin $display (" TEMP DATA"); $monitor (" %b %b ",temp, data); #1 data = 18'hF0; #1 opcode = 10; #10 opcode = 0; #1 $finish; end endmodule
5.6.13.3 The while loop statement The keyword while is used to specify this loop. The while loop executes as long as an < expression > evaluates as true. If the loop is entered when the whileexpression is false, the loop is not executed at all. This is the same as in any other programming language. Syntax: while (< expression >) < statement > Example- while
module while_example(); reg [5:0] loc; reg [7:0] data; always @ (data or loc) begin loc = 0; // If Data is 0, then loc is 32 (invalid value) if (data == 0) begin
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loc = 32; end else begin while (data[0] == 0) begin loc = loc + 1; data = data >> 1; end end $display ("DATA = %b LOCATION = %d",data,loc); end initial begin #1 data = 8'b11; #1 data = 8'b100; #1 data = 8'b1000; #1 data = 8'b1000_0000; #1 data = 8'b0; #1 $finish; end endmodule
VERILOG HDL
5.6.13.4 The for loop statement The for loop is the same as the for loop used in any other programming language. Executes an < initial assignment > once at the start of the loop. Executes the loop as long as an < expression > evaluates as true. Executes a < step assignment > at the end of each pass through the loop. Syntax: for (< initial assignment >; < expression >, < step assignment >) < statement > Note: Verilog does not have ++ operator as in the case of C language. Example For
module for_example(); integer i; reg [7:0] ram [0:255]; initial begin for (i = 0; i < 256; i = i + 1) begin #1 $display(" Address = %g Data = %h",i,ram[i]); ram[i] <= 0; // Initialize the RAM with 0 #1 $display(" Address = %g Data = %h",i,ram[i]); end #1 $finish; end endmodule

5.7 TASK & FUNCTION Tasks are used in all programming languages, generally known as procedures or subroutines. The lines of code are enclosed in task....end task brackets. Data is passed to the task, the processing done, and the result returned. They have to be
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VLSI DESIGN
VERILOG HDL
specifically called, with data ins and outs, rather than just wired in to the general netlist. Included in the main body of code, they can be called many times, reducing code repetition. Tasks are defined in the module in which they are used. It is possible to define a task in a separate file and use the compile directive 'include to include the task in the file which instantiates the task. Tasks can include timing delays, like posedge, negedge, # delay and wait. Tasks can have any number of inputs and outputs. The variables declared within the task are local to that task. The order of declaration within the task defines how the variables passed to the task by the caller are used. Tasks can take, drive and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of task execution. Tasks can call another task or function. Tasks can be used for modeling both combinational and sequential logic. A task must be specifically called with a statement, it cannot be used within an expression as a function can.
Syntax A task begins with keyword task and ends with keyword endtask Inputs and outputs are declared after the keyword task. Local variables are declared after input and output declaration. Example
module simple_task(); task convert; input [7:0] temp_in; output [7:0] temp_out; begin temp_out = (9/5) *( temp_in + 32) end endtask endmodule
FUNCTION
A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more than one output, can not contain delays. Functions are defined in the module in which they are used. It is possible to define functions in separate files and use compile directive 'include to include the function in the file which instantiates the task. Functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay. www.verilogcourseteam.com
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Syntax

VERILOG HDL
Functions can have any number of inputs but only one output. The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used. Functions can take, drive, and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of function execution. Functions can be used for modeling combinational logic. Functions can call other functions, but can not call tasks
A function begins with keyword function and ends with keyword endfunction inputs are declared after the keyword function.
EXAMPLE module simple_function(); function myfunction; input a, b, c, d; begin myfunction = ((a+b) + (c-d)); end endfunction endmodule
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VLSI DESIGN EXAMPLES

Digital circuit for 2 to 4 decoder
VERILOG HDL
RTL Coding for 2 to 4 decoder

module decoder_2to4_gates (A0,A1,D0,D1,D2,D3); input A0,A1; output D0,D1,D2,D3; wire n1,n2; not i1 (n1,A0); not i2 (n2,A1); and a1 (D0,n1,n2); and a2 (D1,n1,A1); and a3 (D2,A0,n2); and a4 (D3,A0,A1); endmodule
Comparator
Digital circuit for Comparator
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RTL Coding for Comparator
module comparator(A,B,AEQB,ALTB,AGTB); input [3:0]A,B; output AEQB,ALTB,AGTB; wire A3,A2,A1,A0; wire B3,B2,B1,B0; assign A3=A[3]; assign A2=A[2]; assign A1=A[1]; assign A0=A[0]; assign B3=B[3]; assign B2=B[2]; assign B1=B[1]; assign B0=B[0]; wire N1,N2,N3,N4,N5,N6,N7,N8; wire N11,N12,N13,N14,N15,N16,N17,N18; wire M1,M2,M3,M4; wire M11,M12,M13,M14,M15,M16,M17,M18; not not not not not not not not and and and and and and and and A11(N1,A3); A12(N2,B3); A13(N3,A2); A14(N4,B2); A15(N5,A1); A16(N6,B1); A17(N7,A0); A18(N8,B0); A19(N11,B3,N1); A20(N12,A3,N2); A21(N13,B2,N3); A22(N14,A2,N4); A23(N15,B1,N5); A24(N16,A1,N6); A25(N17,B0,N7); A26(N18,A0,N8);
VERILOG HDL
nor A27(M1,N11,N12); nor A28(M2,N13,N14); nor A29(M3,N15,N16); nor A30(M4,N17,N18); and A31(M11,M1,N13); and A32(M12,M1,N14); and A33(M13,M1,M2,N15); and A34(M14,M1,M2,N16); and A35(M15,M1,M2,M3,N17); and A36(M16,M1,M2,M3,N18); and A37(AEQB,M1,M2,M3,M4); or A38(ALTB,N11,M11,M13,M15); or A39(AGTB,N12,M12,M14,M16);
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VLSI DESIGN
endmodule
VERILOG HDL
D-latch Digital circuit for D-latch
RTL coding for D-latch

module d_latch( D,E,Q,Qbar); input D,E; output Q,Qbar; wire n1,n2,n3,n4; not a11(n1,D); and a12(n2,E,n1); and a13(n3,E,D); nor a14(Q,n2,Qbar); nor a15(Qbar,n3,Q); endmodule
D Flip Flop
Digital circuit for D Flip Flop RTL coding for D Flip Flop
module d_flipflop( D,C,Q,Qbar); input D,E; output Q,Qbar; wire n1,n2,n3,n4;
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VLSI DESIGN
not a11(n1,D); nand a12(n2,C,n1); nand a13(n3,C,D); nor a14(Qbar,n2,Q); nor a15(Q,n3,Qbar); endmodule
VERILOG HDL
Half Adder Digital circuit for half adder
RTL coding for Half Adder

module half_adder(A,B,S,C); input A,B; output S,C; xor a11(S,A,B); and a12(C,A,B); endmodule
Full Adder Digital circuit for Full Adder
RTL coding for Full Adder

module full_adder(A,B,CIN,S,COUT); input A,B,CIN; output S,COUT; wire n1,n2,n3,n4,n5,n6; xor a11(n1,A,B); xor a12(S,n1,CIN);
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VLSI DESIGN
and a13(n2,n1,CIN); and a14(n3,A,B); or a15(COUT,n2,n3); endmodule
VERILOG HDL
Ripple Carry Adder Digital circuit for Ripple Carry Adder
RTL coding for Ripple Carry Adder Circuit

module ripple_carry_adder(ai,bi,cin,sum,carry); input ai,bi,cin; output sum,carry; wire n1,n2,n3; wire m1,m2,m3,m4,m5,m6,m7; not a11(n1,ai); not a12(n2,bi); not a13(n3,cin);
nand a14(m1,bi,cin); nand a15(m2,cin,ai); nand a16(m3,ai,bi);
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VLSI DESIGN
nand nand nand nand nand nand a17(m4,ai,bi,cin); a18(m5,n3,n2,ai); a19(m6,n3,bin,n1); a20(m7,cin,n2,n1); a21(carry,m1,m2,m3); a22(sum,m4,m5,m6,m7);
VERILOG HDL
endmodule
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Unit5 Verilog HDL

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VLSI DESIGN

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VLSI DESIGN UNIT 5 VERILOG HDL

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VLSI DESIGN UNIT 5 5. HISTORY OF VERILOG

5.1 Overview of Digital Design with Verilog HDL

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Figure 5.1 VLSI Design Flow

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Figure 5.5 Layout view of a system

5.2 DESIGN HIERARCHIES

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Description Unsigned or signed positive number Signed negative number

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5.5 MODELING CONCEPTS

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GATE LEVEL MODELING

Figure 5.18 Gates symbol

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Table 5.6Truth Table Example Gate Instantiation of Buf/Not gates

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Examples AND Gate from NAND Gate

Figure 5.20 Structural model of AND gate from two NANDS

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D-Flip flop from NAND Gate

Figure 5.21 Structural model of D Flip-flop from NAND Gate

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Multiplex from Primitives

Figure 5.22 Structural model of Multiplex from Primitives

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5.6 DATA FLOW AND BEHAVIORAL MODELING

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Example - Tri-state buffer using continuous assignment statement

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Description a less than b a greater than b a less than or equal to b