Offline UPS Reference Design Using The dsPIC DSC

AN1279
Offline UPS Reference Design Using the dsPIC DSC

Types of UPS Systems
Author: Sagar Khare
Microchip Technology Inc. A typical UPS for computers has four basic protection
roles: being able to cope with power surges, voltage
shortage, complete power failure and wide variations in
UPS OVERVIEW the electric current frequency. There are three types of
UPS systems, depending on how the electric power is
An Uninterruptible Power Supply, or UPS, is an being stored and relayed to the electronic device
electronic device that provides an alternative electric connected to them:
power supply to connected electronic equipment when
Offline UPS (also known as Stand-by UPS)
the primary power source is not available.
Line-Interactive (or Continuous UPS)
Unlike auxiliary power, a UPS can provide instant
Online UPS (often called double conversion supply)
power to connected equipment, which can protect
sensitive electronic devices by allowing them to shut OFFLINE UPS
down properly and preventing extensive physical
damage. However, a UPS can only supply energy for a An Offline UPS system (see Figure 1), redirects the
limited amount of time, typically 15 to 20 minutes. electric energy received from the AC input to the load
Although its use can extend to a virtually unlimited list and only switches to providing power from the battery
of applications, in past years the UPS has become when a problem is detected in the utility power. Per-
even more popular as a means of protecting computers forming this action usually takes a few milliseconds,
and telecommunication equipment, thus preventing during which time the power inverter starts supplying
serious hardware damage and data loss. electric energy from the battery to the load.
Application Markets for UPS Systems FIGURE 1: OFFLINE UPS DIAGRAM
UPS systems provide for a large number of applica-

AC Input Load
tions in a variety of industries. Their common applica-
tions range from small power rating for personal
computer systems to medium power rating for medical
facilities, life-support systems, data storage, and emer-
gency equipment, and high power rating for telecom-
Inverter
munications, industrial processing, and online
management systems. Different considerations should Charger
be taken into account for these applications. As an
example, a UPS for emergency systems and lighting
may support the system for 90-120 minutes. For other
applications like computer backup power, a UPS may
typically support the system for 15-20 minutes. If power
is not restored during that time, the system will be
gracefully shut down. Battery
If a longer backup period is considered, a larger battery

is required. For process equipment and high power
applications, some UPS systems are designed to pro-
vide enough time for the secondary power sources,
such as diesel generators, to start up.
2009-2011 Microchip Technology Inc. DS01279B-page 1

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LINE-INTERACTIVE UPS FIGURE 3: ONLINE UPS DIAGRAM
A Line-Interactive UPS (see Figure 2), always relays Static Switch
electric energy through the battery to the load. When (Static Bypass)
AC mains power is available, the battery is being
charged continuously. At the same time, the UPS reg-
ulates the AC output voltage and the lag related to cou-
pling the inverter is nearly zero. When a power outage
occurs, the transfer switch opens and the electric
energy flows from the battery to the load (Stored
Energy mode). Due to these characteristics, continu-
ous UPS systems tend to be somewhat more AC Input Load
expensive than an offline UPS.
FIGURE 2: LINE-INTERACTIVE UPS Rectifier/ Inverter

Charger
DIAGRAM
Static Switch Battery
AC Input Load SYSTEM SPECIFICATIONS

The reference design in this application note describes
the design of an Offline Uninterruptible Power Supply
(UPS) using a Switch Mode Power Supply (SMPS)
dsPIC Digital Signal Controller (DSC).
Inverter
The Offline UPS Reference Design consists of three
major UPS topology blocks:
Push-Pull Converter (steps up the DC battery volt-
age to a constant high-voltage DC)
Legend: Battery
Full-Bridge Inverter (converts DC voltage to a
Normal mode sinusoidal AC output)
Stored-energy mode Flyback Switch Mode Charger (current source
and charges battery with constant current)
ONLINE UPS The input and output specifications are shown in
An Online UPS (see Figure 3), combines the two basic Table 1.
technologies of the previously described UPS models,
with rectifiers and inverter systems working all of the TABLE 1: I/O SPECIFICATIONS
time. As is the case with a Line-Interactive UPS, the 220V UPS Version Specifications
power transfer is made instantly as an outage occurs,
with the rectifier simply being turned off while the AC Input 220 VAC 10%, 50 Hz 3 Hz
inverter draws power from the battery. As utility power DC Input 3 x 12 VDC (lead acid battery)
is again established, the inverter continues to supply UPS Output 220 VAC, 50 Hz 1 Hz,
power to the connected devices, while the rectifier sinusoidal
resumes its activity, recharging the battery. This design
is sometimes fitted with an additional transfer switch for Rating 1000W/1000 VA,
bypass during a malfunction or overload. (1300VA - 2 seconds)
Input Filtering EMI/RFI filtering
110V UPS Specifications
AC Input 110 VAC 10%, 60 Hz 3 Hz
DC Input 3 x 12 VDC (lead acid battery)
UPS Output 110 VAC, 60 Hz 1 Hz,
sinusoidal
Rating 1000W/1000 VA,
(1300VA - 2 seconds)
Input Filtering EMI/RFI filtering
DS01279B-page 2 2009-2011 Microchip Technology Inc.

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1 kVA OFFLINE UPS REFERENCE After a power failure, the system is switched to UPS
mode. In this situation, the DPDT relay is turned OFF
DESIGN
to prevent power from being delivered to the AC line.
The Offline UPS system shown in Figure 4 operates in The push-pull converter steps up the battery voltage to
Stand-by mode and in UPS mode. When AC line volt- 380 VDC. The high DC voltage is then converted with
age is present, the system is in Stand-by mode until a the full-bridge inverter and filtered with an LC filter to
failure occurs on the AC line. During Stand-by mode, create a pure sine wave 220/110 VAC output where
the battery is charged and is maintained after becom- load is connected. This power switchover sequence is
ing fully charged. When the battery is charging, the made in less than 10 ms.
inverter works as a rectifier through the IGBTs anti-par-
allel diodes. The flyback switch mode charger acts as a
current generator and provides constant charging
current to the battery.
FIGURE 4: OFFLINE UPS REFERENCE DESIGN
EMI Filter DPDT Load

220 VAC, Relay
50 Hz
220 VAC
Constant Current Flyback Switch

Mode Charger LC Filter
3 x 12 VDC Push-Pull 380 VDC Full-Bridge

Battery DC/DC Inverter/
Converter Rectifier

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Listing of I/O Signals for Each Block, temperature sensor measures heat sink temperature,
Type of Signal, and Expected Signal and the primary current measurement (IP) protects the
converter in case of transformer flux walking. The PWM
Levels
outputs from the dsPIC DSC are firing pulses to the
driver to control the output voltage.
PUSH-PULL CONVERTER
Table 2 lists the resources used by the dsPIC DSC
As specified in Figure 5, measurement of DC output
device for a push-pull converter.
voltage (UDCM) is required to implement the control
algorithm. The EPP signal is for enabling the driver, the
FIGURE 5: PUSH-PULL CONVERTER RESOURCE DIAGRAM

UDCM+
UBAT IPM
PGND UDCM-
UCDM
IP
T Temperature
EPP
DRIVER Sensor
UB
ADC
PWM
PWM
ADC
ADC
ADC
I/O
dsPIC33FJ16GS504
TABLE 2: RESOURCES REQUIRED FOR A DIGITAL PUSH-PULL CONVERTER

dsPIC DSC
Signal Name Type of Signal Expected Signal Level
Resources Used
UDCM Analog AN3 2.99V
IP Analog AN2 0V-1.65V
T (optional, not implemented Analog AN8 0V-3.3V
in software)
UB Analog AN5 1.5V-1.98V
EPP Enable driver, Digital RB6
Push-Pull Gate Drive Digital PWM3H, PWM3L

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FULL-BRIDGE INVERTER to the rectifier. This happens when the UPS is
operational and the battery is depleted, the UPS goes
The block diagram in Figure 6 illustrates that
off or initial system connect to grid power. The
measurement of the AC output voltage (ACO) is
FLT_CLR signal is used to reset the driver when a fault
required to implement the control algorithm. With
is detected. FAULT/SD and SYS_FLT are used to
measurement of the output current (I), that current can
enable or disable the driver or detect driver faults.
be limited to prevent overloading of the converter. The
Detailed descriptions of these signals can be found in
presence of power grid voltage is detected with
the data sheet of the drivers (IR2214). Switching of the
measurement of (ACI) voltage. When power grid
inverter leg IGBTs is controlled by firing pulses S3, S4
voltage fails, signal A2 turns off the relay K2 and
and S5, S6, and is generated by the dsPIC DSC PWM
prevents power flow to the line when the UPS is
modules.
operational. Signal A1 controls the K1 relay, which is off
when DC link voltage is low to prevent current inrush in Table 3 shows the resources used by a dsPIC DSC
the DC link capacitors when power grid voltage is fed device for a full-bridge inverter.
FIGURE 6: DIGITAL FULL-BRIDGE INVERTER RESOURCE DIAGRAM

UDC+ A1 (Inverter Series Relay)
DRIVER
FAULT/SD
SYS_FLT
FLT_CLR
S3 A2 (Mains Relay)
ACI1M
S4
R Power Grid
PGND L C
ACI2M
S5 I
FAULT/SD
FLT_CLR
SYS_FLT
S6 ACO1M ACO2M
Load
DRIVER
PWM
PWM
ADC
PWM
PWM
ACO
I/O
I/O
I/O
KF(1)
I/O
ADC
I/O
dsPIC33FJ16GS504 ACI
ADC KG(1)
Note 1: KF and KG are feedback gain circuits. Refer to Appendix E: Schematics and Board Layout for details.
TABLE 3: RESOURCES REQUIRED FOR A DIGITAL FULL-BRIDGE INVERTER

dsPIC DSC
Resources Used
ACO Analog AN1 0.27V-3.3V
ACI Analog AN11 0.15V-3.16V
I Analog AN0 2.5V (nominal)
A1 Digital output RC10
A2 Digital output RC0
FLT_CLR Digital output RB7
FAULT/SD Digital input (external interrupt) RC13 (INT1)
SYS_FLT Digital input RC8
S3, S4 (gate drive) PWM output PWM1H, PWM1L
S5, S6 (gate drive) PWM output PWM2H, PWM2L

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FLYBACK SWITCH MODE CHARGER
The block diagram in Figure 7 shows that an analog
current controller is used for battery charging. Four sig-
nals are needed: EFB signal for enabling topswitch, (IB)
for measuring battery charging current, (UB) for mea-
suring battery voltage and IREF for reference set with
PWM4L output.
FIGURE 7: DIGITAL FLYBACK SWITCH MODE CHARGER RESOURCE DIAGRAM

UDC+ Shunt UBAT
K3(1)
PGND
Flyback
PGND transformer UFEEDBACK
+15V
K4(1)
PI
45V
TOPSWITCH
ENABLE
EFB
UB
ADC
- IB
IFEEDBACK ADC
IERROR
PI PWM
IREF
I/O
dsPIC33FJ16GS504
Analog Controller
Note 1: K3 and K4 are feedback gain circuits. Refer to Appendix E: Schematics and Board Layout for details.
Table 4 shows the resources used by the dsPIC DSC

device for a flyback switch mode charger.
TABLE 4: RESOURCES REQUIRED FOR A DIGITAL FLYBACK SWITCH MODE CHARGER

dsPIC DSC
Resources Used
IBATM Analog AN4 0V-1.67V
UBAT Analog AN5 1.5V-2V
EFB Digital output RC7
IREF PWM output PWM4L

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DC/DC CONVERTER Selection of a topology depends on careful analysis of
the design specifications, cost and size requirements of
Most UPS designs contain a transformer-type DC/DC the converter.
converter. The transformer provides electrical isolation
Operation of each of the above topologies is described
between the input and output of the converter. The
in the following sections of this application note. Details
transformer also provides the option to produce
of the topology selection and hardware design are
multiple voltage levels by changing the turns ratio, or
provided in subsequent sections.
provide multiple voltages by using multiple secondary
windings.
Forward Converter
Transformer-type DC/DC converters are divided into
five basic topologies: A forward converter, which can be a step-up or step-
Forward Converter down converter, is shown in Figure 8. When the
transistor Q is ON, VIN appears across the primary, and
Push-Pull Converter
then generates output voltage determined by
Half-Bridge Converter Equation 1.
Full-Bridge Converter
The diode D1 on the secondary ensures that only
Flyback Converter positive voltages are applied to the output circuit while
The Flyback topology operation differs slightly from D2 provides a circulating path for inductor current if the
other topologies in that energy is stored in magnetic transformer voltage is zero or negative. A third winding
material and then released. Other topologies always is added to the transformer of a forward converter, also
transfer energy directly from input to output. Another known as a reset winding. This winding ensures that
case in which topologies are distinguished from each the magnetization of the transformer core is reset to
other is transformer core utilization: zero at the start of the switch conduction. This winding
prevents saturation of the transformer.
Unidirectional core excitation where only the
positive part (quadrant 1) of the B-H loop is used
(flyback and forward converters)
Bidirectional core excitation where both the posi-
tive (quadrant 1) and the negative (quadrant 3) parts
of the B-H loop are utilized alternatively (push-pull,
half-bridge, and full-bridge converters)
FIGURE 8: FORWARD CONVERTER

T L
D1
+ + +
D2 VOUT
+ +
VIN -
-
D3 Q
EQUATION 1:
N2
Vout = Vin d
N1
where d is the duty cycle of the transistor Q

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Push-Pull Converter There are two important considerations with the
push-pull converter:
A push-pull converter is shown in Figure 9. When Q1
switches ON, current flows through the upper half of Both transistors must not conduct together, as this
the T1 transformer primary and the magnetic field in T1 would effectively short circuit the supply. This
expands. The expanding magnetic field in T1 induces a means that the conduction time of each transistor
voltage across the T1 secondary; the polarity is such must not exceed half of the total period (d < 0.5)
that D2 is forward-biased and D1 is reverse-biased. D2 for one complete cycle, otherwise conduction will
conducts and charges the output capacitor C2 via L1. overlap.
L1 and C2 form an LC filter network. When Q1 turns The magnetic behavior of the circuit must be
OFF, the magnetic field in T1 collapses and after a uniform; otherwise, the transformer may saturate,
period of dead time (dependent on the duty cycle of the and this would cause destruction of Q1 and Q2.
PWM drive signal), Q2 conducts, current flows through This behavior requires that the individual
the lower half of T1s primary, and the magnetic field in conduction times of Q1 and Q2 must be exactly
T1 expands. At this point, the direction of the magnetic equal and the two halves of the center-tapped
flux is opposite to that produced when Q1 conducted. transformer primary must be magnetically
The expanding magnetic field induces a voltage across identical.
the T1 secondary; the polarity is such that D1 is for- These criteria must be satisfied by the control and drive
ward-biased and D2 is reverse-biased. D1 conducts circuit and the transformer. The output voltage equals
and charges the output capacitor C2 via L1. After a that of Equation 2.
period of dead time, Q1 conducts and the cycle
repeats. EQUATION 2:
N2
Vout = 2 Vin d
N1
where:
d is the duty cycle of the transistors and 0 < d < 0.5
N2
------ is the secondary-to-primary turns ratio of the
N 1 transformer
FIGURE 9: PUSH-PULL CONVERTER
T1 D1
+ VOUT
L1
+ +
+
C2
+ VIN 0V
+ +
D2
+
C1
Q1 Q2
0V

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Half-Bridge Converter
The half-bridge converter (see Figure 10) is similar to
the push-pull converter, but a center-tapped primary is
not required. The reversal of the magnetic field is
achieved by reversing the direction of the primary wind-
ing current flow. In this case, two capacitors. C1 and
C2, are required to form the DC input mid-point. Tran-
sistors Q1 and Q2 are turned ON alternately to avoid a
supply short circuit, in which case the duty cycle, d,
must be less than 0.5.
For the half-bridge converter, the output voltage VOUT
equals that of Equation 3.
FIGURE 10: HALF-BRIDGE CONVERTER
+VIN
L1
+ T1 D1
C1 Q1
+ +VOUT
+
+ C3
0V
+
+
C2
Q2 D2
0V
EQUATION 3:
N2
Vout = Vin d
N1
where:
d is the duty cycle of the transistors and 0 < d < 0.5
N2/N1 is the secondary-to-primary turns ratio of
the transformer

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Full-Bridge Converter
The full-bridge converter topology shown in Figure 11,
is basically the same as the half-bridge converter,
where four transistors are used.
Diagonal pairs of transistors (Q1-Q4 or Q2-Q3) con-
duct alternately, thus achieving current reversal in the
transformer primary. Output voltage equals that of
Equation 4.
FIGURE 11: FULL-BRIDGE CONVERTER
+VIN
L1
T1 D1
Q1 Q3
+ +VOUT
+
+ C2
+ 0V
C1 +
Q2 Q4 D2
0V
EQUATION 4: Flyback Converter

N2 Figure 12 shows a flyback converter circuit. When tran-
Vout = 2 Vin d sistor Q1 is ON, due to the winding polarities, the diode
N1 D1 becomes reverse-biased. Therefore, transformer
where: core flux increases linearly. When transistor Q1 is
d is the duty cycle of the transistors and 0 < d < 0.5 turned OFF, energy stored in the core causes the cur-
rent to flow in the secondary winding through the diode
N2/N1 is the secondary-to-primary turns ratio of D1 and flux decreases linearly. Output voltage is given
the transformer by Equation 5.
FIGURE 12: FLYBACK CONVERTER
T1 D1
+VIN +VOUT
+
+
C2
+ +
C1 0V
Q1
0V
EQUATION 5:
N2 d
Vout = Vin
N1 1 d

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VOLTAGE SOURCE INVERTER (VSI) Full-Bridge VSI
A single-phase Voltage Source Inverter (VSI) can be Figure 14 shows the topology of a Full-Bridge VSI. This
defined as a half-bridge and a full-bridge topology. Both inverter is similar to the half-bridge inverter; however, a
topologies are widely used in power supplies and second leg provides the neutral point to the load. Both
single-phase UPS systems. switches S1+ and S1- (or S2+ and S2-) cannot be on
simultaneously because a short circuit across the DC
Half-Bridge VSI link voltage source vi would be produced. To avoid the
short circuit across the DC bus and the undefined AC
Figure 13 shows the topology of a Half-Bridge VSI, output voltage condition, the modulating technique
where two large capacitors are required to provide a should ensure that either the top or the bottom switch
neutral point N, such that each capacitor maintains a of each leg is ON at any instant. The AC output voltage
constant voltage vi 2. Because the current can take values up to the DC link value vi, which is
harmonics injected by the operation of the inverter are twice the value obtained with half-bridge VSI topolo-
low-order harmonics, a set of large capacitors (C+ and gies. Several modulating techniques have been devel-
C-) is required. The duty cycle of the switches is used oped that are applicable to full-bridge VSIs. Among
to modulate the output voltage. The signals driving the them, the best known are bipolar and unipolar PWM
switches must ensure some dead time to prevent techniques.
shorting of the DC bus.
FIGURE 13: SINGLE-PHASE

HALF-BRIDGE VSI
ii
+ S+ D+
VI 2 C+
- io
a +
VI + VO
-
N -
+
VI 2 C-
- S- D-
FIGURE 14: SINGLE-PHASE FULL-BRIDGE VSI
ii
S1+ D1+ S2+ D2+
io
a +
+
VI + VI C+ VO
- b
- -
S1- D1- S2- D2-

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BATTERY CHARGER of the battery, and a rectifier that smooths out the
existing sinusoidal AC signal into a constant-voltage
When the AC mains voltage is present, the Offline UPS DC signal. The linear regulating element may be a
charges the batteries, and therefore, a battery charger passive component such as a resistor or an active
circuit is implemented. component such as a transistor that is controlled by a
Most battery chargers can be divided into four basic reference signal. Figure 15 shows a simplified
design types, or topologies: schematic of a linear charger with a linear power supply
with a resistor as the current regulating element.
Linear Chargers
Switch Mode Chargers
Switch Mode Chargers
Ferroresonant Chargers
SCR Chargers In a switch mode charger, AC voltage is rectified, and
then converted to a lower DC voltage through a DC/DC
converter. This type of charger contains additional
Linear Chargers
charge control circuitry to regulate current flow into the
Linear chargers consist of a power supply, which battery. The charge control regulates the way in which
converts AC power to lower voltage DC power, and a the power switch turns ON and OFF, and may be
linear regulating element, which limits the current that accomplished through a circuit, a specialized inte-
flows into the battery. The power supply typically grated chip, or some type of software control. A simpli-
consists of a transformer that steps down AC power fied schematic for a single piece switch mode charger
from 220/110 VAC to a lower AC voltage closer to that is shown in Figure 16.
FIGURE 15: LINEAR CHARGER
Transformer Rectifier Current Battery

Regulating
Element
AC Input
R1
DC Output
Charge
Power Supply Control
FIGURE 16: SWITCH MODE CHARGER
Power Output
Rectifier Transformer Battery
Switch Filter
AC Input
DC Output
Power Supply
Current Control
Logic

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Ferroresonant Chargers SCR Chargers
Ferroresonant chargers (sometimes called ferro char- SCR chargers use a special component known as a
gers), operate by way of a special component called a Silicon-Controlled Rectifier (SCR) to control the current
ferroresonant transformer. The ferroresonant trans- to the battery. The SCR is a controllable switch that can
former reduces the AC voltage to a lower regulated be turned ON and OFF multiple times per second. After
voltage level while simultaneously controlling the a transformer reduces utility voltage to a value near
charge current. A rectifier then converts the AC power that of the battery, the diodes rectify the current while
to DC power suitable for the battery. Figure 17 shows a the SCR enables the flow of charge current according
block diagram of a ferroresonant charger. to a control signal. A block diagram of an SCR charger
is shown in Figure 18.
FIGURE 17: FERRORESONANT CHARGER
Ferroresonant
Transformer Rectifier
Battery
Charge
Control
AC Input DC Output
Power Supply
FIGURE 18: SCR CHARGER
Diode Current
Transformer Rectifier SCR Limiter Battery
AC Input
DC Output
Power Supply Charge Control

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SOFTWARE DESIGN
The Offline UPS Reference Design is controlled by a
single dsPIC DSC device as shown in the system block
diagram in Figure 19.
FIGURE 19: OFFLINE UPS BLOCK DIAGRAM
Power Conversion Block

UPS
Full Bridge Output
Push-Pull Load
Voltage-Source
Converter
Inverter
3x12V Batteries
Relay Logic
AC Mains Input Rectified

by Inverter Body Diodes
Auxiliary Flyback Battery
Power Charger
Supply
dsPIC DSC
USB
LCD Controller
Controller
PIC18F2420
PIC18F2450
LCD Module USB Port

Legend:
User Interface Block Signal Flow
Power Flow
Computer

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The dsPIC DSC device is the heart of the Offline UPS. In addition to the intelligent power peripherals, the
It controls all critical operations of the system as well as dsPIC DSC also provides built-in peripherals for digital
the housekeeping operations. The functions of the communications including I2C, SPI and UART that
dsPIC DSC can be broadly classified into the following can be used for power management and housekeeping
categories: functions.
All power conversion algorithms Note: For device details, refer to the dsPIC33F
UPS state machine for the different modes of GS series device data sheets. For more
operation information on the peripherals, refer to the
Auxiliary tasks including true RMS calculations, corresponding SMPS sections in the
soft start routines and user interface routines. dsPIC33F/PIC24H Family Reference
Manual.
The dsPIC DSC device offers intelligent power periph-
erals specifically designed for power conversion appli- A high-level diagram of the Offline UPS software struc-
cations. These intelligent power Peripherals include ture is shown in Figure 20. As shown in this figure, the
the High-Speed PWM, High-Speed 10-bit ADC, and software is broadly partitioned into two parts:
High-Speed Analog Comparator modules. UPS State Machine (includes power conversion
These peripheral modules include features that ease routines)
the control of any switch-mode power supply with high User Interface Software
resolution PWM, flexible ADC triggering, and
These partitions are described in more detail in
comparator fault handling.
subsequent sections of this document.
FIGURE 20: OFFLINE UPS SOFTWARE: HIGH-LEVEL PARTITIONS
Offline UPS Software
UPS State Machine User Interface Software

(Interrupt Based)
Priority: Medium
Execution Rate: Medium
Power Conversion Algorithms Priority: Low

(Interrupt Based) Execution Rate: Low
Priority: High
Execution Rate: High

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UPS State Machine When a power failure occurs, the UPS state machine
initiates a switchover sequence from Battery Charger
The Offline UPS software implements a state machine mode to Inverter mode. When the AC mains is detected
to determine the mode of operation for the system. The again, the state machine executes the switchover from
state machine is executed once every 100 s inside a Inverter mode to Battery Charger mode. These swi-
timer Interrupt Service Routine (ISR). The state tchover functions must be executed in as little time as
machine configures the on-chip peripherals to execute possible to ensure uninterrupted power to the load.
the correct power conversion algorithms.
The Battery Charger mode and Inverter mode are the
During normal operation of the offline UPS, the state two normal operating modes of the Offline UPS. There
machine configures the system peripherals to execute are two other modes of operation, namely System
the correct power conversion algorithms as determined Startup and System Error. Each mode of operation for
by the system state. the Offline UPS is described in the following sections.
Figure 21 shows the Offline UPS state diagram.
FIGURE 21: OFFLINE UPS STATE DIAGRAM
M
System DC AIN
Startup BA _LINS_O
TT K _ K &
(BATTERY_OK || BATTERY_LOW)
M E R OK
DC AINS Y_
LO &
_
BA LIN _OK W
TT K_ &
E R OK
Y_
OK &
DC_LINK_OK &
MAINS_OK &
MAINS_NOT_OK &
DC_LINK_OK &
BATTERY_OK
M
DC AINS
BA _LIN _OK
TT K
ER _OK &
Y_
LO &
OLTAGE
TAGE
M W
DC AIN
RVOLTAGE
S
BA _LIN _OK
MAINS_OK &
TT K _
OL
MAINS_NOT_OK
E R OK &
DC_LINK_OVERV
Y_
BATTERY_OVERV
OK &
MAINS_OK &
Battery
DC_LINK_UNDE
Inverter Mode Charger

Mode
MA
IN
DC_ S_NOT
L _
BAT INK_O OK &
TER K & A GE
Y_ &
OK
_OK LT
O
OT RV E
BA MA S_N DE AG
TT I IN _U N LT
ER NS_N A
M RY V O
AG
E
BA Y_
UN OT_O E V ER LT
T O
TT
ER DE K T _O V GE
DC Y_ RV & BA RY D ER L TA
_L OV OL E
INK ER TA TT UN RV
O
DC _U VO GE BA K_ VE
_L ND LT L IN O
IN K ER AG _ K_
_O VO E System Error DC IN
VE LT
AG C _L
RV D
OL E
TA
GE
D
C
BATTE
_L
DC_
IN
BATTERY_OVERVOLTAGE
K_
RY_U
O
LINK
VE
R
ND
VO
_UN
LT
ERV
AG
DERV
E
L TA G O
O LTAG
E

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System Startup The battery charger control is implemented partly in
hardware and partly in software. A flyback converter IC
When the Offline UPS is turned ON, the state of the is used to produce a constant current source from the
system is unknown. Therefore, the state machine first rectified AC mains voltage. The dsPIC DSC device pro-
monitors all system variables and determines the vides the reference signal for the output current of the
starting state of the UPS. flyback converter.
During this time, the state machine also monitors for This current reference signal is generated by filtering
fault conditions and ensures that all system variables the PWM output from the dsPIC DSC. The charging
are within specification so that the UPS can switch to current is controlled by modifying the duty cycle of the
normal operation. current reference PWM signal.
BATTERY CHARGER MODE When the Battery Charger mode is started, the dsPIC
DSC device sets up the minimum charging current.
If the AC mains voltage is detected, the Inverter mode Then, the battery voltage and battery current are mea-
is disabled (if running) and the Offline UPS switches to sured using the high-speed 10-bit ADC module. The
the Battery Charger mode. The dsPIC DSC device pro- measured battery voltage determines the charging
vides the reference current level with a variable duty state, and the code specifies the correct charging cur-
cycle PWM signal. rent from the battery charging profile shown in
The battery voltage is measured to ascertain the state Figure 22.
of the battery. Depending on the battery state, the value All system variables are monitored by the state
of the charging current is modified so as to achieve the machine to initiate a switchover sequence if required.
fastest charging time and also to prolong the life of the When an AC mains power failure is detected, the state
batteries. machine switches the UPS operation to the Inverter
The battery charging profile has been configured for mode. If a fault is detected, the system state is changed
sealed lead-acid (SLA) batteries, and is summarized in to System Error.
Figure 22.
FIGURE 22: OFFLINE UPS BATTERY CHARGING PROFILE
Charging Trickle Bulk Over Float

Charging Charging
Current Charging Charging Charging Charging
Off Off
State State State State
2.25A
0.1A
30V 35.7V 40.5V 43.2V 45V Battery Voltage
Note: Not drawn to scale

AN1279
BATTERY CHARGER INITIALIZATION After the inverter is turned OFF, the output relay is
ROUTINE released so that the AC mains is connected to the UPS
output. The output relay must be released in the short-
When the offline UPS switches to the Battery Charger
est possible duration so that there is no interruption of
mode, the code must ensure that the previous mode is
power at the UPS output. Typically, relay switching
turned OFF. To reduce stress on the hardware
times are the limiting factor for the switchover duration.
components, the full-bridge inverter is turned OFF
when the output reaches 0V. The flowchart for the
Battery Charger mode is shown in Figure 23.
FIGURE 23: BATTERY CHARGER INITIALIZATION FLOWCHART

UPS State Machine
Push-Pull Control Loop Battery Charger Initialization

Priority: Medium
(ADC Interrupt)
System Inverter
Startup Mode
Priority: High
Set Relay flag =
NOT_READY_TO_SWITCH
Inverter Control Loop

(ADC Interrupt) No Is relay ready to switch?
(Relay flag cleared in ADC ISR)
Priority: High Yes
Initiate relay release
Call 4 ms delay to allow inverter

output to become 0V
Battery Voltage and Current
Measurement
Turn OFF inverter PWM signals
(ADC Interrupt)
Bypass DC link charging resistor
Priority: Medium Call 12 ms delay to allow

complete release of relay
Reset charging state to UNKNOWN

and set minimum charging
AC Mains Detection current reference
(ADC Interrupt)
Enable charging current
reference signal (PWM4L)
Enable Battery Charger

Priority: Medium Flyback Converter
Battery
Charger
Mode

AN1279
The dsPIC DSC device implements a predictive tech- The battery charging current control scheme is illus-
nique to achieve the fastest switchover time possible. trated in Figure 24. The battery charger control routine
This is done by predicting the relay switching time and is called inside the state machine under the Battery
initiating the relay release even before the inverter out- Charger mode. The battery charging control loop is
put has turned OFF. The switchover operation from the therefore executed at the same rate (once every
inverter to the AC mains is described in subsequent 100 s) and also at the same priority level as the state
sections of this application note. machine. The battery current and voltage measure-
ment is triggered using the PWM trigger feature on the
BATTERY CHARGER CONTROL SCHEME dsPIC DSC device.
The battery charger control loop is implemented in the The measured data is scaled and stored as a variable
state machine. in data memory asynchronous to the control loop exe-
If the measured charging current is less than the refer- cution. When the control loop is called, the data is sim-
ence, the duty cycle is incremented by a fixed step. ply read from the data memory and used for control
Conversely, if the charging current exceeds the refer- loop calculations. The flowchart for the battery charger
ence, the duty cycle is reduced by the same fixed step. control loop is shown in Figure 25.
This process continues until the current error reduces
to a negligible value.
FIGURE 24: BATTERY CHARGER CONTROL SCHEME
Quantizer
+K
Duty Cycle
Charging Current
Reference 0
-1
-K z
Measured Charging Current

AN1279
FIGURE 25: BATTERY CHARGER MODE FLOWCHART
UPS State Machine
Push-pull control loop Battery Charger Control Loop

(ADC Interrupt) Priority: Medium
Battery
Charger
Mode
Priority: High
Yes Is battery voltage <

BATTERY_TRICKLE_VOLTAGE?
Inverter control loop

(ADC Interrupt) No
Is battery voltage < Yes

BATTERY_BULK_VOLTAGE?
Priority: High
No Set Maximum
Charging Current
Is battery voltage < Yes

Battery Voltage and Current BATTERY_FLOAT_VOLTAGE?
Measurement
(ADC Interrupt)
No Calculate and set
Charging Current
Yes Is battery voltage <

Priority: Medium BATTERY_VOLTAGE_MAX?
Set Minimum
No
AC Mains Detection Charging Current
(ADC Interrupt) Turn Charger
OFF
Priority: Medium Battery

Charger
Mode

AN1279
BATTERY CHARGER RESOURCE ALLOCATION
FIGURE 26: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR BATTERY CHARGER
VBAT
AC Input
+
Note 1
GND
KA(2) KB(2)
ADC ADC PWM
dsPIC33FJ16GS504
Note 1: The AC mains input is rectified by the body diodes of the IGBTs to provide a DC voltage to the battery charger.
2: KA and KB are feedback gain circuits. Refer to Appendix E: Schematics and Board Layout for details.
The dsPIC DSC device resources used for the battery

charger are summarized in Table 5.
TABLE 5: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR BATTERY CHARGER

Signal dsPIC DSC
Description Type of Signal Execution Rate/Frequency
Name Resource Used
IREF Charging current reference PWM output PWM4L 25 kHz
(remapped to pin 35)
IB Charging current feedback Analog Input AN4 6.25 kHz
UB Battery voltage feedback Analog Input AN5 6.25 kHz
EFB Flyback converter enable Digital Output RC7 Activated only when the UPS
switches to Battery Charger mode
Inverter Mode When starting Inverter mode, the push-pull converter is

ramped up to the rated DC Link voltage using a soft-
If the AC mains voltage is not detected, the battery start routine. The soft-start routine reduces stress on
charger is disabled and the Offline UPS switches to the system components and also prevents voltage and
Inverter mode. During Inverter mode, the system is current surges from the AC mains or the battery.
running on battery power and produces a clean
sinusoidal voltage at the UPS output so that critical During normal operation of Inverter mode, the push-
electronics can continue operation without interruption. pull converter and the full-bridge inverter are controlled
The sinusoidal output waveform is generated using a by interrupt-based power conversion algorithms, or
sine lookup table in the data memory. This lookup table control loops. The control loops are executed at a fast
serves as the sinusoidal reference voltage for the rate to achieve the best performance. The Inverter
inverter control loop. mode power conversion algorithms are the most critical
routines for the dsPIC DSC device; therefore, these
routines are assigned the highest user-priority level.

AN1279
The state machine, which is also interrupt-based, has a PUSH-PULL CONVERTER INITIALIZATION
lower priority than the control loops. As a result, the
When the system switches to Inverter mode, any previ-
execution of the state machine and user interface code
ous modes of operation must first be disabled. There-
may be interrupted numerous times by the high-priority
fore, the battery charger is first disabled by turning OFF
control loops.
the flyback converter and also by disabling the PWM
This operation is possible because the dsPIC DSC output for battery current reference. The output relay is
device allows for nesting of interrupts. The interrupt engaged to disconnect the AC mains input from the
nesting feature enables the control loops to interrupt UPS output, while the inverter series resistor is
the execution of the state machine. The state machine bypassed by switching ON the bypass relay. Then, the
execution is relatively slower than the control loops. push-pull converter control loop is reinitialized and all
The dsPIC DSC device allows for seamless transition control history is purged.
between the power conversion routines and the UPS
The AC mains input has a wide operating voltage
state machine, with the use of multiple interrupts of
range; therefore, the value of the DC link voltage is
differing priorities and execution rates.
unpredictable when a mains failure occurs. As a result,
When operating in the Inverter mode, all system vari- before turning ON the push-pull converter, the most
ables are monitored by the state machine. As soon as recently measured DC Link voltage is used as the initial
the AC mains voltage is detected, the switchover reference voltage for the push-pull converter. The soft-
sequence is engaged and the system state is changed start routine enables the DC Link voltage to be ramped
to Battery Charger mode. If any system variable is in up at a controlled rate and thus prevents unnecessary
error, the system state is changed to System Error. stress on the circuit components due to current spikes.
FIGURE 27: PUSH-PULL CONVERTER INITIALIZATION FLOWCHART
UPS State Machine
Push-pull Converter Initialization

Push-pull control loop
Priority: Medium
(ADC Interrupt)
Battery
System
Charger
Startup
Mode
Priority: High
Disable Battery Charger

Flyback Converter
(ADC Interrupt) Turn OFF PWM signal for
battery current reference
Priority: High Switch output relay to disconnect

Mains from UPS output
Bypass DC link charging resistor

Measurement
(ADC Interrupt) Re-initialize push-pull control
loop to purge history
Priority: Medium Set minimum duty cycle before

turning ON PWM outputs
Enable PWM outputs for push-pull

AC Mains Detection converter (PWM3H and PWM3L)
(ADC Interrupt)
Inverter
Priority: Medium Mode

AN1279
SOFT-START ROUTINE
The soft-start routine is called right after enabling the
push-pull converter. The soft-start routine increments
the reference voltage for the push-pull converter in soft-
ware in fixed steps until the reference reaches the rated
DC Link voltage. At this point, the inverter is enabled by
calling the inverter re-initialization routine to produce a
sinusoidal voltage at the UPS output.
The ramp rate for the DC Link voltage is fixed and the
starting voltage for the soft-start routine is variable,
making the soft-start duration also variable.
The variable duration of the soft-start routine may
cause uncertainty in the mains-to-inverter switchover
time. The ramp rate for the soft-start routine is
configured to be completed in the time required for the
output relay to turn ON. This ensures that the
switchover time is within the design specification of
10 ms.
However, the other situation must also be considered
where the soft-start is completed in less time. In this
case, the inverter output will turn ON before the relay is
given enough time to switch, thereby causing the
inverter output to be turned ON at the UPS output
midway through the sine wave cycle. If the relay is
turned ON after the completion of the soft-start, the
switchover timing would be too slow.
The dsPIC DSC avoids both of these problems by ini-
tializing a delay counter at the beginning of the soft-
start routine. As the soft-start routine is ramping up the
DC Link voltage, the counter is incremented to reflect
the soft-start duration in milliseconds. If the soft-start is
completed before the minimum required time for the
relay turn-on, the code continues to wait until the mini-
mum required switching time has elapsed. Once the
required relay switching time elapses, the full-bridge
inverter is enabled. This technique ensures that unin-
terrupted power is available at the UPS output at all
times.

AN1279
FIGURE 28: SOFT-START ROUTINE FLOWCHART
UPS State Machine
Push-pull Converter Initialization

Push-pull control loop Priority: Medium
(ADC Interrupt)
Start
Push-Pull
Soft-Start
Priority: High
Initialize delay counter

Set soft-start flag to allow higher
(ADC Interrupt) peak currents during startup
Priority: High Increment delay

counter
Increment push-pull
reference
Measurement No Is Push-pull converter
(ADC Interrupt) reference = final setpoint?
Yes
Priority: Medium
Increment delay
counter
AC Mains Detection No Does delay count represent

(ADC Interrupt) duration greater than relay
switching time?
Yes
Priority: Medium
Clear soft-start flag
Inverter
Mode

AN1279
FULL BRIDGE INVERTER INITIALIZATION The inverter control loop is reinitialized to purge all con-
trol history. The duty cycle is then configured to pro-
The push-pull soft-start routine ensures that the DC link
duce 0V output and the sine wave lookup table pointer
voltage is at the rated value and the output relay has
is also reset to the start. At this point, the PWM outputs
completed the switching event. After the soft-start
are enabled to produce the sinusoidal output voltage.
routine concludes, the full-bridge inverter must be
enabled to produce a sinusoidal voltage at the UPS
output.
FIGURE 29: INVERTER INITIALIZATION FLOWCHART
UPS State Machine
Inverter Initialization
Push-pull control loop
Priority: Medium
(ADC Interrupt)
Priority: High Inverter

Mode

(ADC Interrupt) Re-initialize inverter control loop to
purge all control history
Priority: High
Set duty cycle to produce 0V output

Measurement Reset sine wave lookup table
(ADC Interrupt) to the start
Enable PWM outputs to turn ON

Priority: Medium
inverter (PWM1H, PWM1L,
PWM2H and PWM2L)
AC Mains Detection
(ADC Interrupt)
Inverter
Mode
Priority: Medium

AN1279
PUSH-PULL CONTROL LOOP The voltage mode control algorithm must be executed
at a fast rate in order to achieve the best transient
The push-pull converter is controlled with a voltage
response. Therefore, the control algorithm is executed
mode control scheme. The PWM module in the dsPIC
in the ADC interrupt service routine, which is also
DSC device is configured for Push-Pull mode with an
assigned the highest priority in the UPS code.
independent time-base. The DC Link voltage is
measured by the ADC and converted to a digital value. A block diagram of the push-pull converter control
This value is subtracted from the voltage reference in scheme is shown in Figure 30.
software to obtain the voltage error.
The voltage error is then fed into a control algorithm
that produces a duty cycle value based on the voltage
error, previous error, and control history. The output of
the control algorithm is also clamped to minimum and
maximum duty cycle values for hardware protection.
FIGURE 30: PUSH-PULL CONVERTER CONTROL SCHEME
1:16
Voltage Control Duty
VREF Error Output Cycle + VOUT
X PID
VIN
PWM +
+-
1001010111
Voltage Feedback
ADC S&H

AN1279
INVERTER CONTROL LOOP In the Offline UPS, a 3-level control is implemented for
the full-bridge inverter. So the PWM module in the
The inverter output is generated by varying the voltage
dsPIC DSC device is set up with a fixed duty cycle for
reference using a sinusoidal lookup table. The mea-
zero output voltage. Each leg of the full-bridge inverter
sured output voltage is subtracted from the present ref-
is operated in complementary Center-Aligned mode
erence value and the voltage error is obtained. The
with dead time. The result of the control loop is added
voltage error is fed into the voltage error compensation
to the nominal duty cycle for one leg of the full-bridge
algorithm within the ADC interrupt service routine. The
inverter and subtracted from the nominal duty cycle for
output of the voltage error compensator produces the
the second leg.
current reference value. The measured output current
is subtracted from the current reference to obtain the A block diagram of the full-bridge inverter control
current error. The current error is used as the input to system is shown in Figure 31.
the current error compensation algorithm to produce
the command signal for the PWM module.
FIGURE 31: FULL-BRIDGE INVERTER CONTROL SCHEME
Current
Sinusoidal Reference Reference Current Duty
Voltage Control AC Out
Error Cycle
Error Output
X PI X P
PWM
+ -
+ -
Output Filter
Current
Feedback
S&H
1011010011
1001010111
Voltage Feedback
ADC
S&H

AN1279
PUSH-PULL CONVERTER HARDWARE AND
SOFTWARE RESOURCE ALLOCATION
FIGURE 32: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR PUSH-PULL CONVERTER
VDC
Push-Pull Converter
VBAT +
GND
GND
FET FET
Driver Driver kD kC
PWM PWM ADC ADC

or
Analog Comparator
kE
dsPIC33FJ16GS504
ADC
The dsPIC DSC resources used for the push-pull

converter are summarized in Table 6.
TABLE 6: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR PUSH-PULL CONVERTER

Signal dsPIC DSC Sample Rate/
Description Type of Signal
Name Resource Used Frequency
S1 Push-Pull Drive Signal PWM Output PWM3L 100 kHz
S2 Push-Pull Drive Signal PWM Output PWM3H 100 kHz
IP Push-Pull Primary Analog Input AN2 25 kHz
Current Feedback
UDCM DC Link Voltage Analog Input AN3 25 kHz
Feedback

AN1279
FIGURE 33: dsPIC DSC RESOURCE ALLOCATION FOR FULL-BRIDGE INVERTER
VDC Full-Bridge Inverter
VOUT+
VOUT-
GND
IGBT IGBT IGBT IGBT

Driver Driver Driver Driver kF kG
PWM PWM PWM PWM
ADC
dsPIC33FJ16GS504
ADC
The dsPIC DSC device resources used for the full-bridge

converter are summarized in Table 7.
TABLE 7: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR FULL-BRIDGE CONVERTER

Signal dsPIC DSC Sample Rate/
Description Type of Signal
Name Resource Used Frequency
S3 Inverter Drive Signal PWM Output PWM1L 50 kHz
S4 Inverter Drive Signal PWM Output PWM1H 50 kHz
S5 Inverter Drive Signal PWM Output PWM2L 50 kHz
S6 Inverter Drive Signal PWM Output PWM2H 50 kHz
I Inverter Output Current Analog Input AN0 25 kHz
Feedback
ACO Inverter Output Voltage Analog Input AN1 25 kHz
Feedback
ACI AC Mains Voltage Analog Input AN11 25 kHz
Feedback
A1 Resistor Bypass Relay Digital Output RC10 Activated only at startup
Drive Signal to charge the DC Link
voltage above the
minimum value.
A2 Output Relay Drive Digital Output RC0 Activated only when the
Signal UPS switches to
Inverter mode.

AN1279
Inverter-to-Mains Switchover Routine The state machine then begins the process of
switching from Inverter mode to Battery Charger mode.
When a power failure occurs, the Offline UPS switches The switchover is engaged at the zero-crossing of both
to the Inverter mode and operates in this mode until the the inverter and mains. This provides the smoothest
mains is detected again. The system should switch transition from one mode to the other and occurs
from one mode to the other in the shortest possible instantaneously.
duration in order to provide uninterrupted power to the
load. It is possible that the inverter and mains are out of
phase when AC mains is available again. As the fre-
Before switching to the Battery Charger mode, the soft- quencies of the AC mains and the inverter are nearly
ware must reliably ensure that the mains voltage equal, the zero crossings of the two waveforms may
detected is within the specified levels. The software never align. Therefore, the UPS software first checks
must also ensure that the mains waveform is clean and whether the frequencies are very close. If there is a sig-
has little or no distortion. nificant difference in frequencies, the two waveforms
The mains detection routine is divided into the following will eventually align at the zero crossings, which is
steps: when the UPS will engage the switchover.
1. Mains High Voltage Detection: In the Inverter If the two signals are operating at nearly the same fre-
mode, the UPS software first checks for the quency, the inverter frequency is modified slightly by
presence of high voltage on the mains. If a high discarding some of the samples from the lookup table.
voltage is detected consecutively for 5 ms, the As a result, the zero crossings of the two signals are
mains detection routine proceeds to the next forced to align after a few sine wave cycles. This allows
step. the UPS state machine to switch from the Inverter
2. Zero-Crossing Detection: After a high voltage mode to the Battery Charger mode with almost zero
has been detected, the software keeps polling latency. The inverter-to-mains switchover sequence is
the mains voltage for a zero-crossing detection. described graphically in Figure 34.
A valid zero-crossing is only detected if the pre- It is also important to note that the alignment of the zero
vious voltage is negative and the present volt- crossings must be predicted using information for the
age is positive, and the difference between the relay switching time. The relay is switched a few milli-
previous and present measurement is above a seconds before the actual zero-crossing so that the
minimum value. This ensures that spurious relay switching delay is accounted for.
zero-crossings are not detected due to noise.
3. Mains Data Collection: Once the zero-crossing
has been detected, the UPS software enters the
mains data collection step. In this step, every
sample of the measured mains voltage is stored
in an array. Each sample of the collected data is
averaged over four sine wave cycles to ensure
an accurate reference. This array is later used
as the mains reference to detect a mains failure.
4. Mains Synchronization: After collecting the
mains voltage data, the mains detection routine
now compares the measured voltage with the
mains reference data. If the error is within 20V
consecutively for 8 ms, the software concludes
that the mains is present and indicates the new
state of the AC mains to the state machine.

AN1279
FIGURE 34: INVERTER-TO-MAINS SWITCHOVER SEQUENCE
High Voltage Detected Zero-crossing Detected Start Mains Data Mains Data Collection Zero-crossing Aligned
Collection Complete
AC
Mains
Inverter
Inverter turned
OFF
Inverter
Frequency
Modified

AN1279
Mains-to-Inverter Switchover Routine UPS output. The push-pull converter is then enabled
and the soft-start routine is executed. After the soft-
When mains is present, the UPS software keeps com- start routine is complete, the mains voltage is
paring the measured mains voltage with the corre- measured again.
sponding data in the mains reference array. The
quadrant information is also saved in a variable. On Using a binary search algorithm, the appropriate sam-
every sample, the error between the expected voltage ple number from the sine lookup table is selected,
and the actual voltage is calculated. which is in the appropriate quadrant and has a value
closest to the mains voltage. The inverter is then
If the error is detected to be larger than 20V, a count enabled starting at this sample number so that there is
is incremented. If the error is detected to be outside the no sudden change in voltage on the UPS output. The
limit consecutively for about 1 ms, then the Offline UPS mains-to-inverter switchover sequence is described in
detects that a mains failure has occurred. The system Figure 35.
state is changed to Inverter mode and the relay is
switched immediately to disconnect the mains from the
FIGURE 35: MAINS-TO-INVERTER SWITCHOVER SEQUENCE
Mains Failure
detected
Push-pull Soft-start
Routine Completed
Mains Failure
Occurred Inverter turned ON
at the last measured
mains voltage
UPS
Output
Battery
Charger
Mode (AC Inverter Mode
Mains
Present)
DC
Link
Voltage

AN1279
System Error The DSP instructions of the dsPIC DSC device are uti-
lized to efficiently execute the RMS calculation rou-
The UPS goes into the System Error state if a combi- tines. The Q15 library includes functions for calculating
nation of the system variables is detected to be in a sum-of-squares and square-root. Both of these opera-
fault state. The state diagram in Figure 21 illustrates all tions are available in the Q15 library, and are used for
conditions under which a system error is detected. implementing the RMS calculation in the offline UPS
The dsPIC DSC device has built-in fault and current reference design.
limit features that enable automatic shutdown of power The RMS calculation is called in the idle loop since it is
converters with no software overhead. This feature is executed over the AC mains cycle, and therefore,
critical in power conversion applications and is useful in requires a relatively slow execution rate. The results
protecting the user, system hardware, and downstream are then scaled appropriately to produce a number in
electronics. volts or amperes.
The System Error mode is designed to handle any In order to display the result on the LCD display, each
faults after the respective power stage has been dis- decimal digit of the RMS calculation result is stored as
abled. When the system enters this mode, the type of a character variable. The character variables are then
fault is displayed on the LCD module. When the UPS concatenated into a string in order to display the data
enters the System Error mode, the system needs to be on the LCD module.
restarted again before it can function normally.
LCD DISPLAY
Auxiliary Tasks The LCD control code for the dsPIC DSC device is
All non-critical functions of the Offline UPS are catego- implemented as independent functions for writing pix-
rized as auxiliary tasks. These tasks have a relatively els, bytes, words, or strings to the LCD module. The
slow execution rate and therefore are assigned the LCD display routines are called in the main loop.
lowest execution priority in the Offline UPS software. The Offline UPS Reference Design uses a 4x20 char-
The auxiliary tasks are executed in the main loop of the acter LCD display module controlled by a dedicated
code. These tasks are performed only when other high- MCU (PIC18F2420). The dsPIC DSC device communi-
priority tasks like power conversion control loops and cates with the LCD controller via a Serial Peripheral
the UPS state machine are not active. In other words, Interface (SPI).
the auxiliary tasks are performed during the idle time The dsPIC DSC device is configured as the SPI master
for the power conversion routines and state machine. device and transmits all LCD commands to the LCD
As a result, the main loop is also referred to as the idle controller. The LCD controller converts the serial
loop. The auxiliary tasks are numerously interrupted commands from the dsPIC DSC device into parallel
by high-priority tasks like the control loops and the state data and also manages the timing controls for the LCD
machine. Each of the auxiliary tasks is described briefly module.
in the following sections.
Note: Operation of the LCD controller is beyond
OUTPUT VOLTAGE/CURRENT RMS the scope of this reference design. Visit
www.microchip.com/lcd for LCD design
CALCULATION
solutions.
The RMS Calculation routine provides the output
voltage and current information for the LCD display The LCD controller operates with a 5V supply and the
as well as for output overcurrent and output dsPIC DSC operates on a 3.3V supply. However direct
overvoltage/undervoltage protection. connections between the dsPIC DSC and LCD control-
ler can be made because the digital-only pins of the
The measured current and voltage are stored in data dsPIC DSC are 5V tolerant. Also the digital outputs of
memory in an array of 256 points each. When the RMS the dsPIC DSC can be operated in open-drain configu-
calculation routine is called, the respective array is ration and produce logic high for the 5V LCD controller
passed to the function, while the output of the function using just a pull-up resistor.
is the true RMS value of the parameter.
The resource allocation for LCD control is summarized
in Table 8.
TABLE 8: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR LCD DISPLAY

Signal dsPIC DSC
Description Type of Signal Sample Rate/Frequency
Name Resource Used
SDO SPI Data Output Digital Output RP22 156.25 kHz when active
SDI SPI Data Input Digital Input RP19 156.25 kHz when active
SCK SPI Clock Output Digital Output RP21 156.25 kHz when active
SS SPI Slave Select Digital Output RP20 Asserted only when data is
Output transmitted to LCD controller

AN1279
USB COMMUNICATION The resource allocation for the USB communication
interface is summarized in Table 9.
The Offline UPS also includes a USB communication
interface to enable power management for a computer
or server connected to the UPS. The USB communica-
tion is performed by a separate USB controller MCU
(PIC18F2450). The USB controller communicates with
the dsPIC DSC device via an opto-isolated UART
interface.
TABLE 9: dsPIC DSC DEVICE RESOURCE ALLOCATION FOR USB INTERFACE

Signal dsPIC DSC
Description Type of Signal Sample Rate/Frequency
Name Resource Used
TX UART Transmit Digital Output RP27 9600 bps
RX UART Receive Digital Input RP28 9600 bps

AN1279
Fault States and Protection Schemes Operation with Rectifier Loads
There are a number of fault sources that can cause the One of the most important applications of the Offline
system to turn off all outputs and enter the System UPS is to provide uninterrupted power to computers
Error mode. Any system fault can trigger the Offline and servers. Most computers and servers implement a
UPS to enter the System Error mode. These include switch-mode AC-DC power supply that implements
the following: Power Factor Correction (PFC). Such a load usually
Push-pull primary overcurrent contains a front-end bridge rectifier and is therefore
classified as a rectifier load.
DC Link undervoltage
DC Link overvoltage If PFC is not implemented, the load appears as a highly
capacitive load, resulting in high peak currents and a
Battery undervoltage
low power factor. A block diagram of the connections
Battery overvoltage for such a configuration is shown in Figure 36.
Output overcurrent
The typical configuration of such a power supply con-
Overtemperature tains a PFC boost converter as shown in Figure 37.
The system will enter the System Error mode due to The boost converter usually contains a large output
either a single fault or a combination of faults, capacitor. As seen from the circuit diagram, a low
depending on the operating modes. For example, a DC impedance path exists from the AC input to the output
Link undervoltage condition will not cause the system capacitor. As a result, the output capacitor draws a
to enter the System Error mode if the soft-start routine large inrush current when the load is first connected to
is active. Similarly, transient loads may cause the push- the UPS output.
pull primary current to exceed the limit for a short
duration. Therefore, a push-pull overcurrent fault will
only be generated if the overcurrent condition persists
for an extended duration.
All faults that are fast-acting and destructive to the sys-
tem and users load are handled in the high-priority
control loops. The push-pull overcurrent fault is an
example of a very high-speed signal that must be
detected as soon as possible. As a result, this fault is
detected at the same time as the push-pull control loop.
Other signals like the battery voltage are not very high-
speed signals and therefore the faults are handled in
the UPS state machine.
When a fault condition happens, the system enters the
System Error mode and the type of fault is displayed on
the LCD module.
FIGURE 36: TYPICAL RECTIFIER LOAD FOR THE OFFLINE UPS
Computer/Server Power Supply
UPS AC PFC Boost DC-DC

AC Offline UPS EMI Filter Converter Converter
Output Input

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FIGURE 37: PFC BOOST CONVERTER
AC
Load
If PFC is not implemented, the current is drawn by the

load in a very discontinuous nature with high peaks,
causing the load to appear highly capacitive, as shown
in Figure 38.
FIGURE 38: RECTIFIER LOAD INPUT CURRENT WAVEFORMS (NO PFC)
Diode Diode Diode Diode

ON ON ON ON
Diode Diode Diode
OFF OFF OFF
Input Voltage
Output Voltage
Input Current

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Due to the presence of a large capacitor on the output Peak Current Limiting Function
of the PFC boost converter, the Offline UPS needs to
implement a special algorithm to handle load steps and If the power factor of the rectifier load is too low, it will
startup conditions for rectifier loads. result in a high crest factor for the inverter current. The
Offline UPS Reference Design is rated for a maximum
The current draw during a rectifier load startup can be crest factor of 3:1. If the crest factor of the load exceeds
up to 20 times the maximum rated current. One option this value, no action is taken by the UPS if the current
to support these high current surges is to design the is within the maximum peak current rating. However, a
hardware with sufficient design margin. However, this high crest factor warning is displayed on the LCD
approach is usually not cost effective and may also display module.
cause a drop in performance or efficiency. The dsPIC
DSC provides a number of flexible features to over- If the peak current required by the load exceeds 15A, a
come this problem. The PWM Current-Limit feature can current limiting function overrides the inverter control
be used to limit the current on a cycle-by-cycle basis. loop. This function limits the maximum current on the
This feature, along with software can help charge the output by clamping the duty cycle to a maximum value.
output capacitor in a controlled manner so that the
inrush current is limited. DC Offset Elimination
In the Offline UPS Reference Design, an external inter- A side-effect of operating with a high crest factor is that
rupt is generated when an overcurrent condition the current drawn may become asymmetric. This is
occurs. This causes the PWM module to automatically caused by the presence of a small DC offset on the
shut down. Inside the Interrupt Service Routine, the inverter output voltage. The DC offset occurs due to the
PWM is configured for a very small duty cycle and then tolerance limits of the feedback components.
re-enabled. As the duty cycle is small, the current
A typical analog implementation requires the use of
drawn during one PWM switching cycle is automatically
trimming resistors to eliminate the DC offset. This
limited. The duty cycle is incremented in small steps to
solution requires trimming of each UPS system during
charge the output capacitor in a controlled manner.
manufacturing, and therefore becomes expensive and
While the current-limit fault handling routine is being
time consuming. It may also need periodic adjustment
executed, the inverter control loop is overridden. The
via a servicing schedule to account for effects of long
inverter control loop resumes operation when the sine
term degradation of components. The dsPIC DSC
voltage reference of the inverter becomes equal to the
helps overcome this problem with an active algorithm
actual voltage on the inverter output.
to eliminate the DC offset.
If the first current limit fault is caused by a short circuit
The Offline UPS Reference Design implements an off-
condition on the inverter output, the current limit fault
set elimination routine by comparing the positive and
will be triggered immediately for a second time. This
negative peak of the measured output voltage. If an
will cause the system to shut down with an overcurrent
imbalance is detected, a correction factor is applied to
error. The error state is displayed on the LCD display
the output voltage to cancel the DC offset. The peaks
module and is reset only when the system is turned
are determined by averaging the maximum and mini-
OFF and back ON.
mum recorded voltages over a number of sine wave
cycles. Doing so helps to ignore the effects of load
steps on the output.

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HARDWARE DESIGN TOPOLOGIES CONSIDERED AND REASONS
FOR CURRENT CHOICES
Push-Pull Boost Converter In Figure 39 and Figure 40 all possible push-pull boost
circuits are shown. The combination of a push-pull
DESIGN SPECIFICATIONS inverter (Figure 39(C)) and a full-bridge rectifier
A push-pull boost converter needs to convert the wide (Figure 40(B)) was chosen, which provides the best
range battery link input voltage to a stabilized high-volt- price performance ratio. For the inverter only the low-
age DC-Link. The design specifications used in the side drive circuitry is required and simple PWM signals
Offline UPS Reference Design are: (see Figure 41) can drive the inverter.
Input voltage range: 30-45 VDC

Output voltage: 380 VDC
Continuous power: 1 kVA
Peak power for two seconds: 1.3 kVA
Switching frequency: 100 kHz
FIGURE 39: PRIMARY DRIVE CIRCUITS
Q1 Q2
C1
UB T1
+
(A) Full-Bridge Inverter
Q3 Q4
Q1 C1
(B) Half-Bridge Inverter UB T1

+
C2
Q3
T1
UB +
(C) Push-Pull Inverter
Q Q

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FIGURE 40: RECTIFIER CIRCUITS
T1
L1
(A) Half-Bridge Rectifier

R1
C1
D1 D2
L1
D3 D4
T1
(B) Full-Bridge Rectifier
C1 R1
D1 D2
FIGURE 41: CONTROL SIGNALS FOR The output voltage is calculated by Equation 6, where
PUSH-PULL INVERTER N2 N1 is the transformer windings ratio, and d is the
duty cycle of the PWM signal. The duty cycle must be
limited to the given boundary. In a real application, the
duty cycle must be limited to 0.1 < d < 0.42. This is
done due to the switching behavior of the MOSFETs
and transformer. Due to allowed oscillation and losses
in the system, the calculation using Equation 6 is not
exact. When no load is applied to the push-pull boost
stage, the controller has to switch into Burst mode, and
when heavy load is applied, the duty cycle must be
increased to compensate for various losses.
EQUATION 6:
N2
For the secondary, a full-bridge rectifier was chosen for U DC = U BAT ------ 2d
N1
the following reasons:
where:
Reducing the leakage inductance by using only d is the duty cycle of the transistors and 0 < d < 0.5
one secondary winding on the transformer
N2/N1 is the secondary-to-primary turns ratio of
Reducing cost of transformer the transformer
Rectifier diodes can be rated lower in reverse
breakdown voltage, such diodes have better
forward and switching characteristics.
Synchronous rectification is not required due to
high-voltage and low current operation.

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DESIGN OF POWER-TRAIN COMPONENTS from FERROXCUBE was selected. From core loss,
maximum flux density can be calculated, as shown in
The push-pull transformer has been designed using a
Equation 7. The factors used in this equation are
ferrite magnetic core. The transformer design is based
provided in Table 10.
using the area product (WaAc) approach and is
designed to meet the following conditions:
EQUATION 7:
Minimum input voltage: Vimin = 30V
Maximum DC link voltage: Vo = 380V c d
P l = a f B max
Maximum output power: Pomax = 2000W
Primary RMS current: IPrms = 30.5A
Core loss density is normally selected around 150 mW/
Maximum duty cycle: Dmax = 0.42
cm3. The calculated maximum flux density must be lim-
Switching frequency: f = 100 kHz ited to less than half of B at saturation. This B level is
The manufacturers data sheet is used to help select chosen because the transformer core will develop
the appropriate material for the desired application. For excessive temperature rise at this frequency when the
the given range of materials, frequency, core loss, and flux density is close to saturation. Maximum flux density
maximum flux density of the material should be can now be calculated, as shown in Equation 8.
considered. From the research data, 3C90 material
TABLE 10: FACTORS APPLIED TO Equation 7 (CORE LOSS EQUATION)

Material Frequency a c d
R, 35G, N87, 3C90 f < 100 kHz 0.074 1.43 2.85
100 kHz f < 500 kHz 0.036 1.64 2.68
f 500 kHz 0.014 1.84 2.28
P, 45G, N72, 3C85 f < 100 kHz 0.158 1.36 2.86
100 kHz f < 500 kHz 0.0434 1.63 2.62
f 500 kHz 7.36e-7 3.47 2.54
F, 25G, N41, 3C81 f < 10 kHz 0.790 1.06 2.85
10 kHz f < 100 kHz 0.0717 1.72 2.66
100 kHz f < 500 kHz 0.0573 1.66 2.68
f 500 kHz 0.0126 1.88 2.29
EQUATION 8:
1000 1000
-----------
d
- -----------
2.68
-
Pl 150
B max = ------------------------------c = ---------------------------------------------------
1.64
- = 1339G
a ----------- f - 0.036 100000 ------------------
1000 1000

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For selecting the right size core, the area product of the FIGURE 42: HYSTERESIS LOOP OF
core must be calculated by Equation 9. This equation is MAGNETIC CORE
derived from the flux linkage equation ( = N * ) and
represents the power handling ability of the core. B
Therefore, each core has a number that is a product of
its window area, Wa, and the core cross-sectional area,
Ac. BSAT
EQUATION 9: BMAX
8
10 P omax
W a A c = --------------------------------------
-
K t B f J B
B
H
B in Equation 9 is equal to 2Bmax due to bidirectional
core excitation as seen in Figure 42. Current density of
B
a winding is estimated to be 500A/cm2, and maximum
output power Pomax is 2000W. Therefore, the calculated
area product is shown in Equation 10. BMAX
EQUATION 10:
8 BSAT
10 2000 4
W a A c = -------------------------------------------------------------------------
- = 5.9cm
0.254 2678 100000 500
The selected core must have an area product larger

than calculated. ETD54 shape and size of a core was
selected with WaAc = 12.6 cm2. A larger size was
selected due to the primary and secondary windings,
which fit to the winding area of that core.
The primary turns are calculated by Equation 11. Given
result is then rounded up or down to the integer value.
In this case it is rounded to 4 turns for one-half of the
primary.
EQUATION 11:
2 2
10 V imin --- D max 10 8 30 ------------------ 0.42
8
f 100000
NP = ----------------------------------------------------------------- = ---------------------------------------------------------------------- = 3.4
B A C 2678 2.8

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The secondary turns are calculated by Equation 12. not be much higher due to the short winding. Primary
The result is rounded to the value 60 of secondary RMS current is IPrms = 30.5A. Secondary current can be
turns. calculated by Isrms = IPrms * Np Ns = 2.03A.
EQUATION 12: EQUATION 13:

Vo I Prms 2
---------------- 380 A cuP = ------------
- = 3.81mm
2D max -------------------- JP
2 0.42
N s = ---------------- N p = --------------------- 4 = 60.3
V imin 30
I Srms 2
A cuS = -----------
- = 0.41mm
JS
The cross section of the primary and secondary wind-
ings is calculated by Equation 13. Different current den-
Because of the high switching frequency, f = 100 kHz,
sities are used (JP = 8A/mm2 and JS = 5A/mm2) to fit the
litz wire must be selected to reduce winding
windings into the transformer bobbin and because the
losses (losses by skin and proximity effect). Litz wire
length of one-half of the primary is very short compared
must also be designed for that frequency.
to the secondary. In that case, it is allowed to use higher
current density for primary as temperature of winding will Figure 43 shows the transformer winding diagram and
construction diagram.
FIGURE 43: TRANSFORMER ELECTRICAL AND MECHANICAL CONSTRUCTION
NS
NP
NP NP
NS
Bobbin CORE Insulation and Shield
NP
NP NP
NS

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PUSH-PULL MOSFETS EQUATION 17:
When choosing the right MOSFETs the following must
be considered: U DC N 2
d=
Maximum Breakdown Voltage 2 U bat N1
Continuous Current
Peak Current When we use a transformer with windings ratio of 16
Package Thermal Performance the peak current is that of Equation 18:
Maximum Breakdown Voltage EQUATION 18:

In the chosen configuration, a MOSFET must be able
to hold more than twice the battery voltage, as 2000W
I pm = = 160.3 A
expressed in Equation 14. In this calculation, a safety 30V 0.416
factor of 30% overrating was chosen. Therefore, the
selected devices need to have a drain-to-source
Therefore, we have to design the MOSFETs for contin-
breakdown voltage higher than 117V.
uous drain current of 16.67A and peak drain current of
160.3A. Because the waveform shape will not be an
EQUATION 14: exact sawtooth, these calculations are only an esti-
mate. To be on the safe side, these numbers are
VBRDSS > 2VBAT increased by 30%.
2 45V 1.3 = 117V
Package Thermal Performance
To design the thermal performance, the rms current
Continuous Current
value must be calculated. If the waveform shape and
To calculate the current rating of the devices, peak and peak current are known, the rms can be calculated
average currents have to be estimated. The peak and using Equation 19.
average currents can be estimated from the power rat-
ings and input voltage. The average current is calcu- EQUATION 19:
lated using Equation 15, where PC is the continuous
power and UBAT is the battery voltage.
d
I rms = I pc
EQUATION 15: 3
I a = Pc / U bat The rms current can now be calculated and is shown in

Equation 20:
The highest current will flow at the lowest battery EQUATION 20:
voltage so the continuous current is:
I = 1000W 30V = 33.34A. And per leg, the continuous 2
drain current is half of this: ID = 16.67A. I rms = 80.15 .416 = 42.13 A
3
Peak Current
Per leg, the current is half of this: IDRMS = 21.07A. This
The peak current must be calculated at maximum
is the most critical design consideration; therefore, an
power and the form of the current waveform must also
be taken into account. When we assume that the cur- overrating of 50% should be done IDRMS = 21.07A * 1.5
= 31.5A, and all current leading traces and the
rent waveform will have a sawtooth waveform with the
transformer should also be rated for this current.
given duty cycle (d), we can calculate the resulting
peak current using Equation 16. The duty cycle (d) is The conductive losses on the MOSFETs are calculated
calculated using Equation 17. using Equation 21.

2
I pm =
Pmax Pc = I Drms RDSon
U bat d

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For a switching frequency of 100 kHz and with the A typical transformer in this range should have not
push-pull configuration also switching, losses have to more than L = 0.5 H of leakage inductance.
be taken into account. If the current waveform is near Therefore, the turn-off power would be that of
sawtooth, turn-on losses can be neglected. Turn-off Equation 24:
losses depend on the peak current and leakage induc-
tance. To limit the voltage spikes at turn-off a voltage EQUATION 24:
clamp circuit is used. This circuit enables the MOS-
FETs to operate without RC snubbers. Snubbers are 1.6e 3
only used to suppress high frequency oscillation, and Poff = 100e3 = 40W
not to dissipate the energy stored in the leakage induc- 4
tance of the transformer. Therefore, all of the energy is
dissipated on the MOSFETs. Equation 22 can be used Total dissipation on the MOSFETs is then Ptot = Poff +
to estimate the power dissipation at turn-off. PC, and it is estimated to be 55W per leg.
Now the MOSFETs can be selected. In the reference
EQUATION 22: design, a TO-220 package is used for the MOSFETs.
Typical junction-to-heat sink thermal resistance of
WL
Poff = f SW these devices is Rt = 2.5C/W when using silicone
4 pad insulation.
We will allow a continuous junction temperature of
In Equation 22, WL is the energy stored in the leakage 110C and a heat sink temperature of 60C. From this
inductance at turn-off and is calculated using and the power dissipation, we can calculate the needed
Equation 23. thermal resistance, which provides the number of
parallel MOSFETs to use.
EQUATION 23: The number of necessary devices is calculated as
2 n = Rt RJH = 2.7. According to the calculation
i L shown in Equation 25, three parallel FDP2532 devices
WL =
2 from Fairchild Semiconductor were selected.
EQUATION 25:
50
RJH = = = 0.91C / W
Ptot 55

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FULL-WAVE RECTIFIER
FIGURE 44: RECTIFIERS WITH CURRENT FLOW
L1
D3 D4
T1
C1 R1
(A) D3 and D2 Conduct
D1 D2
L1
D3 D4
T1
(B) D1 and D4 Conduct C1 R1
D1 D2
When selecting diodes, the following must be Average Forward Current

considered:
Average forward current per leg is easily calculated
Diode Breakdown Voltage using Equation 26 from the desired DC link voltage and
Average Forward Current continuous output power.
Peak Forward Current
Switching Characteristics EQUATION 26:
Package Thermal Performance Pc 1000
I avg = = = 2.6 A
Diode Breakdown Voltage VDC 380
The transformer secondary voltage is calculated as
VS = VBAT * N2 N1. The maximum secondary voltage Peak Forward Current
at the highest battery voltage is VS = 45 * 16 = 720V.
Because of transformer leakage inductance, diode Peak current is calculated using the transformer
internal inductance, and DC link inductor inductance, current ratio and peak MOSFET current previously
voltage spikes appear on diodes when switching. Due calculated in Equation 9.
to this, the calculated breakdown voltage is increased
by 30% and should be more than 936V. EQUATION 27:
N1
I pD = I P = 160.3 0.625 = 10 A
N2

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Switching Characteristics
Diode switching characteristics are determined by
forward recovery time and reverse recovery time.
FIGURE 45: DIODE SWITCHING CHARACTERISTICS
i[A] tfr t
u[V]
i
PDon PDoff
t1 t2 t3 t[s]
Diode switching loss can be estimated using Total power loss is estimated by adding conduction
Equation 28. losses and switching losses, as shown in Equation 29.
PswD = Qc VDC f SW Ptot = PswD + PfD = 10W
Package Thermal Performance The estimation shows that the power losses are within
For diodes, an isolated TO-220-2 package is used. the set criteria.
Continuous working junction temperature should not
exceed 130C at a heat sink temperature of 60C. Typ-
Output Inductor
ical thermal junction-to-heat sink resistance of the junc- This inductor is optional and is not required. Its use
tion-isolated TO-220-2 package is Rt = 3.5C/W. depends on the transformer construction and control of
Therefore, the maximum allowed power dissipation per DC-link voltage, and the inductor value that must be
part is PMAX = 70 3.5 = 20W. used. This section describes the design of a 50 H
The STTH1210DI from STMicroelectronics meets the output inductor.
voltage and current requirements. Power loss calculation The design of the output inductor uses the area product
can be determined by consulting the diode data sheet. approach with the following conditions:
Inductance: L = 50 H
Peak DC current: Ip = 13A
Operating flux density: Bm = 300 mT
Current density: J = 500 A/cm2
Window utilization: Ku = 0.4
First, the energy handling capability must be calculated
by Equation 30.

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L I p2 LIp
50 106 132 Bnew = = 308mT
E= = = 0.0043Ws N Ac
2 2
Then, to select the appropriate size of ferrite core, the The 3C81 material has a saturation point at 320 mT
area product calculation must be done, as shown in (100oC).
Equation 31. If the criteria are not fulfilled, different material, air gap,
number of turns, or even a bigger core must be
EQUATION 31: selected.
The cross-section of a wire is calculated by
2 E 104 Equation 35, where RMS current through the inductor
Wa Ac = = 1.43cm 4
Bm J K u is calculated from primary RMS current of push-pull
transformer and turns ratio. This current is twice as
large as primary because for half of a switching period,
The selected core was the P36/22 pot core from FER- the first primary winding is conducting and in the other
ROXCUBE due to its small size and shape, which pro- half, the second primary winding.
duces less interference into surrounding components.
The area product of this core is 1.46 cm4 and can be EQUATION 35:
calculated from the data in the manufacturers data
sheet. NP
2 I Prms
The number of turns required to get the desired I rms NS
inductance of the coil is calculated by Equation 32. The Acu = = = 0.82mm 2
Core cross section Ac = 172 mm2 is obtained from the
J J
manufacturers data sheet. The calculated value is the minimum cross-section of a
wire (100 kHz litz wire must be used).
EQUATION 32:
Next, the fill factor must be calculated by Equation 36.
LIp This provides an estimation of whether the winding fits
N= = 12.6 into the bobbin. The fill factor must be 0.4 or less.
Ac Bm Wb is the bobbin winding area and is 72.4 mm2, and
can be found in the core data sheet.
The calculated number of turns is then rounded to the
nearest integer value, which is 13. EQUATION 36:
To get the desired inductance, 3C81 material with an N Acu
air gap was selected to control the flux density. If an air Ku = = 0.15
gap is distributed into the magnetic path of the core, the Wb
effective permeability of material changes and induc-
tance factor AL. From the AL value and number of turns,
the inductance is calculated by Equation 33. The AL Output Capacitors
value is obtained from the material data sheet and is
When choosing DC-link capacitors, the following must
315 nH at 0.97 mm air gap.
be considered:
EQUATION 33: Voltage Rating

Ripple Current
L = N 2 AL = 53 H Voltage Rating
The voltage rating is defined by the DC Link voltage:
VDC = 380V. Therefore, the capacitors must be above
The new operating flux density is verified by this rating.
Equation 34 and must be lower than the saturation
point of the selected material.

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Ripple Current EQUATION 39:
When the DC link voltage controller is working as 1
expected, the low frequency ripple current caused by f = = 2.7 MHz
the inverter is negligible. Therefore, the capacitors 2 CDS LS
need only compensate for the reactive load current,
which depends on the device specifications:
Damping of the system is very low because of the low
S = 1300VA and P = 1000W.
primary winding resistance (RS) and the series
resistance of the battery link capacitors (RC), which are
EQUATION 37: both in the range of milliohms. To reduce this high
frequency ringing, a series RC snubbers were added
Q = S 2 P 2 = 830.7Var across the primary winding. The capacitance should be
one to three times the capacitance of the MOSFETs,
and the series resistor value should be chosen so that
EQUATION 38: it grants damping and the power dissipation is within
the resistor rating. To maintain high efficiency of the
Q 830.7 system we allow less than 1% of the rated power to be
Ir = = = 3.6 A dissipated on the primary snubbers. The final values of
VAC 230 the RC snubber are evaluated by experimenting and
are C = 10 nF and R = 12. The power rating of the
SNUBBERS resistors is 4W.
Snubbers are used to dampen high frequency oscilla- To design the snubbers for the rectifier diodes, the
tion and reduce ringing losses on diodes. Snubbers on capacitance of the rectifier diode must be known. The
the primary side are placed across the primary wind- simplified high frequency circuit is shown in Figure 47.
ings and are not used to handle voltage spikes at turn-
off of the MOSFETs. They only reduce ringing and FIGURE 47: HIGH-FREQUENCY CIRCUIT
transformer in-rush current.
To design the snubber for the primary side, the CD1 L1
LSS
capacitance of the MOSFETs and leakage inductance
of the transformer must be known. Both parameters
can be measured; however, MOSFET capacitance is CD3
voltage dependent so only an estimate can be used. In
our case, the capacitance of three parallel MOSFETs is
approximately CDS = 7 nF, and leakage inductance of
the transformer is estimated at LS = 500 nH. A Here, the capacitor should be in the range from two to
simplified high frequency circuit is shown in Figure 46. five times the capacitance of the diode. The diode
capacitance can be found in the diode data sheet. For
FIGURE 46: HIGH-FREQUENCY CIRCUIT the selected diodes it is approximately CD = 70 pF.
Therefore, a good starting capacitance value for the
snubber is C = 150 pF. Here we will also limit the max-
imum waste power to 1% of the rated converter power
to keep the efficiency of the converter as high as possi-
RS ble. Thus, the resistor ratings will also be 4W. The
resistor value should be selected so that the main
switching voltage signal will produce as low as possible
LS
dissipation on the resistor. The dissipation is depen-
RC dent on the RC frequency characteristics, and selecting
.5 H
lower resistance or lower capacitance will shift the
characteristic frequency of the RC circuit higher, which
CDS result in the 100 kHz switching voltage producing less
6.6 nF dissipation on the snubbers. However, damping of the
snubbers will also decrease. A good starting value for
the resistor is R = 1 k.
The resonant frequency is calculated using

Equation 39.

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Calculating the required snubber circuit is very complex To ensure low resistance in the ON state the gates are
and does not give the expected results. Therefore, the driven with 12V signals. The drive circuit is shown in
parameters have to be evaluated by experimenting. Figure 48, which consists of the driver shown as S1,
When designing the snubbers the following must be slope control elements, equalization resistors R1, R2,
considered: R3, R4, R5, and C1 turn-off voltage clamp circuit D1,
Overall system efficiency D2, Q4, R6.
Signal quality The elements R5 and C1 are optional. R5 is used to
Device power ratings ensure the MOSFETs do not turn on by themselves. C1
is used to compensate for Miller capacitance and EMI
Device voltage ratings
control. Resistors R1, R2, and R3 are used to equalize
the gate threshold voltage of the MOSFETs to ensure
Design of Drive Circuitry
parallel turn-on. In combination with R4, the turn-on
To drive the MOSFETs, a driver must be used that slope is also controlled. In addition, the turn-off slope is
amplifies the signal from the dsPIC DSC device and controlled until the drain-to-source voltage (VDS)
drives the gates of MOSFETs. The gate of a MOSFET reaches the voltage clamp circuit threshold. When the
behaves like a capacitor. The MOSFET drain-to-source voltage clamp circuit becomes active, VDS stays con-
RDS depends on the gate to source voltage, VGS. The stant and the turn-off slope is reduced. This enables
higher the gate-to-source voltage, the lower the drain- part of the energy stored in the leakage inductance to
to-source resistance of the MOSFET. For the selected be transferred to the secondary side and the other part
MOSFETs: to be dissipated in a controlled fashion by the MOS-
VGS = 20V FETs. Also, overall system oscillation is reduced due to
VGS(TH) = 2-4V lower current slopes. However, it must be considered
that the turn on time of the MOSFETs will increase and
CG(TOT) = 10.7 nF
that the maximum duty cycle must be reduced.
Driver continuous supply current is calculated using
Equation 40. Where n is the number of parallel
MOSFETs.
FIGURE 48: MOSFET DRIVE CIRCUIT

T
D1 Zener
Q4
R6
D2 Q1 Q2 Q3
R1 R2 R3
S1 R4
+ V1
12V R5
C1
EQUATION 40:
I Gc = 2 n CG (tot ) VDRV f SW = 2 3 10.7 109 15 100 103 = 96.3mA

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Peak current estimate is calculated using Equation 41. Thermal Design
The heat produced by the MOSFETs and diodes must
EQUATION 41: be transferred to ambient air using heat sinks. Total
power loss estimation which were performed earlier
VDRV VGS (TH )
I Gp = are:
R 4 + ( R11 + R 21 + R31 ) 1 For MOSFETs, PMOS = 110W
For diodes, PDIODE = 40W. Forced air cooling is
Driver power dissipation calculation is shown in the
used to dissipate the heat
MCP14E3/MCP14E4/MCPE5 4.0A Dual High-Speed
Power MOSFET Drivers with Enable (DS22062) data
sheet. The total power dissipation is calculated to Full-Bridge Inverter
approximately Ptot = 1W.
INVERTER DESIGN SPECIFICATIONS
Design of Voltage and Current Feedback The inverter is used to generate the UPS output
Circuitry voltage. The specifications are:
For the push-pull stage, battery link, and DC link volt- Input voltage : 380 VDC
age, measurements are needed. Both measurements Output voltage: 230 VACrms
are done differential with the MCP6022 rail-to-rail oper- Continuous power: 1 kW
ational amplifiers. When taking high voltage differential
Continuous output current: 5.6 Arms
measurements, the input resistance must be high and
voltage and power rating of the resistors must not be Peak power for 2 seconds: 1300 VA
exceeded. Because of this, 1206 resistors are used on Maximum output current: 10 Arms
the input dividers in the reference design. The output Switching frequency: 50 kHz
signal for the differential amplifiers is 5V to increase Short circuit-proof
SNR. Then, a resistor divider is used near the dsPIC
DSC to interface to the 3.3V, 10-bit A/D converter. In INVERTER POWER-TRAIN DESIGN
addition, a capacitor is placed near the dsPIC DSC to
enable fast charge of the S&H capacitor. For measure- IGBT Selection
ment, 1% tolerance resistors are used. This is espe-
Due to the high switching frequency, IGBTs with low
cially important for the differential amplifiers to
switching losses must be selected. Their voltage rating
guarantee the same resistance in both arms to reduce
should be 600V with a current rating of 14A or more con-
common mode noise rejection.
tinuous. The STGP14NC60KD from STMicroelectronics
The MOSFET drain current and heat sink temperature was chosen and fulfills all of the selected criteria.
are also measured. The current measurement is based
Loss estimation can be done using information in the
on the voltage drop measurement on the drain-to-
data sheet and is estimated at P = 17W. The estimated
source resistance, RDSON. This type of measurement
junction-to-heat sink resistance using SilPad is:
is temperature dependent so a semiconductor
Rt = 3C/W. According to these estimates, the junc-
temperature sensor is placed which has nearly the
tion temperature will raise 50C above the heat sink
same temperature dependency as the MOSFET,
temperature.
RDSON. The current feedback signal is used to prevent
the transformer from saturating. The IGBT inverter also acts as a full-wave rectifier
when charging the battery from the power grid.
PCB Layout Considerations
Output Common-mode Choke
For the push-pull stage, special care should be taken
with traces leading the primary current. High frequency The common mode inductor has two windings on the
currents and high current peak values can produce a same core. It is called common mode because it blocks
lot of noise and even losses on the PCB. Therefore, the common mode interference and switching noise
traces should be as short as possible and they should produced by the inverter to the output. A schematic of
contain no sharp edges. It is a good idea to connect the the inductor is shown in Figure 49. The dot on the
primary windings with the transformer litz wire that is windings indicates the start of a winding. When load is
used for winding the transformer (fly leads). connected to the output, the flux in the core must be
summed; otherwise, the inductor is connected
Care should be taken to not couple the power and
incorrectly.
signal parts with the ground planes.

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FIGURE 49: COMMON MODE INDUCTOR EQUATION 44:
SCHEMATIC
LIp
N= = 39.9
Ac Bm
I1 O1
The calculated number of turns is the number for both
windings. The number is rounded to the value of 40, so
Input Output that both winding have an equal number of turns, which
is 20.
To get the desired inductance, the AL value is
I2 O2 calculated by Equation 45.
EQUATION 45:
Design of the output common-mode choke is the same L

design of that of a DC inductor, with the following AL = = 156nH
conditions: N2
Inductance: L = 250 H
Peak AC current: Ip = 17A Now, from the core manufacturers data sheet the
correct air gap can be selected. For the Epcos N87
Operating flux density: Bm = 380 mT
material, the air gap length is calculated with
Current density: J = 500A/cm2 Equation 46.
Window utilization: Ku = 0.4
Output power: Po = 1000W EQUATION 46:
First, the energy handling capability must be 1
calculated, as shown in Equation 42. A k2
s = L = 3.3mm
EQUATION 42: k1
L I p2 250 106 17 2 The gap is chosen from the data sheet to be 3.5 mm.
E= = = 0.036Ws The new AL value must be calculated for the new air
2 2 gap by Equation 47.
After that, to select the appropriate size of the core, the EQUATION 47:
area product calculation must be done, as shown in
Equation 43.
AL = K1 s K2 = 148nH
EQUATION 43:
2 E 104 The new inductance value is shown in Equation 48.

Wa Ac = = 10.3cm 4
Bm J K u
EQUATION 48:
The selected core is an Epcos ETD54 ferrite core. The

area product of that core is 11.5 cm4, and can be calcu- L = N 2 AL = 237 H
lated from the dimension data in the manufacturers
data sheet.
The number of turns required to get the desired induc- The new operating flux density is verified by
tance of the coil is calculated by Equation 44. The core Equation 49 and must be lower than the saturation
cross-section, Ac = 172 mm2, is obtained from the point of the selected material.
manufacturers data sheet.

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EQUATION 49: Output Relays
Two relays are used in the system. Relay K1 is used to
LIp control charging of the DC link capacitors from the
Bnew = = 360mT power grid. During operation this relay is always on.
N Ac
Relay K2 is used for switchover when the power grid
fails. This relay must have a fast switchover time so
N27 material has a saturation point of 410 mT (100oC). additional components are used to reduce the
switchover time. The R||C combination of R68 and C43
The cross section of the wire is calculated by
is used to allow high current at turn-on, and then
Equation 50, where RMS current through the inductor
reduce current during the ON state to allow for faster
is calculated from the output power and the RMS value
turn-off. Resistor R72 is used to deplete the energy
of the output voltage.
stored in the relay coil for faster turn-off. Transistor
Q11s switching speed is increased using R-C||R
EQUATION 50: combination, which allows for a higher base current at
Po turn-on and negative voltage on the base current at
turn-off.
I rms 230V
Acu = = = 0.88mm 2
J J DESIGN OF GATE DRIVE CIRCUITRY
A half-bridge driver with fault- and short-circuit protec-
The calculated value is the minimum cross-section of a tion must be used to fulfill the design specification. The
wire (100 kHz litz wire must be used). selected IGBT can withstand a short circuit of 10 s. If
Next, the fill factor has to be calculated by Equation 51. the driver detects a short-circuit, it will perform a soft
This will give an estimate if the windings will fit into the turn-off for the IGBTs. In addition, a bootstrap with a
bobbin. The fill factor must be 0.4 or less. Wb is the bob- 600V floating channel is needed to drive the high-side
bin winding area and is 315.6 mm2. This information IGBTs. To be able to meet the EMI requirements, the
can be found in the core data sheet. turn-on and turn-off slopes should be tunable with gate
resistors. The IR2214 from International Rectifier
EQUATION 51: meets all of these requirements. Looking at the data
sheet of the IGBTs the allowed gate voltage is VGMAX
N Acu = 20V and the gate threshold voltage is VG(TH) = 4.5-
Ku = = 0.11 6.5V. The driver is supplied by VCC = 12V to ensure
Wb IGBT turn-on. To ensure that the IGBT does not turn on
due to internal IGBT Miller capacitance when VCE
rises with high slope, gate to collector capacitors are
Output Capacitor Selection used.
The Inverter switching transistors produce the DESIGN OF VOLTAGE AND CURRENT
sinusoidal pulse width modulated voltage waveform
FEEDBACK CIRCUITRY
that has a fundamental frequency of 50 Hz or 60 Hz.
The low-pass filter comprises an output inductor and an For voltage feedback, differential amplifiers are used,
output capacitor to pass only the low-frequency which are built with the MCP6022 operational amplifier.
component (50 Hz or 60 Hz) of the sinusoidal pulse To measure power grid and output voltage, bipolar
width modulated voltage waveform, in order to produce measurements are needed. To enable the differential
a low-frequency sinusoidal output voltage. amplifiers to measure a bipolar signal voltage, an offset
of Voff = 2.5V is used as the positive reference point.
The value of the output capacitor must be large enough
Therefore, the operational amplifier gives 2.5V to its
to pass the fundamental frequency and low enough so
output when the differential measured voltage is zero.
that it should need high reactive current. To get a cut-
When the differential measured voltage is negative, the
off frequency of ~100 Hz, the value of the output capac-
output goes to 0V and conversely, the output voltage
itor selected is 4.7 F. The output capacitor should be
goes to 5V when the measured differential voltage is
able to take the high inductor ripple current as well as
positive.
suppress the switching noise. The B32924C3475M
MKP series film capacitor from Epcos fulfills all of the
selected criteria.

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Because of the high differential input voltage, a series of The clamping elements are designed using design
1206 resistors were used to stay within the voltage and tools from the manufacturer of the TOP250Y.
power rating of the devices. All of the resistors used
were 1% tolerance to guarantee the exact measurement Flyback Transformer
and reduce common mode noise rejection. The flyback transformer is designed to the desired out-
For current measurement, a Hall effect-based sensor put power and output current ripple, to enable current
from LEM is used. The sensor is bipolar and signal source operation. For the flyback converter, a trans-
output is 0.5V. At zero current, the output is 2.5V. former with air gap is needed. The transformer is
designed for the following conditions:
For all of the 5V signals, a resistor divider was
added near the dsPIC DSC to interface with the 3.3V Minimum DC link voltage: Vimin = 130.6 V
10-bit A/D converter. In addition, a capacitor was Maximum DC link voltage: Vimax = 364 V
added near the dsPIC DSC to fast-charge the SH Nominal DC link voltage: Vinom = 247.4 V
capacitor.
Nominal duty cycle: dn = 0.24
PCB LAYOUT CONSIDERATIONS Output current: Io1max = 2.5A
Nominal output voltage: Vo = 40V
Traces leading the output current should be held as
short as possible. Special care should be taken Secondary current ripple: Is[%] < 25%
because of high voltage. Around the IGBT driver the Switching frequency: f = 132 kHz
logical level and gate drive components should be sep- The primary to secondary turns ratio is calculated with
arated, and care should be taken to not couple the Equation 52.
parts with ground planes.
EQUATION 52:
THERMAL DESIGN
IGBTs must be placed on a heat sink to dissipate the Vinom VDSon d
produced heat. Total power dissipation is estimated as N PS = ( ) n = 1.9
PIGBT = 68W. The devices must be mounted on the heat VO + VDf 1 dn
sink using thermal conductive and electric insulating
material. To limit the current ripple, the inductance of primary and
secondary windings must be calculated with
Battery Charger Design Equation 53.
DESIGN SPECIFICATIONS FOR BATTERY EQUATION 53:

CHARGER SPECIFICATIONS
A battery charger is used to charge the batteries from
(Vo + VDf ) (T TON max )
LS = = 196 H
the power grid. Three series lead acid batteries were Is
used in the system. The charger design specifications
are: LP = LS N PS 2 = 684 H
Input voltage: 95-260 VAC
Output voltage: 30-45V Now, the primary current can be calculated with
Equation 54, where transformer efficiency is estimated
Output current: 0-2.5A
at 90%, and for secondary current with Equation 55.
Current control
Voltage limit
DESIGN OF POWER-TRAIN COMPONENTS

To realize the flyback converter primary drive stage, an
integrated solution TOP250Y from Power Integrations
was selected. Maximum output power is calculated as
PCH = UBmax * IBmax - 112.5W. The flyback works with
a switching frequency of f = 132 kHz. Therefore, a fast
rectifier and primary clamp diode must be used. The
transformer ratio is N2 N1 = 28 52. Based on this
ratio and the maximum input voltage, the rectifier
reverse voltage rating should be higher than the result
of Equation 66, where VF(IGBTD) is the voltage drop
across the IGBT anti-parallel diode, which are used for
power grid voltage rectification.

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EQUATION 54:
(VO ) (T Ton max )

I S = = I O I S [% ] = 1A
LS
IO
I Sc = = 4A
(1 d max )
I S
I Speek = I Sc + = 4.5 A
2
I S 1 I
I S rms = (1 d max )( I Speek ( I Sc ) + ( I Speek ( I Sc S )) 2 = 3.2 A
2 3 2
EQUATION 55:
(Vi min ) Ton max

I P = = 0.55 A
LP
VO I O
I Pc = = 2.4 A
(Vi min ) 0.9 d max
I P
I Ppeek = I Pc + = 2.7 A
2
I P 1 I
I Prms = d max ( I Ppeek ( I Pc ) + ( I Ppeek ( I Pc P )) 2 = 1.5 A
2 3 2
Now, the required wires for primary and secondary can EQUATION 57:
be selected. We will design the flyback transformer to
run a current density of J = 4 A/mm2. Therefore, the 100 PO max
required copper area for the primary and secondary Wa Ac = = 0.65cm 4
can be calculated with Equation 56 (litz wire for
Kt 2 B f J
132 kHz must be used).
The selected core needs to have a higher area product
than what has been calculated. From the magnetics
EQUATION 56: side, ETD34 and above will be sufficient; however,
I Prms there needs to be enough space to fit the windings. For
ACuP = = 0.375mm 2 this in iterations for different cores, the number of turns
J and from this the window utilization and fill factor has to
I be calculated. If the window utilization is higher than
ACuS = Srms = 0.8mm 2 90% or a fill factor higher than 0.4, the windings will not
J fit. The transformer construction winding diagram and
mechanical diagram are shown in Figure 50.
A winding factor of K = 0.2 is selected for the trans-
former and N87 material for the core. The maximum
core flux density is set to B = 130 mT. To select the
core, the area product has to be calculated with
Equation 57.

AN1279
FIGURE 50: TRANSFORMER ELECTRICAL AND MECHANICAL CONSTRUCTION
Primary
NP Secondary
Primary
NS
Bobbin CORE Insulation and Shield
NP
Primary
Secondary
Primary
For the windings, litz wire is used to grant low copper EQUATION 60:
losses at high frequency. For switching frequency f =
132 kHz, a litz wire made of AWG38 wires is used to 25
eliminate skin and proximity effect. The required number N tP = = 25 25
of parallel wires is calculated with Equation 58. DP
25
EQUATION 58: N tS = = 16.7 16
DS
ACuP
nwP = = 47.7
ACuw EQUATION 61:
ACuP NP
nwS = = 101.8 N lP = = 2.32 3
ACuw N tP
For both, we have to select standard litz wires. So, for NS
N lS = = 1.875 2
the primary, 45xAWG38 is selected and for the second- N tS
ary, 105xAWG38 is selected. The diameter of selected
wires with silk isolation is DP = 1 mm and DS = 1.5 mm.
The window utilization is shown in Equation 62 and fill
For the used ETD39 core with an air gap, the required factor in Equation 63.
number of turns can now be calculated from the
required primary inductance, turns ratio, and core data. EQUATION 62:
Primary turns are calculated with Equation 59.
EQUATION 59:
Wu = ( DP N lP + DS N lS ) / Wa = 86%
104 LP I Ppeek
NP = = 58.1 58
2 B Ae EQUATION 63:
NP
NS = = 30.5 30 K u = ( ACuP N P + ACuS N S ) / Wa = 0.25
N PS
Now, the window utilization and fill factor can be calcu- According to this the windings fit to the selected core.
lated for the selected core and wires. The bobbin win- The required air gap can be calculated from the core
dow is 25x7 mm. From this we can calculate how many data sheet. To calculate the required air gap the AL
turns for the primary and secondary (Equation 60) and value of the core has to be calculated. The AL value is
the number of required layers (Equation 61). air gap dependent. From knowing the primary induc-
tance and number of winding turns, the required AL
value can be calculated with Equation 64.

AN1279
EQUATION 64: VOLTAGE, CURRENT AND TEMPERATURE
SENSE CIRCUITRY
L The battery charger works as a current source deliver-
AL = = 203.3nH
N2 ing the requested charge current to the battery, inde-
pendent of battery voltage. For current measurement
Now, from the core manufacturer data sheet, the cor- and control, a resistor and a high-side current shunt
rect air gap can be selected. For the used EPCOS monitor (INA168 from Texas Instruments) were used.
ETD39 N87 core, the correct air gap is calculated with For current control, a discrete analog PI controller was
Equation 65. built that controls the duty cycle of the TOP250Y. In
addition, the measured current is fed through a differ-
ential amplifier stage to the dsPIC DSC device. Parallel
EQUATION 65:
to the current feedback loop, a voltage feedback loop is
1 used to limit the output voltage in case the battery is not
A k2 connected. In addition, a header is placed on the PCB
s = L = 0.95mm to interface with a temperature sensor to monitor the
k1 battery temperature and allow battery management
software to know the state of the batteries.
The nearest standard air gap values are 0.7 mm and
PCB LAYOUT CONSIDERATIONS
1 mm. Our calculated value is close to 1 mm so we
select an air gap of 1 mm and do not need to change Precaution must be taken due to high voltage signals.
the windings. If an air gap of 0.7 mm is selected, the Also the primary clamp components should be placed
number of winding turns must be corrected. as near as possible to the transformer and the
TOP250Y to reduce stress of the switching compo-
Battery Selection nents. Care should also be taken to not couple the
power, control, and measurement parts with ground
The battery selection will depend on the DC voltage
planes.
and the required backup time of the Offline UPS
system. The Offline UPS Reference Design has been
THERMAL DESIGN
designed for 36V input DC voltage, being able to
produce one hour of backup time with a 35 AH battery. The top switch and rectifier diode must be mounted on
a heat sink. Assuming efficiency of the battery charger
to be 70%, nearly 50W of loss will be dissipated. Those
losses consist of clamp losses, transformer losses,
primary switch (TOP250Y), and rectifier losses.
Therefore, we can estimate that near 30W of losses
need to be dissipated on the heat sink. Both elements
TOP250Y and the rectifier diode must be mounted on
the heat sink using thermal conductive electrical
insulating material.
EQUATION 66:
N2 28
VBR ( rect ) = Vin 2 + Vbat 2 VF ( IGBTD ) = 260 2 + 45 2 1.3 = 240.4V
N1 52

AN1279
Design of Auxiliary Power Supply CONCLUSION
DESIGN SPECIFICATIONS The Microchip dsPIC DSC device provides all of the
necessary power peripherals used for power conver-
The auxiliary power supply provides power, which is sion applications. It is a highly flexible Intelligent Power
taken from the battery link, to all of the on-board Peripheral (IPP), ADC, Comparator, and PWM mod-
electronics. The design specifications are: ules simplify the hardware schematic and reduces the
Input voltage: 30V-45V number of components in the design of a high-perfor-
Output: 150 mA @ 3.3V, 300 mA @ 5V, 500 mA mance UPS system. The built-in DSP engine and IPP
@ 12V help in optimizing control loop design, being able to
produce a clean sine wave output (THD less than 3%)
CHOICE OF COMPONENTS even with a rectifier load and a crest factor of 3:1.
Because of a wide range of input voltage and power With the help of optimized instruction sets, like MAC,
losses, a buck converter was used to generate 12V there is enough time left to perform all of the auxiliary
from the battery voltage. For 3.3V and 5V, linear tasks, fault protection, housekeeping, and communica-
regulators are used because of simplicity and price. All tion with the external world. The dsPIC33F enables
the voltage regulators are connected in series so the power conversion design with all advance features
12V buck converter needs to deliver 1A of current. For within the target price.
the buck converter, an LM5575 from National
Semiconductor was used with the switching frequency REFERENCES
set at f = 500 kHz. Components were selected
according to the LM5575 data sheet. For the linear MCP14E3/MCP14E4/MCPE5 4.0A Dual High-
voltage regulators, power dissipation must be Speed Power MOSFET Drivers with Enable
calculated to select the right package in the PCB (DS22062), Microchip Technology Inc.
layout. For the 5V regulator, maximum power TC1262 500 mA Fixed Output CMOS LDO
dissipation is calculated to P5V = (VIN - VOUT) * IOUT = (DS21372), Microchip Technology Inc.
3.15 mW and for 3.3V to P5V = (VIN - VOUT) * IOUT = 255 Power Electronics Converter, Applications and
mW. For the 5V regulator, a (KE7805ER) TO-263 Design by N.Mohan, T.M. Undeland, and W.P.
package with a PCB mount heat sink was selected, and Robbins
for the 3.3V regulator, a (TC1262) SOT223 package
Control Topology Options for Single-Phase UPS
was selected. For the analog circuits, additional chip
Inverter by M.J Ryan, W.E. Brumsickle, and R.D.
inductors and capacitors were added to separate digital
Lorenz, IEEE transaction on industry application,
and analog supply voltages.
Vol. 33, No. 2, March/April 1997.
The auxiliary power supply will start when DC link A Current Mode Control Technique with Instanta-
voltage is present or when the button is pressed. neous Inductor Current Feedback for UPS
Inverter by H.Wu, D.Lin, D. Zhang, K. Yao,
PCB LAYOUT CONSIDERATIONS
J.Zhang, IEEE transaction, 1999.
For the buck converter, due to very high frequency cur- A High Performance Sine Wave Inverter Control-
rent, care should be taken when designing the output ler with Capacitor Current Feedback and Back-
traces. The inductor, Schottky diode, and low-ESR out- EMF coupling by M.J Ryan and R.D. Lorenz,
put capacitors should be as close as possible to the IC. IEEE transaction, 1995.
Also input capacitors should be placed close to the IC
to block the noise produced by the buck converter.
For linear regulators, adequate PCB and copper area
must be provided to keep the devices cool.

AN1279
NOTES:

AN1279
APPENDIX A: SOURCE CODE
Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the Company) is intended and supplied to you, the
Companys customer, for use solely and exclusively with products manufactured by the Company.
The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.
Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR
STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE
FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
All of the software covered in this application note is

available as a single WinZip archive file. This archive
can be downloaded from the Microchip corporate Web
site at:
www.microchip.com

AN1279
APPENDIX B: CONTROL SYSTEM based on integrators and saturations. The input is
typically voltage given by the modulation block
DESIGN
(conversion of duty ratio to actual excitation voltage).
The Offline UPS Reference Design implements full dig- Depending on the topology, the power system block will
ital control of the push-pull converter and full-bridge change. Parasitic components such as capacitor ESR
inverter. MATLAB was used to design the compensa- and inductor DCR are included in the system here. In
tors based on the hardware and to generate optimal addition, loading of the system will be accounted here.
coefficients to be used in the software.
CONTROL SYSTEM BLOCK
MATLAB SIMULINK This block generates the duty ratio that drives the
power section block. The feedback signals from the
The simulation files contain the models for various sub- feedback block is the input and the output as a number
systems. Some subsystems are presented as nested between 0 and 1, which represents the duty cycle ratio.
blocks to simplify the main diagram. Simulink provides
mathematical blocks for the time domain simulations. This block may consist of various cascaded PID loops
based on the control scheme (voltage mode or current
There are typically two models in each file. mode control). In digital implementation integrators and
Analog implementation differentiators are replaced by their digital equivalents.
Digital implementation
MODULATION INVERSE BLOCK
Each SIM file analog implementation typically consists
of the following sections: This block may be part of the control system block as it
converts the output of the PID loops from voltage and
Reference Block current quantities to duty ratio quantities between 0 and
Feedback System Block 1. Different topologies have different implementations.
Power System Block Typically, it involves division with a voltage quantity
Control System Block (e.g., input voltage for buck converter and output
Modulation Inverse Block voltage for boost converter). It is just the inverse
operation of modulation performed by the physical
Modulation Block
system in converting duty ratio into voltage.
Load System Block
These models typically have a division with a voltage
Special Blocks
quantity (divisor) with little variation. Sometimes in soft-
The Simulink blocks will vary based on the converter ware these routines are not implemented, but in an
topology and control scheme implemented (i.e., current actual system, the quantity is assumed to be constant
mode, voltage mode). The following sections describe and gains are prescaled appropriately.
each block used within the models.
MODULATION BLOCK
REFERENCE BLOCK
This block represents the average model of the switch-
This system provides the input for the control system. ing system. This block converts the duty applied to
Typically, it is only a DC constant for DC-DC converters physical system to voltage quantity. Its input is the duty
or a sine wave generator for UPS-type models. The cycle ratio/parameter (0 to 1) that gets converted to
control system is required to track the reference wave- voltage quantity. It usually takes the system input volt-
form. This block may or may not be labeled as such in age and duty cycle as input and generates an output
the actual models. voltage.
FEEDBACK SYSTEM BLOCK LOAD SYSTEM BLOCK

Various signals are typically measured in a system. This block is used to generate different types of load
These include the voltages and currents for performing current. For example, a step load with DC offset can be
the control operations. created, which is useful for step loading. Sinusoidal
In digital implementation, additional blocks may be loads for UPS-type systems with variable phase (induc-
needed to account for quantization due to the presence tive, resistive, etc.), amplitude, and frequency can also
of an ADC and zero order holds for sampling the signal be used depending on the choice of test conditions.
at a constant frequency.
SPECIAL BLOCKS
POWER SYSTEM BLOCK Second order effects like saturation of inductor and
This is the actual physical system. This system dead-time are modeled for systems where these
represents energy states and is what actually gives the become important like UPS. These are indicated by
output to be controlled. Typically, it will consist of an L- saturation and dead-time blocks.
C circuit. The system implementation of L and C is

AN1279
MATLAB .m File Depending on implementation, input voltage may be
assumed constant and lumped together with some of
The .m file is used to generate the coefficients that are the gains.
used in the MATLAB model (.mdl). It also generates
the scaled values to be used in the software. The gen- Bode plots are generated by the .m file for a graphical
erated values are in fractional format. In software they representation. The following are typical plots:
must be represented as Q15(x), where x is a fractional Loop gain plot (A x ) this is used to determine
value. phase and gain margin
The following parameters are typically used: Closed loop plot (A x )/(1 + A x ) or Vo/Vo*
used to determine the closed loop response and
The input voltage
bandwidth of the system
L (equivalent inductor value)
Disturbance rejection plot Io(s)/Vo(s) used to
C (equivalent capacitor value) determine the stiffness of the system and
ESR (capacitor ESR) expected amount of voltage ripple when a load is
LSR (lumped series resistance includes tracks + applied as a function of frequency
switch + cable resistance, etc.)
Based on the topology used, these parameters can Push-Pull Compensator
vary from the actual values. For example, if three con- For the push-pull converter, a PID control algorithm
verters are in parallel, then simulation is performed for has been implemented using voltage mode control.
a single converter (instead of (3x) the capacitor value, This means that the output voltage is measured and
only a single capacitor is modeled and the inductor compared to a reference set point. The difference is
value will remain the same). then passed through the PID compensator. The PID
The input voltage may vary especially when control algorithm will look at the error, the previous
transformers are involved. Typically, all quantities are error, and the control history to determine the output
then referenced to primary or secondary based on value. The output of the PID will determine the ON
convenience. In either case, the input voltage will vary. time for the PWM duty cycle. Figure B-1 provides a
push-pull converter control scheme.
FIGURE B-1: PUSH-PULL CONTROL SCHEME
1:16
Voltage Control Duty
VREF Error Output Cycle + VOUT
X PID
VIN
PWM +
+
1001010111
Voltage Feedback
ADC S&H

AN1279
Figure B-2 shows the MATLAB Simulink block
diagram. For further details of each block refer to the
MATLAB (.mdl) file.
FIGURE B-2: MATLAB DIGITAL IMPLEMENTATION (PUSH-PULL)
VO
D
VIN D
VIN.D L_C VO1
390 VO*
VIN1 Voltage
VO*1 Digital iLoad IL
Control System Buck Modulation1
540 L_C Circuit1 Scope1
VIN1
Out1 In1
ADC
VO ILOAD x
Product3 Expected Input

Inverter Load Generator1
Current1
The following bode plots are generated from the

MATLAB (.m) file. Each plot is used to describe the
behavior of the system. The disturbance rejection plot
is defined as: I(s)/VO(s).
Figure B-3 describes the amount of load current ampli-
tude needed to be applied to generate one unit voltage
sag as a function of frequency. The higher this absolute
figure of merit, the stiffer (better) the power supply will
be. The minimum is -4 db, which will correlate to a 1A
load producing 1.5V dip on the output.
FIGURE B-3: DISTURBANCE REJECTION PLOT (PUSH-PULL)

AN1279
The loop gain voltage plot shown in Figure B-4 is used
to find phase and gain margin. From the plot it can be
seen that the phase margin (difference between 180
degrees and the phase angle where the gain curve
crosses 0 db) is 90 degrees.
To prevent the system from being conditionally unsta-
ble, it is imperative that the gain plot drops below 0 db
when the phase hits 180 degrees.
The blue curve is for the analog implementation and
the green curve is for the digital implementation. It is
generally recommended to have a phase margin of at
least 40 degrees to allow for parameter variations.
The gain margin is the difference between gain curve
at 0 db and where the phase curve hits 180 degrees.
The gain margin (where the green line on the phase
plot hits 180 degrees) is -20 db.
FIGURE B-4: LOOP GAIN VOLTAGE PLOT (PUSH-PULL)

AN1279
Figure B-5 shows the closed loop bode plot. The point
where the gain crosses -3 db or -45 degrees in phase
is usually denoted as the bandwidth. In this system, the
bandwidth of the voltage loop is approximately 1250 Hz
(8000 rad/s), which is closely matched by the bode plot.
FIGURE B-5: CLOSED LOOP (PUSH-PULL)
Full-Bridge Inverter Compensator rent reference value. The measured current value is
subtracted from the reference and the difference is
Current mode control has been implemented for the passed to the current error compensator (P). The out-
Inverter using two control algorithms: PI and P. put of the compensator is used to control the PWM out-
In current mode control, the current as well as the volt- puts. Current mode control is the preferred method as
age is measured. The inverter output is generated by it has better transient response and stability of the out-
varying the input voltage reference using a sinusoidal put. However, current mode control is usually harder to
lookup table. The difference is passed through the volt- implement as there are two control algorithms instead
age error compensator (PI) and the output is the cur- of just one as in voltage mode control.
FIGURE B-6: FULL-BRIDGE INVERTER CONTROL SCHEME
Current
Sinusoidal Reference Reference Current Duty
Voltage Control AC Out
Cycle
Error Error Output
X PI X P
PWM
+ -
+ -
Output Filter
Current
Feedback
S&H
1011010011
1001010111
Voltage Feedback
ADC
S&H

AN1279
Figure B-7 shows the MATLAB Simulink block diagram
for the inverter. For further details of each block, refer
to the MATLAB (.mdl) file.
FIGURE B-7: MATLAB DIGITAL IMPLEMENTATION (INVERTER)

Sine Wave
(input variation)
VO
++
VIN
390
IL Dtop Dtop
VIN VIN D.VIN VO

VO*
(2.D-1)
ILZX iLoad IL
Sine Wave Zero-order
ILoad L_C Circuit1
VO*1 Hold2 Full-Bridge
Digital Modulation Model1 Scope2
Control System1
Out1 In1 ++
Out2 In2 ++
Out1
The disturbance rejection plot as previously described in

Push-Pull Compensator section is defined as: I(s)/VO(s).
For the inverter, the minimum is -30 db, which implies
that for 1A load amplitude @ 1000 Hz (6280 rad/s), the
output voltage will exhibit a sinusoidal variation of 31V.
FIGURE B-8: DISTURBANCE REJECTION PLOT (INVERTER)

AN1279
Figure B-9 shows the loop gain bode plot for the Figure B-10 shows the closed loop bode plot for the
inverter. From the plot, it can be seen that the phase inverter. The point where the gain crosses -3 db or -45
margin (difference between 180 degrees and the degrees in phase is usually denoted as the bandwidth.
phase angle where the gain curve crosses 0 db) is 47 In this system, the bandwidth of voltage loop is 1250 Hz
degrees. (8000 rad/s), which is closely matched by the bode
The gain margin is the difference between the gain plots.
curve at 0 db, and where the phase curve hits 180
degrees. In the plots below, the gain margin (where the
green line on the phase plot hits 180 degrees) is -10 db.
FIGURE B-9: LOOP GAIN VOLTAGE PLOT (INVERTER)
FIGURE B-10: CLOSED LOOP (INVERTER)

AN1279
Scaling As an example, we are trying to measure 100V. We have
a potential divider such that 100V would give 1.65V on
The gains calculated from MATLAB are based on real the analog pin. Then, the value read in Q15 format is
units (volts, amps, etc.). The dsPIC DSC has a fixed 16383 or Q15(0.5), which is equivalent to Q15(100/200).
point processor and the values in the processor have a Therefore, 200 becomes the base voltage.
linear relationship with the actual physical quantities
they represent. The base (or normalizer) is denoted as VN. In other words,
VN is the voltage that will produce 3.3V or full-range
The gains generated by MATLAB being in real units, voltage on the analog ADC pin.
cannot be directly applied to these scaled values (rep-
resentation of physical quantities). Therefore, for con- At this point, voltage has been scaled as a fraction
sistency, these gains themselves need to be scaled. (V/VN) in software.
The following sections present general concepts Similarly, other physical quantities that are read via
behind proper scaling. ADC feedback are also represented in Q15 format.
The basic idea behind scaling is quantities that need to
GAIN SCALING
be added or subtracted should be of the same scale.
In simulation the control gains are calculated in real
Scaling does not affect the structure of the control sys-
units. For example, in current mode control, the output
tem block diagram in any way. Scaling only effects the
of voltage loop is the current reference (in amps).
software representation of various quantities.
Therefore, the gain is Amps/Volts or in units of 1/ohms:
SCALING FEEDBACK V Gain IREF
To properly scale the PID gains, it is imperative to The goal is to obtain IREF in an appropriate format like
understand the feedback gain calculation. The feed- Q15(I/IN) to enable implementation of the current loop
back can be represented in various formats. Fractional in software.
format (Q15) is a very convenient representation. In theory, the Q15 voltage V/VN is first multiplied by
Fractional format allows easy migration of code from VN, and then gain (G), and then the IREF that is
one design to another with completely different ratings obtained is divided by IN to get current in the cor-
with most changes only in the coefficients defined in the rect format. Since VN and IN are constants, the gain
header file. G is scaled as: G * VN/IN. This value can be used in
software to act on voltage quantity and give out a
To completely use the 16 bits available in the current quantity.
processor, the Q15 format is most convenient as it
allows signed operations and full utilization of the The input quantity should be in fractional format (this
available bits (maximum resolution). Other formats are has to be ensured in code). Then, the output current
also possible, but resolution is lost in the process. Q15 quantity will automatically be in the correct fractional
allows us to use the fractional multiply MAC operation quantity. This essentially solves the objective of
of the dsPIC DSC effectively. scaling. The same logic applies to any control block.
The feedback signal (typically voltage or current) is By considering the input and output units and scale of
usually from a 10-bit ADC. Based on the potential each block to be implemented in software, the proper
divider/amplifier in the feedback circuitry, actual voltage scaled values can be arrived at.
and currents are scaled.
SAMPLING TIME
Typically, the feedback 10-bit value (0 -1023) is brought
In calculation of the derivative and integral term in the
to +/- 32767 range by multiplying by 32. This format is
discrete time domain, TS (sampling time) factors show
also known as Q15 format: Q15(m) where -1 < m < 1
up. Since sampling time is usually constant, it can also
and is defined as (int) (m * 32767).
be lumped together with the gains. For example, if GS
These formulas will have some error as we need 2^15 is the integral gain in real units, GS * TS * VN/IN is the
= 32768, but due to finite resolution of 15 bits we use scaled value.
only +/- 32767. From a control perspective, for most
systems these hardly introduce any significant error.
In this format, +32767 corresponds to +3.3V and 0
corresponds to 0V.
The feedback circuitry and the left shift by 5 (x32) is
effectively taking the physical quantity and dividing it by
a larger base quantity. The fractional value is then rep-
resented as Q15 in software. Our goal is to find that
larger base quantity.

AN1279
PRESCALER Modulation and Duty Generation
As most physical quantities are represented as Q15 The output of a control system after saturation is
format for easy multiplication with gains, the gains also brought to 0-32767. Based on the topology, this can be
need to be in fractional format. If the value of gain interpreted as a duty ratio/modulation index
(G * VN/IN) is between -1 and +1, it can be easily representing 0-1. This can then be used to convert to a
represented as fractional format. duty cycle value by multiplying it with the PWM period.
Multiplications can then be performed using This varies with topology, but the idea behind scaling is
fractional multiply functions like MAC or using the same.
builtin_mul functions and shifting appropriately. Again, the following equation can be used where
For example, z = (__builtin_mulss(x,y) >> 15) PERIOD corresponds to 100% duty :
results in z = Q15(fx,fy), where all x, y, and z are in
Q15 format (fx and fy are the fractions that are Duty = ( __builtin_mulss(m, PERIOD) >> 15)
represented by x and y).
Division By VIN
In many instances, the gain terms are greater than
unity. Since 16-bit fixed point is a limitation, a prescaler The output of the controller in the MATLAB model is
may be used to bring the gain term within the +/- range. usually a voltage quantity. This needs to be converted
For example, if the value that needs to be used is 2.5, to a duty/modulation quantity. To do this, the control
it is predivided by 4 to bring it within 1 range. output needs to be divided by the input voltage VIN. To
If a prescaler is used for P term in a control block, it also avoid division, VIN can be assumed to be constant and
must be used for the I and D term in the control block 1/VIN can be used as a constant multiplier and bundled
as all of the terms get added together. along with the gains in the previous blocks.
To prevent number overflows, PID output and I output

individually have to be properly saturated to 32767.
The saturation limits for the PID output must be set at
one-fourth of the original 32767 to account for the
prescaler. Therefore, they are set at 8192.
Finally after saturation, the output has to be postscaled
by 4 to bring it to proper scale again.

AN1279
APPENDIX C: ELECTRICAL
SPECIFICATIONS
This Appendix provides an overview of the UPS electri-
cal specifications as well as scope plots from initial test
results.
TABLE C-1: OFFLINE UPS REFERENCE DESIGN ELECTRICAL SPECIFICATIONS

Parameter Description Min Typ Max Units Comments
VIN Input Voltage 210 220 242 V
fIN Input Frequency 47 50 53 Hz
VOUT Output Voltage 220 V
fOUT Output Frequency 49 50 51 Hz
VBATTERY Battery Input Voltage 34 36 45 V
POUT Continuous Output Power 1000 VA
OLP Over Load Protection >100 135 % 1350 VA for 2 seconds
THD Output Voltage THD 3 % Full load (resistive)
Battery Charger Mode 84 %
System Efficiency
Inverter Mode System Efficiency 84 % >50% load
tTRANSFER Mains to Inverter Transfer Time 10 ms
Inverter to Mains Transfer Time 0 ms
ICHARGE Battery Charge Current 2 2.5 A
I_BATTERY Battery Input Current (note 1) 40 A @ 100% load
T Operating Temperature 25 C
CF Crest Factor 3:1
PF Power Factor (Inductive Load) .65 Only tested at .8 PF
Power Factor (Rectifier Load) .65
Note 1: UPS run time will vary with output load current and the batteries discharge rate. Refer to the battery data
sheet for specific discharge times.

AN1279
FIGURE C-1: EFFICIENCY CHART ACROSS LOAD SPECTRUM
220V UPS Efficiency Chart
90
85
80
Percentage (%)
75
70
65
60
10 25 50 60 70 80 90 100
% Load
FIGURE C-2: OUTPUT VOLTAGE WAVEFORM NO LOAD

AN1279
FIGURE C-3: OUTPUT VOLTAGE AND OUTPUT CURRENT FULL LOAD
FIGURE C-4: OUTPUT VOLTAGE AND OUTPUT CURRENT 500 VA REACTIVE LOAD

AN1279
FIGURE C-5: MAINS TO INVERTER SWITCH OVER 400W LOAD
FIGURE C-6: INVERTER TO MAINS SWITCH OVER 400W LOAD

AN1279
FIGURE C-7: DYNAMIC LOAD RESPONSE 400W UNLOAD
FIGURE C-8: DYNAMIC LOAD RESPONSE 400W LOAD STEP

AN1279
APPENDIX D: SAFETY NOTICES
The following safety notices and operating instructions General Notices

should be adhered to, to avoid a safety hazard. If in any
doubt, consult your supplier. The reference design is intended for evaluation
and development purposes and should only be
WARNING This reference design must be earthed operated in a normal laboratory environment as
(grounded) at all times. defined by IEC 61010-1:2001
WARNING The reference design should not be Clean with a dry cloth only
installed, operated, serviced, or modified except by Operate flat on a bench, do not move during
qualified personnel who understand the danger of operation and do not block the ventilation holes
electric shock hazards and have read and understood
The reference design should not be operated
the user instructions. Any service or modification
without all of the supplied covers fully secured in
performed by the user is done at the users own risk
place
and voids all warranties.
The reference design should not be connected or
WARNING It is possible for the output terminals to be operated if there is any apparent damage to the
connected to the incoming AC mains supply and may unit
be up to 410V with respect to ground, regardless of the
The reference design unit is designed to be
input mains supply voltage applied. These terminals
connected to the AC mains supply via a standard
are live during operation AND for five (5) minutes after
non-locking plug:
disconnection from the supply. Do not attempt to
access the terminals or remove the cover during this - The Mains switch constitutes the means of
time. disconnection from the AC Mains supply, and
therefore, the user must have unobstructed
WARNING High Voltage could be present at any of access to this switch during operation
the AC voltage terminals (Mains Input and UPS Output)
- The unit has no switch to disconnect the battery,
due to residual charge and/or from the system batteries
and therefore, the user must have unobstructed
being connected. Ensure all terminals are
access to this connector during operation
disconnected for at least five (5) minutes prior to
servicing or removing the cover. - The reference design should only be operated
with the supplied batteries. A DC power supply
CAUTION Particular care should be taken during must not be connected to the Battery Connector.
code development as unexpected voltage regulation
behavior is possible. Ensure that the Load connected
to the UPS Output is properly protected against an
overvoltage event caused by code development.
CAUTION For continued protection against the risk of
fire, replace fuses with the same type of fuses included
in the original UPS unit.

AN1279
APPENDIX E: SCHEMATICS AND BOARD LAYOUT
FIGURE E-1: OFFLINE UPS REFERENCE DESIGN BOARD LAYOUT (TOP)

FIGURE E-2:
Imax=2.5A
DS01279B-page 76
Vmax=48V
AN1279
D25
R96
Udc W2 STTH8R06D Uch Ubat
T2 0.33e 5W
R97
C82
0.22uF 630V C84 C85
P4 6k8 4W C83 R98 C86 100uF 100V
R99
PGND DNP 0.68uF 100V 100V
1206 4.7nF 1000V DNP
390k
Charger+
D26 PGND
P2 R100
1206 BYV26E TP13
390k
Charger- C144
R102 D49 12V
100nF 25V
1206 Zener 47V
PGND U6
390k ETD39 Flyback transformer N1:N2 = 52:28 Lp=700uH 1SMB5941BT3G
INA168
GND
5
12V
R108 3
+
1206 R101 1
Q12
390k 3k3 U7B 4
BC817 R103 -
LM358
8
2
R109 6.8k 1%
TP14 6
1206 7 R106
R104 B
7
2
390k 5 GND
3k3
1k5 1%
D
4
1
C R105
IC4 C143
R107 GND
180e 100nF
S
X
F
TOP250YN (TO220-7) 6.8e D27
Ibatm+
Ibatm-
C88
4
3
5
DNP BAR43C PGND
100nF 100V C89
R110 47uF 25V

12k C91
12V
100nF 25V
U7A
8
LM358 R111 R112

GND 24k 2k2
2
Iref
PGND 1
A C92 C147
3 R113
10k 1uF 1uF
Q14
4
R114
BC817 GND
4k7 C93
R115 GND
EFB
1k5
47nF
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 1 OF 8)
GND
PGND
R202
2k2
GND
2009-2011 Microchip Technology Inc.

FIGURE E-3:
12V
L10
P3 3V3 C25 C94
P_FAN
dsVpp 1 2 4.7uH 1.5A C59
D29
3 4 dsICSPD GND C22 1
dsICSPC 5 6 1uF 100nF 10uF 25V 2
GND ES1B 1uF 25V
ICSP e10 FAN
No galvanic isolation!
Do not connect when UPS is connected to AC Line!
R116
EPP
EFB
Q15
PS
dsICSPC
dsICSPD
/SYS_FLT
Tb
Iref
3V3 100 IRLL2705
10k

3V3 AR1
44
43
42
41
40
39
38
37
36
35
34
U15 GND
R206 dsPIC33FJ16GS504
C95
Vss
VDD
RP6
RP5
RP8
DNP
AN9
RP15
RP24
RP23
1 GND
FLT_CLR PGC1
PWM4L
33
PWM4H
OSCO R11712pF
2 Y1 1M DNP
SS RP20
32
R207 OS CI 2 C96
3 20MHz
SCLK RP21
10e 31 GND
AN8 T
4 12pF
SDO RP22
30
Vss
5 3V3 C97
SDI RP19
29
VDD
6
R15 R26 R127 R201 Vss 100nF
28
DNP DNP DNP DNPC140 10uF 6V Tant AN10 A1 C98
7
VCAP
100nF C139 27
AN11 ACi
8 1uF
S2 PWM3H
26
D30 S2 D33 D34 AN5 Ub GND
9
DNP DNP DNP S1 PWM3L
GND 25
AN4 Ib
DNP 10
S6 PWM2H
24
AN3 Udcm
GND 11
S5 PWM2L
23
AN2 IP
PWM 1H
PWM 1L
RP16
RP29
AVSS
AVDD
MCLR
RP2 7
RP2 8
AN0
AN1
12
13
14
15
16
17
18
19
20
21
22
I
ACo
A2
S4
S3
TX
RX
FAULT/SD
3V3
BR4 3V3A R118
C141
0e 10k
1uF
AGND GND dsVpp
C99
C142
100nFAGND 100pF
GND
DS01279B-page 77
AN1279
5V
R119 R120
FIGURE E-4:
220e 10k
DS01279B-page 78
C100
100nF
AN1279
P5
1 2
3 4 A0
GND
E1 5 6 E2
5V
DB0 7 8 DB1
DB2 9 10 DB3
DB4 11 12 DB5 R121
R122
DB6 13 14 DB7 4k7
10k
15 16 LED1
BTN 17 18 LED2
R123
19 20
C101 4k7
2.2nF LCD P6 5V
Vpp 1 2
GND
3 4 ICSP D
ICSP C 5 6
GND
ICSP
No galvanic isolation!
Do not connect when UP S is connected to AC L ine!
5V
5V U8
2 21
DB6 RA0/AN0 RB0/INT0 DB0
R136 3 22
DB7 RA1/AN1 RB1/INT1 DB1
10k 4 23 R124 R125 R204 R126
A0 RA2/AN2/VREF- RB2/INT2 DB2
5 24 DNP DNP DNP DNP
E1 RA3/AN3/VREF+ RB3/CCP2 DB3 5V
6 25
E2 RA4/T0CKI RB4 DB4
7 26
RA5/AN4/SS/LVDIN RB5/PGM DB5
10 27
OSC2/CLKO/RA6 RB6/PGC ICSP C
9 28
OSC1/CLKI RB7/PGD ICSP D
Y2
7.3728MHz 5V 11 P_BZ R128
RC0/T1OSO/T1CKI LED1
2 1 12 SS
RC1/T1OSI/CCP2 LED2 1 0R
13
R130 RC2/CCP1 2 R129
14
10k RC3/SCK/SCL SCLK
R131 15 0R
RC4/SDI/SDA
1M 1 16 R132
VPP MCLR/VPP RC5/SDO
17 SDO
RC6/TX/CK BTN 0R
C102 C103 18
RC7/RX/DT R133
33pF 33pF
8 5V
VSS R134 SDI
19 20 0R
VSS VDD
GND GND 4k7
GND C104
D31 R203 R135
PIC18F2420-E/SO 100nF
DNP DNP
GND
GND

S6 S3
R41 R42
S5 S4
4k7 4k7
FIGURE E-5:
R43 R44
4k7 4k7
GND GND
GND GND K1
3V3 3V3
Phoenix Contact DP DT MR...21- 21
UDC
FLT_CLR DSH2
R45 47e 12V D15
R46 R47 HOP2
D13 D14
4k7 4k7 R48 12e
HON2
R49 1N4148 Q6
/SYS_FLT R51 1k Q7 Q8 R50
4k7 SDDH2 BC817
EGP10J EGP10J A1
GND STGP14NC60KD STGP14NC60KD 3k3
FAULT/SD DSH1
R53 47e R52
HOP1 10k

R54 12e
U3 HON1 R55 C34 R56
12V R57 1k 10k 3.3nF 25V 10k
S6 HIN DSH DSH2 SDDH1 C33 GND
S5 LIN Vb
3.3nF 25V R40
FLT_CLR FLT_CLR N.C. C35 L2
/SYS_FLT /SYS_FLT HOP HOP2 250uH ETD54
1uF 25V DSL2 100e 4W
FAULT/SD /FAULT/SD HON HON2 R58 47e L1 L2
Vss Vs LOP2
D16 D17
SDDL2 SSDL SSDH SDDH2 R59 12e
L2
GND LON2
COM N.C. R60 1k Q9
LON2 LON N.C. SDDL2 Q10
EGP10J EGP10J
1
3
5
7
2
4
6
8
PGND LOP2 LOP N.C. STGP14NC60KD STGP14NC60KD

DSL1
Vcc N.C. R61 47e
1
3
5
7
2
4
6
8
DSL2 DSL N.C. LOP1

C145 R62 12e C36
1uF 25V IR2214 LON1 R63 C38 R64
1kR65 U4
D18 SDDL1 C37 10k 3.3nF 25V 10k
PGND R66 HXS 20-NP/SP2
3.3nF 25V 4.7uF 305V
1e 1206
ref
out
gnd
Vc
EGP10J
9
12
11
10
12V U5 PGND 5VA

S4 HIN DSH DSH1
C39
S3 LIN Vb C40
C41 100nF
FLT_CLR FLT_CLR N.C.
/SYS_FLT /SYS_FLT HOP HOP1
1uF 25V 100nF
FAULT/SD /FAULT/SD HON HON1 Im
Vss Vs
C132
SDDL1 SSDL SSDH SDDH1
L1
4n7 AGND AGND
A Ci1 m
A Ci2 m
GND COM N.C.

LON1 LON N.C. S1
AGND
PGND LOP1 LOP N.C.
N Filter N
Vcc N.C.
DSL1 DSL N.C.
C146
1uF 25V IR2214 SW-DPST L L
F2
D19 J6
PGND R67 PE J5
Not on PCB ACInL
Not on PCB ACInN R68
No t on PCB
1e 1206 GND 33e 12V
C42 1206
A Co2m
EGP10J
A Co1m
J3 J4
Not on PCB 470pF

PACin C43 ACOutN ACOutL
2
Q11 10uF 25V
3 A2
BC817
1 R69 R70
R71 R72
100e 3k3
Plug AC Male 10k 12e
GND D20
GND
K2
Phoenix Contact DP DT MR...21- 21 1N4148
DS01279B-page 79
AN1279
C105
C106 4.7nF
4.7nF
FIGURE E-6:
R137
R138
2k 1%
DS01279B-page 80
2k2 1% 5VA 3V3
5VA 3V3 R139 R140 R141 C107
AN1279
R142 R143 R144 R145 Udcm-

C108
8
ACi1m 56k 1% 56k 1% 56k 1%
1206 1206 1206 100nF U9A
8
82k 1% 82k 1% 82k 1% 82k 1%
100nF U10A 2 AGND MCP6022 D12
1206 1206 1206 1206
2 AGND MCP6022 D35 1 R146 BAR43S
R147 BAR43S R148 R149 R150 A Udcm
1 3 1k69 1%
R151 R152 R153 R154 A ACi Udcm+
3 R155
ACi2m 1k69 1% 56k 1% 56k 1% 56k 1%
R156 1206 1206 1206 R157 C109 C110
4
82k 1% 82k 1% 82k 1% 82k 1%
1206 1206 1206 1206 R158 C111 C112 4.7nF 3k3 1% 4.7nF
4
4.7nF 3k3 1% 4.7nF 3V3 2k 1%
2k2 1% AGND AGND AGND AGND
2V5A AGND AGND AGND AGND
D36 C113
AGND
C114 R159 BAR43S 4.7nF
4.7nF Im I
1k69 1% R160
R162 R161
C115 2k2 1%
2k2 1% 3V3
3k3 1% 4.7nF R163
3V3
R164 R165 R166 R167 Ubm-
8
ACo1m AGND AGND AGND 33k 1%

1206 U9B
8
82k 1% 82k 1% 82k 1% 82k 1%
U10B 6 MCP6022 D37
1206 1206 1206 1206
6 MCP6022 D38 7 R168 BAR43S
R169 BAR43S R170 B Ub
7 5 1k69 1%
R171 R172 R173 R174 B ACo Ubm+
5 1k69 1% 33k 1% R175 C117
ACo2m
R176 1206 R177 C116
82k 1% 82k 1% 82k 1% 82k 1%
4
1206 1206 1206 1206 R178 C118 C119 4.7nF 3k3 1% 4.7nF
4
4.7nF 3k3 1% 4.7nF 2k2 1%
2k2 1% AGND AGND AGND AGND
2V5A AGND AGND AGND
C120
4.7nF
AGND
2V5A R179
100k 1%
5VA R180
5VA 3V3
5VA C121 R181 C122 2k2 1%
Ibatm-
8
8
100nF U11A 33k 1%
1206 100nF U12A 3V3
R182 2 AGND MCP6022 D39
2 AGND MCP6022
1 R183 BAR43S
A 1
8
2k2 1% 3 R184 A Ib
3 U12B
Ibatm+ 1k69 1%
R185 6 MCP6022 D40
R186 33k 1% R187 BAR43S
4
C123 1206 R188 C124 C125 7
4
B IP
4.7nF 2k2 1% 4.7nF 3k3 1% 4.7nF 5 1k69 1%
100k 1% IPm R189 C126
AGND
AGND AGND AGND AGND R190
4
AGND C127 R191

3k3 1% 4.7nF
220pF
3V3 10k
Tr DNP 2k2 1%
AGND AGND AGND AGND
R192 R193
AGND
2k2 1% 3k3 1% P7 5VA
AGND 3V3 D41
1 R194 BAR43S
2 Tb
8
U11B 3 C128 R195
1k
6 MCP6022 D42 Bat Temp AGND 100nF
7 R196 BAR43S 100k
R197 B T
5 1k69 1% AGND
Tm+
R198 AGND AGND
3k3 1%
C129
4
C130 3k3 1% 100nF
100nF
AGND AGND AGND
AGND

Udc Ubat
P1
W1 12V 1 2 12V
R73 C44 C45 C46
2-position header 5V 3 4 5VA
FIGURE E-7:
1206 external ON/OFF switch F1 0.33uF 100V 0.33uF 100V 470nF 25V
SMD075F/60 3V3 5 6 3V3A
150k D21
(on enclosure) GND 7 8 AGND
BAV99
R76 GND GND C47 power
1206 R77
150k IC1 12V
100k L3
C48 220nF 25V
R79 1uF 25V 3 1 47uH 2.6A
VIN VCC
1206 2 16 C49
/SD BST
150k GND 4 14 D22 330pF C50 C51 C52 D44
SYNC SW
8 15 ES3B C53
RAMP PRE BZX85C16
R80 BC856 R74 10 13 1uF 25V 68uF 25V 68uF 25V 68uF 25V
SS IS
1206 Q13 10k 7 R81 LowESR LowESR LowESR
RT
150k 5 11 10e R82 GND

COMP OUT
6 1206
FB 10k
R84 R75 9 12
AGND PGND
1206 47k C54 GND
150k R78 1uF 25V R85 GND
C55 12K PAGND1 LM5575 GND R86 R83
68k
R87 P10 680pF 25V DNP 1k 1%
4k7 S3
2
1206 SW-PB
1
PAGND1
GND TEST R88
PAGND1 24k
C56
GND 1nF 25V L6
C57 C64 0805

R18 C66
2.2nF 25V BLM21PG221
4k7 1uF 25V 68uF 25V
LowESR
BR2 D45 GND
0e
GND PAGND1 Needs heatsink on P CB
VR1 5V 5VA
L8
VIN VOUT
0805 C68
GND R220 C72
C73 BLM21PG221
C75 2k2 2.2uF 10V 68uF 25V
LM2904S-5.0
2.2uF 10V 68uF 25V LowESR
LowESR AGND
GND
D46
GND
GND
VR2 3V3 3V3A

L5
VIN VOUT
C60 0805 C62
GND R221 C61
BLM21PG221
2.2uF 10V 1k 2.2uF 10V 68uF 25V

TC1262-3.3
UBAT UDC LowESR
GND AGND
100pF 2kV 100pF 2kV GND
D47
C80 C81 C78 C79 GND
100pF 2kV 100pF 2kV
GND PGND
EGND EGND EGND EGND
DS01279B-page 81
AN1279
D1 R1 D2 R4 TP2
S2
S1
P9A
EPP
2.4k 3W 2.4k 3W
R2 R5 ETD54 L1 DC+
FIGURE E-8:
DNP C2D05120 C2D05120 Udc

T1
R3 DNP Ubat C1 C4 Udcm+
DS01279B-page 82
4k7 C23 200H
Ubm+ R16 C2 C3
150pF 1kV 150pF 1kV
AN1279
e15 C5 C7 e15
R6 4k7 10R 3W 0.01uF
.1uF 630V .1uF 630V
100V Udcm-
J1 Fext 470uF 400V HT 105C
BR1 DC- PGND
C13 C14
4
3
2
1
0e 2x20A e5 e5 P9B
BAT+ Slow Blow (on enclosure) T3 DNP
U2 C11 C12 0.33uF 0.33uF CT 1:1000 Tr
MCP14E4 J2 Ubm- 1200uF 1200uF (optional)
GND PGND 100V 100V R8
GND
I N_B
I N_A
100V 100V
ENB_A
10k DNP
BAT- PGND PGND C24 R7 R9
1000uF 100V HT 105C R17
12V 10R 3W PGND 2.4k 3W ref1
2.4k 3W
OUT_ B
VDD
OUT_ A
ENB_ B
12V D3 D28
0.01uF
100V
5
6
7
8
C6 C8 R12 R13
C2D05120 C2D05120 C17
R10
DNP DNP DNP
150pF 1kV 150pF 1kV
1k
C15 C16 current sense GND
Q18 12V
1uF 25V 68uF 25V BAS21
BC817 Tr
LowESR D4
DNP
D8 R25
R11
Q1A Q1B Q1C 1k 10k DNP

D23
100V FDP2532 FDP2532 FDP2532
BAR43S current sense
D7 Q19
BAS21 ref2
BAS21 BC817
D5
DNP
D9
R23 R29 R30
C26
10k Q2A Q2B Q3C DNP DNP DNP
4.7e R19A
4.7e R19B
4.7e R19C
D24
100V FDP2532 FDP2532 FDP2532
BAR43S
D10
R19 PGND BAS21 GND
12e 1206 12V

R24
10k
4.7e R22A
4.7e R22B
4.7e R22C
C20 R20 R14

D6
3.3nF 25V 10k R22 PGND 3k3
D11 D43
12e 1206
BZX84C3V6
PGND C21
Q5
BAS21 BAS21 3.3nF 25V
TP5 R21 BC807
100nF C27 5V P_CT
10k
DNP U1A
1 Tm+
3
ref1 R36 2
GND 1 R28
1k PGND
2 RT1 DNP
t
R37
TP6 LM393 10k
C28 2k2 C29 KTY81/122
Vvercurrent shutdown to driver
100pF DNP DNP
GND DNP
TP7 3V3 IPm
GND R38 R38a DNP

D32 D48 Tm-
Current sense to dsPIC GND BAV99 BAV99
GND
1206 DNP
1206
R39 U1B
DNP
33e(CT)
10k DNP 5
1k / 33e(CT)
7
PS
6
ref2
Cycle-by-cycle Current-Limit to dsPIC C30
68pF DNP GND
GND

FIGURE E-9:
P8 5VUSB
UVpp 1 2
3 4 UICSP D
UICSP C 5 6
GNDUSB
ICSP

3V3 5VUSB
C131 C136
100nF 100nF
U13
1 8
GND Vcc1 Vcc2 GNDUSB
2 7
RX Out A In A
3 6
TX In B Out B
4 5
GND 1 GND2
GND ISO7221 GNDUSB

5VUSB
U14
R199
10k
1 28
UVpp MCLR/VPP/RE3 RB7/KBI3/PGD UICSP D
2 27
RA0/AN0 RB6/KBI2/PGC UICSP C
3 26
RA1/AN1 RB5/KBI1/PGM
4 25
RA2/AN2/VREF- RB4/AN11/KBI0
5 24
RA3/AN3/VREF+ RB3/AN9/VPO
C133 6 23 5VUSB
RA4/T0CKI/RCV RB2/AN8/INT2/VMO
7 22
GNDUSB RA5/AN4/HLVDIN RB1/AN10/INT1
8 21
2
Vss RB0/AN12/INT0
12pF 9 20 C134 0805
OSC1/CLKI VDD
R200 Y3 10 19 100nF BLM21PG221
OSC2/CLKO/RA6 VSS
C135 1M 11 18 5VUSB L9 J7
1
RC0/T1OSO/T1CKI RC7/RX/CK
12 17 1
GNDUSB RC1/T1OSI/UOE RC6/TX/CK VBUS
20MHz 13 16 2
RC2/CCP1 RC5/D+/VP D-
12pF 14 15 C137 3
VUSB RC4/D-/VM D+
1uF 25V 4
GND
C138
1nF GNDUSB
USB B 1-1470156- 1
GNDUSB PIC18F2450 GNDUSB
GNDUSB
EGND
DS01279B-page 83
AN1279
AN1279
APPENDIX F: REVISION HISTORY
Revision A (August 2009)

This is the initial released version of this document.
Revision B (October 2011)

This revision includes the following updates:
Added Appendix D: Safety Notices
Added Appendix F: Revision History
Additional minor updates to text and formatting
were incorporated throughout the document

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyers risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2009-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-723-2
Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

Worldwide Sales and Service
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Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/
Fax: 852-2401-3431 France - Paris
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Offline UPS Reference Design Using The dsPIC DSC

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AN1279

Offline UPS Reference Design Using the dsPIC DSC

Application Markets for UPS Systems FIGURE 1: OFFLINE UPS DIAGRAM

UPS systems provide for a large number of applica-

If a longer backup period is considered, a larger battery

2009-2011 Microchip Technology Inc. DS01279B-page 1

FIGURE 2: LINE-INTERACTIVE UPS Rectifier/ Inverter

AC Input Load SYSTEM SPECIFICATIONS

DS01279B-page 2 2009-2011 Microchip Technology Inc.

FIGURE 4: OFFLINE UPS REFERENCE DESIGN

EMI Filter DPDT Load

Constant Current Flyback Switch

3 x 12 VDC Push-Pull 380 VDC Full-Bridge

2009-2011 Microchip Technology Inc. DS01279B-page 3

FIGURE 5: PUSH-PULL CONVERTER RESOURCE DIAGRAM

TABLE 2: RESOURCES REQUIRED FOR A DIGITAL PUSH-PULL CONVERTER

DS01279B-page 4 2009-2011 Microchip Technology Inc.

FIGURE 6: DIGITAL FULL-BRIDGE INVERTER RESOURCE DIAGRAM

TABLE 3: RESOURCES REQUIRED FOR A DIGITAL FULL-BRIDGE INVERTER

2009-2011 Microchip Technology Inc. DS01279B-page 5

FIGURE 7: DIGITAL FLYBACK SWITCH MODE CHARGER RESOURCE DIAGRAM

Table 4 shows the resources used by the dsPIC DSC

TABLE 4: RESOURCES REQUIRED FOR A DIGITAL FLYBACK SWITCH MODE CHARGER

DS01279B-page 6 2009-2011 Microchip Technology Inc.

FIGURE 8: FORWARD CONVERTER

where d is the duty cycle of the transistor Q

2009-2011 Microchip Technology Inc. DS01279B-page 7

FIGURE 9: PUSH-PULL CONVERTER

DS01279B-page 8 2009-2011 Microchip Technology Inc.

FIGURE 10: HALF-BRIDGE CONVERTER

2009-2011 Microchip Technology Inc. DS01279B-page 9

FIGURE 11: FULL-BRIDGE CONVERTER

EQUATION 4: Flyback Converter

FIGURE 12: FLYBACK CONVERTER

DS01279B-page 10 2009-2011 Microchip Technology Inc.

FIGURE 13: SINGLE-PHASE

FIGURE 14: SINGLE-PHASE FULL-BRIDGE VSI

S1- D1- S2- D2-

2009-2011 Microchip Technology Inc. DS01279B-page 11

FIGURE 15: LINEAR CHARGER

Transformer Rectifier Current Battery

FIGURE 16: SWITCH MODE CHARGER

DS01279B-page 12 2009-2011 Microchip Technology Inc.

FIGURE 17: FERRORESONANT CHARGER

FIGURE 18: SCR CHARGER

Power Supply Charge Control

2009-2011 Microchip Technology Inc. DS01279B-page 13

FIGURE 19: OFFLINE UPS BLOCK DIAGRAM

Power Conversion Block

AC Mains Input Rectified

LCD Module USB Port

DS01279B-page 14 2009-2011 Microchip Technology Inc.

FIGURE 20: OFFLINE UPS SOFTWARE: HIGH-LEVEL PARTITIONS

Offline UPS Software

UPS State Machine User Interface Software

Power Conversion Algorithms Priority: Low

2009-2011 Microchip Technology Inc. DS01279B-page 15

FIGURE 21: OFFLINE UPS STATE DIAGRAM

Inverter Mode Charger