1000w Inverter PURE SINE WAVE Schematic Diagram

AN1279
Offline UPS Reference Design Using the dsPIC DSC

Authors:
Sagar Khare
Mohammad Kamil
Microchip Technology Inc.
UPS OVERVIEW
An Uninterruptible Power Supply, or UPS, is an
electronic device that provides an alternative electric
power supply to connected electronic equipment when
the primary power source is not available.
Unlike auxiliary power, a UPS can provide instant
power to connected equipment, which can protect
sensitive electronic devices by allowing them to shut
down properly and preventing extensive physical
damage. However, a UPS can only supply energy for a
limited amount of time, typically 15 to 20 minutes.
Although its use can extend to a virtually unlimited list
of applications, in past years the UPS has become
even more popular as a means of protecting computers
and telecommunication equipment, thus preventing
serious hardware damage and data loss.
Application Markets for UPS Systems

UPS systems provide for a large number of applications in a variety of industries. Their common applications range from small power rating for personal
computer systems to medium power rating for medical
facilities, life-support systems, data storage, and emergency equipment, and high power rating for telecommunications, industrial processing, and online
management systems. Different considerations should
be taken into account for these applications. As an
example, a UPS for emergency systems and lighting
may support the system for 90-120 minutes. For other
applications like computer backup power, a UPS may
typically support the system for 15-20 minutes. If power
is not restored during that time, the system will be
gracefully shut down.
Types of UPS Systems

A typical UPS for computers has four basic protection
roles: being able to cope with power surges, voltage
shortage, complete power failure and wide variations in
the electric current frequency. There are three types of
UPS systems, depending on how the electric power is
being stored and relayed to the electronic device
connected to them:
Offline UPS (also known as Standby UPS)
Line-Interactive (or Continuous UPS)
Online UPS (often called double conversion supply)
OFFLINE UPS
An Offline UPS system (see Figure 1), redirects the
electric energy received from the AC input to the load
and only switches to providing power from the battery
when a problem is detected in the utility power. Performing this action usually takes a few milliseconds,
during which time the power inverter starts supplying
electric energy from the battery to the load.
FIGURE 1:
OFFLINE UPS DIAGRAM
AC Input
Load
Inverter
Charger
Battery
If a longer backup period is considered, a larger battery

is required. For process equipment and high power
applications, some UPS systems are designed to provide enough time for the secondary power sources,
such as diesel generators, to start up.
2009 Microchip Technology Inc.
DS01279A-page 1
AN1279
LINE-INTERACTIVE UPS
FIGURE 3:
A Line-Interactive UPS (see Figure 2), always relays

electric energy through the battery to the load. When
AC mains power is available, the battery is being
charged continuously. At the same time, the UPS regulates the AC output voltage and the lag related to coupling the inverter is nearly zero. When a power outage
occurs, the transfer switch opens and the electric
energy flows from the battery to the load (Stored
Energy mode). Due to these characteristics, continuous UPS systems tend to be somewhat more expensive than an offline UPS.
FIGURE 2:
ONLINE UPS DIAGRAM

Static Switch
(Static Bypass)
AC Input
Load
Battery
Static Switch
AC Input
Load
Inverter
Battery
Legend:
Inverter
Rectifier/
Charger
LINE-INTERACTIVE UPS
DIAGRAM
Normal mode
Stored-energy mode
ONLINE UPS
An Online UPS (see Figure 3), combines the two basic
technologies of the previously described UPS models,
with rectifiers and inverter systems working all of the
time. As is the case with a Line-Interactive UPS, the
power transfer is made instantly as an outage occurs,
with the rectifier simply being turned off while the
inverter draws power from the battery. As utility power
is again established, the inverter continues to supply
power to the connected devices, while the rectifier
resumes its activity, recharging the battery. This design
is sometimes fitted with an additional transfer switch for
bypass during a malfunction or overload.
SYSTEM SPECIFICATIONS
The reference design in this application note describes
the design of an Offline Uninterruptible Power Supply
(UPS) using a Switch Mode Power Supply (SMPS)
dsPIC Digital Signal Controller (DSC).
The Offline UPS Reference Design consists of three
major UPS topology blocks:
Push-Pull Converter (steps up the DC battery voltage to a constant high-voltage DC)
Full-Bridge Inverter (converts DC voltage to a
sinusoidal AC output)
Flyback Switch Mode Charger (current source
and charges battery with constant current)
The input and output specifications are shown in
Table 1.
TABLE 1:
I/O SPECIFICATIONS
220V UPS Version Specifications

AC Input
220 VAC 10%, 50 Hz 3 Hz
DC Input
3 x 12 VDC (lead acid battery)
UPS Output
220 VAC, 50 Hz 1 Hz,

sinusoidal
Rating
1000 W/1000 VA,

(1300VA - 2 seconds)
Input Filtering
EMI/RFI filtering
110V UPS Specifications
DS01279A-page 2
AC Input
110 VAC 10%, 60 Hz 3 Hz
DC Input
3 x 12 VDC (lead acid battery)
UPS Output
110 VAC, 60 Hz 1 Hz,

sinusoidal
Rating
1000 W/1000 VA,

(1300VA - 2 seconds)
Input Filtering
EMI/RFI filtering
AN1279
1 kVA OFFLINE UPS REFERENCE
DESIGN
After a power failure, the system is switched to UPS

mode. In this situation, the DPDT relay is turned OFF
to prevent power from being delivered to the AC line.
The push-pull converter steps up the battery voltage to
380 VDC. The high DC voltage is then converted with
the full-bridge inverter and filtered with an LC filter to
create a pure sine wave 220/110 VAC output where
load is connected. This power switchover sequence is
made in less than 10 ms.
The Offline UPS system shown in Figure 4 operates in

Standby mode and in UPS mode. When AC line voltage
is present, the system is in Standby mode until a failure
occurs on the AC line. During Standby mode, the battery is charged and is maintained after becoming fully
charged. When the battery is charging, the inverter
works as a rectifier through the IGBTs anti-parallel
diodes. The flyback switch mode charger acts as a current generator and provides constant charging current
to the battery.
FIGURE 4:
220 VAC,
50 Hz
OFFLINE UPS REFERENCE DESIGN
DPDT
Relay
EMI Filter
Load
220 VAC
Constant Current
Battery
3 X 12 VDC
Flyback Switch
Mode Charger
Push-Pull
DC/DC
Converter
LC Filter
380 VDC
Full-Bridge
Inverter/
Rectifier
DS01279A-page 3
AN1279
Listing of I/O Signals for Each Block,
Type of Signal, and Expected Signal
Levels
temperature sensor measures heat sink temperature,

and the primary current measurement (IP) protects the
converter in case of transformer flux walking. The PWM
outputs from the dsPIC DSC are firing pulses to the
driver to control the output voltage.
PUSH-PULL CONVERTER
As specified in Figure 5, measurement of DC output
voltage (UDCM) is required to implement the control
algorithm. The EPP signal is for enabling the driver, the
FIGURE 5:
PUSH-PULL CONVERTER RESOURCE DIAGRAM

UDCM+
UBAT
IPM
PGND
UDCM-
UCDM
IP
DRIVER
EPP
Temperature
Sensor
ADC
ADC
ADC
ADC
I/O
PWM
PWM
UB
dsPIC33FJ16GS504
Table 2 lists the resources used by the dsPIC DSC

device for a push-pull converter.
TABLE 2:
RESOURCES REQUIRED FOR A DIGITAL PUSH-PULL CONVERTER

Type of Signal
dsPIC DSC
Resources Used
Expected Signal Level
Analog
AN3
2.99V
IP
Analog
AN2
0V-1.65V
T (optional, not implemented

in software)
Analog
AN8
0V-3.3V
UB
Analog
AN5
1.5V-1.98V
Enable driver, Digital
RB6
Digital
PWM3H, PWM3L
Signal Name
UDCM
EPP
Push-Pull Gate Drive
DS01279A-page 4
AN1279
FULL-BRIDGE INVERTER
The block diagram in Figure 6 illustrates that
measurement of the AC output voltage (ACO) is
required to implement the control algorithm. With
measurement of the output current (I), that current can
be limited to prevent overloading of the converter. The
presence of power grid voltage is detected with
measurement of (ACI) voltage. When power grid
voltage fails, signal A2 turns off the relay K2 and
prevents power flow to the line when the UPS is
operational. Signal A1 controls the K1 relay, which is off
when DC link voltage is low to prevent current inrush in
FIGURE 6:
the DC link capacitors when power grid voltage is fed

to the rectifier. This happens when the UPS is
operational and the battery is depleted, the UPS goes
off or initial system connect to grid power. The
FLT_CLR signal is used to reset the driver when a fault
is detected. FAULT/SD and SYS_FLT are used to
enable or disable the driver or detect driver faults.
Detailed descriptions of these signals can be found in
the data sheet of the drivers (IR2214). Switching of the
inverter leg IGBTs is controlled by firing pulses S3, S4
and S5, S6, and is generated by the dsPIC DSC PWM
modules.
DIGITAL FULL-BRIDGE INVERTER RESOURCE DIAGRAM

A1 (Inverter Series Relay)
UDC+
PGND
S5
S6
A2 (Mains Relay)
R
ACI1M
Power Grid
ACI2M
I
FLT_CLR
FAULT/SD
SYS_FLT
S4
FLT_CLR
FAULT/SD
SYS_FLT
DRIVER
S3
ACO1M
ACO2M
Load
I/O
ADC
PWM
PWM
I/O
I/O
I/O
PWM
PWM
DRIVER
ADC
ACO
KF(1)
ACI
KG(1)
I/O
dsPIC33FJ16GS504
Note 1:
ADC
KF and KG are feedback gain circuits. Refer to Appendix D: Schematics and Board Layout for details.
Table 3 shows the resources used by a dsPIC DSC

device for a full-bridge inverter.
TABLE 3:
RESOURCES REQUIRED FOR A DIGITAL FULL-BRIDGE INVERTER
Signal Name
Type of Signal
dsPIC DSC
Resources Used
ACO
Analog
AN1
0.27V-3.3V
ACI
Analog
AN11
0.15V-3.16V
Analog
AN0
2.5V (nominal)
Digital output
RC10
A2
Digital output
RC0
FLT_CLR
Digital output
RB7
FAULT/SD
Digital input (external interrupt)
RC13 (INT1)
SYS_FLT
Digital input
RC8
S3, S4 (gate drive)
PWM output
PWM1H, PWM1L
S5, S6 (gate drive)
PWM output
PWM2H, PWM2L
A1
DS01279A-page 5
AN1279
FLYBACK SWITCH MODE CHARGER
The block diagram in Figure 7 shows that an analog
current controller is used for battery charging. Four signals are needed: EFB signal for enabling topswitch, (IB)
for measuring battery charging current, (UB) for measuring battery voltage and IREF for reference set with
PWM4L output.
FIGURE 7:
DIGITAL FLYBACK SWITCH MODE CHARGER RESOURCE DIAGRAM

Shunt
UDC+
UBAT
K3(1)
PGND
Flyback
transformer
PGND
UFEEDBACK
+15V
K4(1)
PI
TOPSWITCH
45V
ENABLE
EFB
UB
-
PI
IERROR
IFEEDBACK
IREF
IB
ADC
ADC
PWM
I/O
dsPIC33FJ16GS504
Analog Controller
Note 1:
K1 and K2 are feedback gain circuits. Refer to Appendix D: Schematics and Board Layout for details.
Table 4 shows the resources used by the dsPIC DSC

device for a flyback switch mode charger.
TABLE 4:
RESOURCES REQUIRED FOR A DIGITAL FLYBACK SWITCH MODE CHARGER
Signal Name
Type of Signal
dsPIC DSC
Resources Used
IBATM
Analog
AN4
0V-1.67V
UBAT
Analog
AN5
1.5V-2V
EFB
Digital output
RC7
IREF
PWM output
PWM4L
DS01279A-page 6
AN1279
DC/DC CONVERTER
Selection of a topology depends on careful analysis of

the design specifications, cost and size requirements of
the converter.
Most UPS designs contain a transformer-type DC/DC

converter. The transformer provides electrical isolation
between the input and output of the converter. The
transformer also provides the option to produce
multiple voltage levels by changing the turns ratio, or
provide multiple voltages by using multiple secondary
windings.
Operation of each of the above topologies is described

in the following sections of this application note. Details
of the topology selection and hardware design are
provided in subsequent sections.
Forward Converter
Transformer-type DC/DC converters are divided into

five basic topologies:
A forward converter, which can be a step-up or stepdown converter, is shown in Figure 8. When the
transistor Q is ON, VIN appears across the primary, and
then generates output voltage determined by
Equation 1.
Forward Converter
Push-Pull Converter
Half-Bridge Converter
Full-Bridge Converter
Flyback Converter
The diode D1 on the secondary ensures that only

positive voltages are applied to the output circuit while
D2 provides a circulating path for inductor current if the
transformer voltage is zero or negative. A third winding
is added to the transformer of a forward converter, also
known as a reset winding. This winding ensures that
the magnetization of the transformer core is reset to
zero at the start of the switch conduction. This winding
prevents saturation of the transformer.
The Flyback topology operation differs slightly from

other topologies in that energy is stored in magnetic
material and then released. Other topologies always
transfer energy directly from input to output. Another
case in which topologies are distinguished from each
other is transformer core utilization:
Unidirectional core excitation where only the
positive part (quadrant 1) of the B-H loop is used
(flyback and forward converters)
Bidirectional core excitation where both the positive (quadrant 1) and the negative (quadrant 3) parts
of the B-H loop are utilized alternatively (push-pull,
half-bridge, and full-bridge converters)
FIGURE 8:
FORWARD CONVERTER
T
+
D1
+
D2
VIN
VOUT
-
D3
EQUATION 1:
Vout Vin
N2
d
N1
where d is the duty cycle of the transistor Q
DS01279A-page 7
AN1279
Push-Pull Converter
PWM drive signal), Q2 conducts, current flows through

the lower half of T1's primary, and the magnetic field in
T1 expands. At this point, the direction of the magnetic
flux is opposite to that produced when Q1 conducted.
The expanding magnetic field induces a voltage across
the T1 secondary; the polarity is such that D1 is forward-biased and D2 is reverse-biased. D1 conducts
and charges the output capacitor C2 via L1. After a
period of dead time, Q1 conducts and the cycle
repeats.
A push-pull converter is shown in Figure 9. When Q1

switches ON, current flows through the upper half of
the T1 transformer primary and the magnetic field in T1
expands. The expanding magnetic field in T1 induces a
voltage across the T1 secondary; the polarity is such
that D2 is forward-biased and D1 is reverse-biased. D2
conducts and charges the output capacitor C2 via L1.
L1 and C2 form an LC filter network. When Q1 turns
OFF, the magnetic field in T1 collapses and after a
period of dead time (dependent on the duty cycle of the
FIGURE 9:
PUSH-PULL CONVERTER
D1
T1
+
+ VIN
+
+
+ VOUT
L1
C2
0V
+
D2
C1
Q1
Q2
0V
There are two important considerations with the

push-pull converter:
Both transistors must not conduct together, as this
would effectively short circuit the supply. This
means that the conduction time of each transistor
must not exceed half of the total period (d < 0.5)
for one complete cycle, otherwise conduction will
overlap.
The magnetic behavior of the circuit must be
uniform; otherwise, the transformer may saturate,
and this would cause destruction of Q1 and Q2.
This behavior requires that the individual
conduction times of Q1 and Q2 must be exactly
equal and the two halves of the center-tapped
transformer primary must be magnetically
identical.
EQUATION 2:
Vout 2 Vin
N2
d
N1
where:
d is the duty cycle of the transistors and 0 < d < 0.5
N2/N1 is the secondary-to-primary turns ratio of
the transformer
These criteria must be satisfied by the control and drive

circuit and the transformer. The output voltage equals
that of Equation 2.
DS01279A-page 8
AN1279
Half-Bridge Converter
The half-bridge converter (see Figure 10) is similar to
the push-pull converter, but a center-tapped primary is
not required. The reversal of the magnetic field is
achieved by reversing the direction of the primary winding current flow. In this case, two capacitors. C1 and
C2, are required to form the DC input mid-point. Transistors Q1 and Q2 are turned ON alternately to avoid a
supply short circuit, in which case the duty cycle, d,
must be less than 0.5.
For the half-bridge converter, the output voltage VOUT
equals that of Equation 3.
FIGURE 10:
HALF-BRIDGE CONVERTER
+VIN
C1
D1
T1
Q1
+VOUT
+
+
C3
+
0V
C2
L1
+
Q2
D2
0V
EQUATION 3:
Vout Vin
N2
d
N1
where:
the transformer
DS01279A-page 9
AN1279
Full-Bridge Converter
The full-bridge converter topology shown in Figure 11,
is basically the same as the half-bridge converter,
where four transistors are used.
Diagonal pairs of transistors (Q1-Q4 or Q2-Q3) conduct alternately, thus achieving current reversal in the
transformer primary. Output voltage equals that of
Equation 4.
FIGURE 11:
FULL-BRIDGE CONVERTER
+VIN
Q1
L1
D1
T1
Q3
+VOUT
+
+
C1
C2
+
0V
Q2
Q4
D2
0V
Flyback Converter
EQUATION 4:
Vout 2 Vin
N2
d
N1
where:
the transformer
Figure 12 shows a flyback converter circuit. When transistor Q1 is ON, due to the winding polarities, the diode
D1 becomes reverse-biased. Therefore, transformer
core flux increases linearly. When transistor Q1 is
turned OFF, energy stored in the core causes the current to flow in the secondary winding through the diode
D1 and flux decreases linearly. Output voltage is given
by Equation 5.
FIGURE 12:
FLYBACK CONVERTER
D1
T1
+VIN
+VOUT
C1
+
C2
+
0V
Q1
0V
EQUATION 5:
Vout Vin
DS01279A-page 10
N2 d
N1 1 d
AN1279
VOLTAGE SOURCE INVERTER (VSI)
Full-Bridge VSI
Figure 14 shows the topology of a Full-Bridge VSI. This
inverter is similar to the half-bridge inverter; however, a
second leg provides the neutral point to the load. Both
switches S1+ and S1- (or S2+ and S2-) cannot be on
simultaneously because a short circuit across the DC
link voltage source vi would be produced. To avoid the
short circuit across the DC bus and the undefined AC
output voltage condition, the modulating technique
should ensure that either the top or the bottom switch
of each leg is ON at any instant. The AC output voltage
can take values up to the DC link value vi, which is
twice the value obtained with half-bridge VSI topologies. Several modulating techniques have been developed that are applicable to full-bridge VSIs. Among
them, the best known are bipolar and unipolar PWM
techniques.
A single-phase Voltage Source Inverter (VSI) can be

defined as a half-bridge and a full-bridge topology. Both
topologies are widely used in power supplies and
single-phase UPS systems.
Half-Bridge VSI
Figure 13 shows the topology of a Half-Bridge VSI,
where two large capacitors are required to provide a
neutral point N, such that each capacitor maintains a
constant voltage vi 2. Because the current harmonics
injected by the operation of the inverter are low-order
harmonics, a set of large capacitors (C+ and C-) is
required. The duty cycle of the switches is used to
modulate the output voltage. The signals driving the
switches must ensure some dead time to prevent
shorting of the DC bus.
FIGURE 13:
ii
VI
SINGLE-PHASE
HALF-BRIDGE VSI
+
C+
S+
VI
+
VI
io
N
+
C-
FIGURE 14:
D+
S-
+
VO
-
D-
SINGLE-PHASE FULL-BRIDGE VSI
ii
S1+
VI
+
-
VI
S2+
D2+
io
+
C+
S1-
D1+
D1-
S2-
+
VO
-
D2-
DS01279A-page 11
AN1279
BATTERY CHARGER
When the AC mains voltage is present, the Offline UPS
charges the batteries, and therefore, a battery charger
circuit is implemented.
Most battery chargers can be divided into four basic
design types, or topologies:
Linear Chargers
Switch Mode Chargers
Ferroresonant Chargers
SCR Chargers
Switch Mode Chargers
Linear Chargers
Linear chargers consist of a power supply, which
converts AC power to lower voltage DC power, and a
linear regulating element, which limits the current that
flows into the battery. The power supply typically
consists of a transformer that steps down AC power
from 220/110 VAC to a lower AC voltage closer to that
FIGURE 15:
of the battery, and a rectifier that smooths out the

existing sinusoidal AC signal into a constant-voltage
DC signal. The linear regulating element may be a
passive component such as a resistor or an active
component such as a transistor that is controlled by a
reference signal. Figure 15 shows a simplified
schematic of a linear charger with a linear power supply
with a resistor as the current regulating element.
In a switch mode charger, AC voltage is rectified, and

then converted to a lower DC voltage through a DC/DC
converter. This type of charger contains additional
charge control circuitry to regulate current flow into the
battery. The charge control regulates the way in which
the power switch turns ON and OFF, and may be
accomplished through a circuit, a specialized integrated chip, or some type of software control. A simplified schematic for a single piece switch mode charger
is shown in Figure 16.
LINEAR CHARGER
Transformer
Rectifier
Current
Regulating
Element
Battery
AC Input
R1
Power Supply
FIGURE 16:
DC Output
Charge
Control
SWITCH MODE CHARGER

Rectifier
Power
Switch
Transformer
Output
Filter
Battery
AC Input
DC Output
Power Supply
Current Control
Logic
DS01279A-page 12
AN1279
Ferroresonant Chargers
SCR Chargers
Ferroresonant chargers (sometimes called ferro chargers), operate by way of a special component called a
ferroresonant transformer. The ferroresonant transformer reduces the AC voltage to a lower regulated
voltage level while simultaneously controlling the
charge current. A rectifier then converts the AC power
to DC power suitable for the battery. Figure 17 shows a
block diagram of a ferroresonant charger.
SCR chargers use a special component known as a

Silicon-Controlled Rectifier (SCR) to control the current
to the battery. The SCR is a controllable switch that can
be turned ON and OFF multiple times per second. After
a transformer reduces utility voltage to a value near
that of the battery, the diodes rectify the current while
the SCR enables the flow of charge current according
to a control signal. A block diagram of an SCR charger
is shown in Figure 18.
FIGURE 17:
FERRORESONANT CHARGER
Ferroresonant
Transformer
Rectifier
Battery
Charge
Control
DC Output
AC Input
Power Supply
FIGURE 18:
SCR CHARGER
Transformer
Diode
Rectifier
SCR
Current
Limiter
Battery
AC Input
DC Output
Power Supply
Charge Control
DS01279A-page 13
AN1279
SOFTWARE DESIGN
The Offline UPS Reference Design is controlled by a
single dsPIC DSC device as shown in the system block
diagram in Figure 19.
FIGURE 19:
OFFLINE UPS BLOCK DIAGRAM

Power Conversion Block
Push-Pull
Converter
3x12V Batteries
Auxiliary
Power
Supply
UPS
Output
Full Bridge
Voltage-Source
Inverter
Load
Relay Logic
AC Mains Input Rectified

by Inverter Body Diodes
Flyback Battery
Charger
dsPIC DSC
LCD Controller
PIC18F2420
USB
Controller
PIC18F2450
LCD Module
USB Port
User Interface Block
Legend:
Signal Flow
Power Flow
Computer
The dsPIC DSC device is the heart of the Offline UPS.

It controls all critical operations of the system as well as
the housekeeping operations. The functions of the
dsPIC DSC can be broadly classified into the following
categories:
All power conversion algorithms
UPS state machine for the different modes of
operation
Auxiliary tasks including true RMS calculations,
soft start routines and user interface routines.
The dsPIC DSC device offers intelligent power peripherals specifically designed for power conversion applications. These intelligent power Peripherals include
the High-Speed PWM, High-Speed 10-bit ADC, and
High-Speed Analog Comparator modules.
DS01279A-page 14
These peripheral modules include features that ease

the control of any switch-mode power supply with high
resolution PWM, flexible ADC triggering, and
comparator fault handling.
In addition to the intelligent power peripherals, the
dsPIC DSC also provides built-in peripherals for digital
communications including I2C, SPI and UART that
can be used for power management and housekeeping
functions.
Note:
For device details, refer to the dsPIC33F

GS series device data sheets. For more
information on the peripherals, refer to the
corresponding SMPS sections in the
dsPIC33F Family Reference Manual.
AN1279
A high-level diagram of the Offline UPS software structure is shown in Figure 20. As shown in this figure, the
software is broadly partitioned into two parts:
UPS State Machine (includes power conversion
routines)
User Interface Software
These partitions are described in more detail in
subsequent sections of this document.
FIGURE 20:
OFFLINE UPS SOFTWARE: HIGH-LEVEL PARTITIONS

Offline UPS Software
UPS State Machine
(Interrupt Based)
User Interface Software
Priority: Medium
Execution Rate: Medium
Power Conversion Algorithms
(Interrupt Based)
Priority: Low
Execution Rate: Low
Priority: High
Execution Rate: High
UPS State Machine

The Offline UPS software implements a state machine
to determine the mode of operation for the system. The
state machine is executed once every 100 s inside a
timer Interrupt Service Routine (ISR). The state
machine configures the on-chip peripherals to execute
the correct power conversion algorithms.
During normal operation of the offline UPS, the state
machine configures the system peripherals to execute
the correct power conversion algorithms as determined
by the system state.
When a power failure occurs, the UPS state machine
initiates a switchover sequence from Battery Charger
mode to Inverter mode. When the AC mains is detected
again, the state machine executes the switchover from
Inverter mode to Battery Charger mode. These switchover functions must be executed in as little time as
possible to ensure uninterrupted power to the load.
The Battery Charger mode and Inverter mode are the
two normal operating modes of the Offline UPS. There
are two other modes of operation, namely System
Startup and System Error. Each mode of operation for
the Offline UPS is described in the following sections.
Figure 21 shows the Offline UPS state diagram.
DS01279A-page 15
AN1279
FIGURE 21:
OFFLINE UPS STATE DIAGRAM
M
D AIN
BA C_LI S_O
T T NK K
ER _O &
Y_ K &
LO
W
MA
DC IN
BA _LINS_O
TT K _ K &
ER O K
Y_ &
OK
BATTERY_OVERVOLTAGE
MAINS_NOT_OK
Inverter Mode
MAINS_OK &
DC_LINK_OVERVOLTAGE
MAINS_OK &
DC_LINK_UNDERVOLTAGE
MAINS_NOT_OK &
DC_LINK_OK &
BATTERY_OK
Startup
Battery
Charger
Mode
MA
IN
DC_ S_NOT
BAT LINK_ _OK &
TER OK &
Y_
OK
E
& TAG
OK OL
_
E
O T RV
AG
_N DE
LT
NS _UN
I
O
E
V
MAERY
AG
ER
LT
OV
TT
O
_
A
Y
B
RV
GE
ER
DE
TA
TT
OL
UN
_
V
BA
K
R
IN
VE
_L
_O
K
DC
IN
_L
DC
BA
M
TT AIN
ER S_
Y_ N O
BA
UN T _
TT
DE OK
ER
RV &
Y_
OL
DC
OV
TA
_L
ER
INK
GE
V
_U
DC
OL
ND
TA
_L
INK
ER
GE
VO
_O
VE
LT
AG
RV
OL
E
TA
GE
MAINS_OK &
DC_LINK_OK &
(BATTERY_OK || BATTERY_LOW)
M
D AIN
BA C_LI S_O
TT N K K
ER _ O &
Y_ K &
M
LO
DC AIN
W
S
_
_
BA LIN O
TT K _ K &
ER OK
Y_ &
OK
System
System Error
D
C
_L
IN
O
K_
R
VE
VO
E
E
TAG
A GE
L
RVO
NDE
AG
LT
_U
LINK
DC_
RVO
LT
BATTERY_OVERVOLTAGE
BATT
ERY_
UND
E
System Startup
When the Offline UPS is turned ON, the state of the
system is unknown. Therefore, the state machine first
monitors all system variables and determines the
starting state of the UPS.
During this time, the state machine also monitors for
fault conditions and ensures that all system variables
are within specification so that the UPS can switch to
normal operation.
DS01279A-page 16
AN1279
BATTERY CHARGER MODE
This current reference signal is generated by filtering

the PWM output from the dsPIC DSC. The charging
current is controlled by modifying the duty cycle of the
current reference PWM signal.
If the AC mains voltage is detected, the Inverter mode

is disabled (if running) and the Offline UPS switches to
the Battery Charger mode. The dsPIC DSC device provides the reference current level with a variable duty
cycle PWM signal.
When the Battery Charger mode is started, the dsPIC

DSC device sets up the minimum charging current.
Then, the battery voltage and battery current are measured using the high-speed 10-bit ADC module. The
measured battery voltage determines the charging
state, and the code specifies the correct charging current from the battery charging profile shown in
Figure 22.
The battery voltage is measured to ascertain the state

of the battery. Depending on the battery state, the value
of the charging current is modified so as to achieve the
fastest charging time and also to prolong the life of the
batteries.
The battery charging profile has been configured for
sealed lead-acid (SLA) batteries, and is summarized in
Figure 22.
All system variables are monitored by the state

machine to initiate a switchover sequence if required.
When an AC mains power failure is detected, the state
machine switches the UPS operation to the Inverter
mode. If a fault is detected, the system state is changed
to System Error.
The battery charger control is implemented partly in

hardware and partly in software. A flyback converter IC
is used to produce a constant current source from the
rectified AC mains voltage. The dsPIC DSC device provides the reference signal for the output current of the
flyback converter.
FIGURE 22:
OFFLINE UPS BATTERY CHARGING PROFILE

Charging
Current
Trickle
Charging
State
Charging
Off
Bulk
Charging
State
Over
Charging
State
Float
Charging
State
Charging
Off
2.25A
0.1A
30V
35.7V
40.5V
43.2V
45V
Battery Voltage
Note: Not drawn to scale
DS01279A-page 17
AN1279
BATTERY CHARGER INITIALIZATION
ROUTINE
When the offline UPS switches to the Battery Charger
mode, the code must ensure that the previous mode is
turned OFF. To reduce stress on the hardware
components, the full-bridge inverter is turned OFF
when the output reaches 0V. The flowchart for the
Battery Charger mode is shown in Figure 23.
FIGURE 23:
After the inverter is turned OFF, the output relay is

released so that the AC mains is connected to the UPS
output. The output relay must be released in the shortest possible duration so that there is no interruption of
power at the UPS output. Typically, relay switching
times are the limiting factor for the switchover duration.
BATTERY CHARGER INITIALIZATION FLOWCHART

UPS State Machine
Battery Charger Initialization
Priority: Medium
Push-Pull Control Loop

(ADC Interrupt)
Inverter
Mode
System
Startup
Priority: High
Set Relay flag =
NOT_READY_TO_SWITCH
Inverter Control Loop

(ADC Interrupt)
Priority: High
No
Is relay ready to switch?

(Relay flag cleared in ADC ISR)
Yes
Initiate relay release
Battery Voltage and Current

Measurement
(ADC Interrupt)
Call 4 ms delay to allow inverter

output to become 0V
Turn OFF inverter PWM signals
Bypass DC link charging resistor
Priority: Medium
AC Mains Detection
(ADC Interrupt)
Call 12 ms delay to allow

complete release of relay
Reset charging state to UNKNOWN
and set minimum charging
current reference
Enable charging current
reference signal (PWM4L)
Priority: Medium
Enable Battery Charger

Flyback Converter
Battery
Charger
Mode
DS01279A-page 18
AN1279
The dsPIC DSC device implements a predictive technique to achieve the fastest switchover time possible.
This is done by predicting the relay switching time and
initiating the relay release even before the inverter output has turned OFF. The switchover operation from the
inverter to the AC mains is described in subsequent
sections of this application note.
The battery charging current control scheme is illustrated in Figure 24. The battery charger control routine
is called inside the state machine under the Battery
Charger mode. The battery charging control loop is
therefore executed at the same rate (once every
100 s) and also at the same priority level as the state
machine. The battery current and voltage measurement is triggered using the PWM trigger feature on the
dsPIC DSC device.
BATTERY CHARGER CONTROL SCHEME

The battery charger control loop is implemented in the
state machine.
The measured data is scaled and stored as a variable

in data memory asynchronous to the control loop execution. When the control loop is called, the data is simply read from the data memory and used for control
loop calculations. The flowchart for the battery charger
control loop is shown in Figure 25.
If the measured charging current is less than the reference, the duty cycle is incremented by a fixed step.
Conversely, if the charging current exceeds the reference, the duty cycle is reduced by the same fixed step.
This process continues until the current error reduces
to a negligible value.
FIGURE 24:
BATTERY CHARGER CONTROL SCHEME

Quantizer
+K
Duty Cycle
Charging Current
Reference
0
-K
-1
Measured Charging Current
DS01279A-page 19
AN1279
FIGURE 25:
BATTERY CHARGER MODE FLOWCHART

UPS State Machine
Push-pull control loop
(ADC Interrupt)
Battery Charger Control Loop

Priority: Medium
Battery
Charger
Mode
Priority: High
Yes
Inverter control loop

(ADC Interrupt)
Is battery voltage <

BATTERY_TRICKLE_VOLTAGE?
No
Yes
BATTERY_BULK_VOLTAGE?
Priority: High
Set Maximum
Charging Current
No
Yes
BATTERY_FLOAT_VOLTAGE?

Measurement
(ADC Interrupt)
No
Priority: Medium
AC Mains Detection
(ADC Interrupt)
Priority: Medium
DS01279A-page 20
Yes
Set Minimum
Charging Current
Calculate and set

Charging Current

BATTERY_VOLTAGE_MAX?
No
Turn Charger
OFF
Battery
Charger
Mode
AN1279
BATTERY CHARGER RESOURCE ALLOCATION
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR BATTERY CHARGER
FIGURE 26:
VBAT
AC Input
+
Note 1
GND
kA(2)
kB(2)
ADC
ADC
PWM
dsPIC33FJ16GS504
Note 1:
2:
The AC mains input is rectified by the body diodes of the IGBTs to provide a DC voltage to the battery charger.
KA and KB are feedback gain circuits. Refer to Appendix D: Schematics and Board Layout for details.
The dsPIC DSC device resources used for the battery

charger are summarized in Table 5.
TABLE 5:
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR BATTERY CHARGER
Signal
Name
dsPIC DSC
Resource Used
Description
Type of Signal
IREF
Charging current reference
PWM output
PWM4L
(remapped to pin 35)
25 kHz
IB
Charging current feedback
Analog Input
AN4
6.25 kHz
UB
Battery voltage feedback
Analog Input
AN5
6.25 kHz
EFB
Flyback converter enable
Digital Output
RC7
Activated only when the UPS

switches to Battery Charger mode
Inverter Mode
If the AC mains voltage is not detected, the battery
charger is disabled and the Offline UPS switches to the
Inverter mode. During Inverter mode, the system is
running on battery power and produces a clean
sinusoidal voltage at the UPS output so that critical
electronics can continue operation without interruption.
The sinusoidal output waveform is generated using a
sine lookup table in the data memory. This lookup table
serves as the sinusoidal reference voltage for the
inverter control loop.
Execution Rate/Frequency
When starting Inverter mode, the push-pull converter is

ramped up to the rated DC Link voltage using a softstart routine. The soft-start routine reduces stress on
system components and also prevents voltage and
current surges from the AC mains or the battery.
During normal operation of Inverter mode, the pushpull converter and the full-bridge inverter are controlled
by interrupt-based power conversion algorithms, or
control loops. The control loops are executed at a fast
rate to achieve the best performance. The Inverter
mode power conversion algorithms are the most critical
routines for the dsPIC DSC device; therefore, these
routines are assigned the highest user-priority level.
DS01279A-page 21
AN1279
The state machine, which is also interrupt-based, has a
lower priority than the control loops. As a result, the
execution of the state machine and user interface code
may be interrupted numerous times by the high-priority
control loops.
This operation is possible because the dsPIC DSC
device allows for nesting of interrupts. The interrupt
nesting feature enables the control loops to interrupt
the execution of the state machine. The state machine
execution is relatively slower than the control loops.
The dsPIC DSC device allows for seamless transition
between the power conversion routines and the UPS
state machine, with the use of multiple interrupts of
differing priorities and execution rates.
When operating in the Inverter mode, all system variables are monitored by the state machine. As soon as
the AC mains voltage is detected, the switchover
sequence is engaged and the system state is changed
to Battery Charger mode. If any system variable is in
error, the system state is changed to System Error.
FIGURE 27:
PUSH-PULL CONVERTER INITIALIZATION

When the system switches to Inverter mode, any previous modes of operation must first be disabled. Therefore, the battery charger is first disabled by turning OFF
the flyback converter and also by disabling the PWM
output for battery current reference. The output relay is
engaged to disconnect the AC mains input from the
UPS output, while the inverter series resistor is
bypassed by switching ON the bypass relay. Then, the
push-pull converter control loop is reinitialized and all
control history is purged.
The AC mains input has a wide operating voltage
range; therefore, the value of the DC link voltage is
unpredictable when a mains failure occurs. As a result,
before turning ON the push-pull converter, the most
recently measured DC Link voltage is used as the initial
reference voltage for the push-pull converter. The softstart routine enables the DC Link voltage to be ramped
up at a controlled rate and thus prevents unnecessary
stress on the circuit components due to current spikes.
PUSH-PULL CONVERTER INITIALIZATION FLOWCHART

UPS State Machine
(ADC Interrupt)
Push-pull Converter Initialization

Priority: Medium
Battery
Charger
Mode
System
Startup
Priority: High
Disable Battery Charger

Flyback Converter
(ADC Interrupt)
Turn OFF PWM signal for

battery current reference
Priority: High
Switch output relay to disconnect

Mains from UPS output
Bypass DC link charging resistor

Measurement
(ADC Interrupt)
Re-initialize push-pull control

loop to purge history
Priority: Medium
Set minimum duty cycle before

turning ON PWM outputs
AC Mains Detection
Enable PWM outputs for push-pull

converter (PWM3H and PWM3L)
(ADC Interrupt)
Priority: Medium
DS01279A-page 22
Inverter
Mode
AN1279
SOFT-START ROUTINE
The soft-start routine is called right after enabling the
push-pull converter. The soft-start routine increments
the reference voltage for the push-pull converter in software in fixed steps until the reference reaches the rated
DC Link voltage. At this point, the inverter is enabled by
calling the inverter re-initialization routine to produce a
sinusoidal voltage at the UPS output.
The ramp rate for the DC Link voltage is fixed and the
starting voltage for the soft-start routine is variable,
making the soft-start duration also variable.
The variable duration of the soft-start routine may
cause uncertainty in the mains-to-inverter switchover
time. The ramp rate for the soft-start routine is
configured to be completed in the time required for the
output relay to turn ON. This ensures that the
switchover time is within the design specification of
10 ms.
However, the other situation must also be considered
where the soft-start is completed in less time. In this
case, the inverter output will turn ON before the relay is
given enough time to switch, thereby causing the
inverter output to be turned ON at the UPS output
midway through the sine wave cycle. If the relay is
turned ON after the completion of the soft-start, the
switchover timing would be too slow.
The dsPIC DSC avoids both of these problems by initializing a delay counter at the beginning of the softstart routine. As the soft-start routine is ramping up the
DC Link voltage, the counter is incremented to reflect
the soft-start duration in milliseconds. If the soft-start is
completed before the minimum required time for the
relay turn-on, the code continues to wait until the minimum required switching time has elapsed. Once the
required relay switching time elapses, the full-bridge
inverter is enabled. This technique ensures that uninterrupted power is available at the UPS output at all
times.
DS01279A-page 23
AN1279
FIGURE 28:
SOFT-START ROUTINE FLOWCHART

UPS State Machine
Push-pull Converter Initialization

Priority: Medium
(ADC Interrupt)
Start
Push-Pull
Soft-Start
Priority: High
Initialize delay counter
Set soft-start flag to allow higher

peak currents during startup
(ADC Interrupt)
Priority: High
Increment delay
counter
Increment push-pull
reference
Measurement
No
(ADC Interrupt)
Is Push-pull converter
reference = final setpoint?
Yes
Priority: Medium
Increment delay
counter
AC Mains Detection
(ADC Interrupt)
Priority: Medium
No
Does delay count represent

duration greater than relay
switching time?
Yes
Clear soft-start flag
Inverter
Mode
DS01279A-page 24
AN1279
FULL BRIDGE INVERTER INITIALIZATION
The push-pull soft-start routine ensures that the DC link
voltage is at the rated value and the output relay has
completed the switching event. After the soft-start
routine concludes, the full-bridge inverter must be
enabled to produce a sinusoidal voltage at the UPS
output.
FIGURE 29:
The inverter control loop is reinitialized to purge all control history. The duty cycle is then configured to produce 0V output and the sine wave lookup table pointer
is also reset to the start. At this point, the PWM outputs
are enabled to produce the sinusoidal output voltage.
INVERTER INITIALIZATION FLOWCHART

UPS State Machine
(ADC Interrupt)
Priority: High
Inverter Initialization
Priority: Medium
Inverter
Mode

(ADC Interrupt)
Re-initialize inverter control loop to

purge all control history
Priority: High
Set duty cycle to produce 0V output

Measurement
(ADC Interrupt)
Priority: Medium
Reset sine wave lookup table

to the start
Enable PWM outputs to turn ON

inverter (PWM1H, PWM1L,
PWM2H and PWM2L)
AC Mains Detection
(ADC Interrupt)
Inverter
Mode
Priority: Medium
DS01279A-page 25
AN1279
PUSH-PULL CONTROL LOOP
The voltage mode control algorithm must be executed

at a fast rate in order to achieve the best transient
response. Therefore, the control algorithm is executed
in the ADC interrupt service routine, which is also
assigned the highest priority in the UPS code.
The push-pull converter is controlled with a voltage

mode control scheme. The PWM module in the dsPIC
DSC device is configured for Push-Pull mode with an
independent time-base. The DC Link voltage is
measured by the ADC and converted to a digital value.
This value is subtracted from the voltage reference in
software to obtain the voltage error.
A block diagram of the push-pull converter control

scheme is shown in Figure 30.
The voltage error is then fed into a control algorithm

that produces a duty cycle value based on the voltage
error, previous error, and control history. The output of
the control algorithm is also clamped to minimum and
maximum duty cycle values for hardware protection.
FIGURE 30:
PUSH-PULL CONVERTER CONTROL SCHEME

1:16
VREF
Voltage
Error
PID
Duty
Cycle
Control
Output
PWM
+-
+
Vin
VOUT
1001010111
Voltage Feedback
DS01279A-page 26
ADC
S&H
AN1279
INVERTER CONTROL LOOP
In the Offline UPS, a 3-level control is implemented for

the full-bridge inverter. So the PWM module in the
dsPIC DSC device is set up with a fixed duty cycle for
zero output voltage. Each leg of the full-bridge inverter
is operated in complementary Center-Aligned mode
with dead time. The result of the control loop is added
to the nominal duty cycle for one leg of the full-bridge
inverter and subtracted from the nominal duty cycle for
the second leg.
The inverter output is generated by varying the voltage

reference using a sinusoidal lookup table. The measured output voltage is subtracted from the present reference value and the voltage error is obtained. The
voltage error is fed into the voltage error compensation
algorithm within the ADC interrupt service routine. The
output of the voltage error compensator produces the
current reference value. The measured output current
is subtracted from the current reference to obtain the
current error. The current error is used as the input to
the current error compensation algorithm to produce
the command signal for the PWM module.
FIGURE 31:
A block diagram of the full-bridge inverter control

system is shown in Figure 31.
FULL-BRIDGE INVERTER CONTROL SCHEME
Sinusoidal Reference
X
+
Voltage
Error
PI
Current
Reference Current
Error
X
+
AC Out
PWM
Output Filter
Current
Feedback
1011010011
Duty
Cycle
Control
Output
S&H
1001010111
Voltage Feedback
ADC
S&H
DS01279A-page 27
AN1279
PUSH-PULL CONVERTER HARDWARE AND
SOFTWARE RESOURCE ALLOCATION
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR PUSH-PULL CONVERTER
FIGURE 32:
VDC
Push-Pull Converter
VBAT
GND
GND
FET
Driver
FET
Driver
PWM
PWM
kD
kC
ADC ADC
or
Analog Comparator
kE
dsPIC33FJ16GS504
ADC
The dsPIC DSC resources used for the push-pull

converter are summarized in Table 6.
TABLE 6:
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR PUSH-PULL CONVERTER

Type of Signal
dsPIC DSC
Resource Used
Sample Rate/
Frequency
Push-Pull Drive Signal
PWM Output
PWM3L
100 kHz
S2
Push-Pull Drive Signal
PWM Output
PWM3H
100 kHz
IP
Push-Pull Primary
Current Feedback
Analog Input
AN2
25 kHz
UDCM
DC Link Voltage
Feedback
Analog Input
AN3
25 kHz
Signal
Name
S1
Description
DS01279A-page 28
AN1279
FIGURE 33:
dsPIC DSC RESOURCE ALLOCATION FOR FULL-BRIDGE INVERTER

Full-Bridge Inverter
VDC
VOUT+
VOUT-
GND
IGBT
Driver
IGBT
Driver
IGBT
Driver
IGBT
Driver
PWM
PWM
PWM
PWM
dsPIC33FJ16GS504
kF
kG
ADC
ADC
The dsPIC DSC device resources used for the fullbridge converter are summarized in Table 7.
TABLE 7:
Signal
Name
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR FULL-BRIDGE CONVERTER

Description
Type of Signal
dsPIC DSC
Resource Used
Sample Rate/
Frequency
S3
Inverter Drive Signal
PWM Output
PWM1L
50 kHz
S4
PWM Output
PWM1H
50 kHz
S5
PWM Output
PWM2L
50 kHz
S6
PWM Output
PWM2H
50 kHz
Inverter Output Current

Feedback
Analog Input
AN0
25 kHz
ACO
Inverter Output Voltage

Feedback
Analog Input
AN1
25 kHz
ACI
AC Mains Voltage
Feedback
Analog Input
AN11
25 kHz
A1
Resistor Bypass Relay

Drive Signal
Digital Output
RC10
Activated only at startup

to charge the DC Link
voltage above the
minimum value.
A2
Output Relay Drive

Signal
Digital Output
RC0
Activated only when the

UPS switches to
Inverter mode.
DS01279A-page 29
AN1279
Inverter-to-Mains Switchover Routine
When a power failure occurs, the Offline UPS switches
to the Inverter mode and operates in this mode until the
mains is detected again. The system should switch
from one mode to the other in the shortest possible
duration in order to provide uninterrupted power to the
load.
Before switching to the Battery Charger mode, the software must reliably ensure that the mains voltage
detected is within the specified levels. The software
must also ensure that the mains waveform is clean and
has little or no distortion.
The mains detection routine is divided into the following
steps:
1.
2.
3.
4.
Mains High Voltage Detection: In the Inverter

mode, the UPS software first checks for the
presence of high voltage on the mains. If a high
voltage is detected consecutively for 5 ms, the
mains detection routine proceeds to the next
step.
Zero-Crossing Detection: After a high voltage
has been detected, the software keeps polling
the mains voltage for a zero-crossing detection.
A valid zero-crossing is only detected if the previous voltage is negative and the present voltage is positive, and the difference between the
previous and present measurement is above a
minimum value. This ensures that spurious
zero-crossings are not detected due to noise.
Mains Data Collection: Once the zero-crossing
has been detected, the UPS software enters the
mains data collection step. In this step, every
sample of the measured mains voltage is stored
in an array. Each sample of the collected data is
averaged over four sine wave cycles to ensure
an accurate reference. This array is later used
as the mains reference to detect a mains failure.
Mains Synchronization: After collecting the
mains voltage data, the mains detection routine
now compares the measured voltage with the
mains reference data. If the error is within 20V
consecutively for 8 ms, the software concludes
that the mains is present and indicates the new
state of the AC mains to the state machine.
DS01279A-page 30
The state machine then begins the process of

switching from Inverter mode to Battery Charger mode.
The switchover is engaged at the zero-crossing of both
the inverter and mains. This provides the smoothest
transition from one mode to the other and occurs
instantaneously.
It is possible that the inverter and mains are out of
phase when AC mains is available again. As the frequencies of the AC mains and the inverter are nearly
equal, the zero crossings of the two waveforms may
never align. Therefore, the UPS software first checks
whether the frequencies are very close. If there is a significant difference in frequencies, the two waveforms
will eventually align at the zero crossings, which is
when the UPS will engage the switchover.
If the two signals are operating at nearly the same frequency, the inverter frequency is modified slightly by
discarding some of the samples from the lookup table.
As a result, the zero crossings of the two signals are
forced to align after a few sine wave cycles. This allows
the UPS state machine to switch from the Inverter
mode to the Battery Charger mode with almost zero
latency. The inverter-to-mains switchover sequence is
described graphically in Figure 34.
It is also important to note that the alignment of the zero
crossings must be predicted using information for the
relay switching time. The relay is switched a few milliseconds before the actual zero-crossing so that the
relay switching delay is accounted for.
AN1279
FIGURE 34:
INVERTER-TO-MAINS SWITCHOVER SEQUENCE
High Voltage Detected
Zero-crossing Detected
Start Mains Data

Collection
Mains Data Collection

Complete
Zero-crossing Aligned
AC
Mains
Inverter
Inverter turned
OFF
Inverter
Frequency
Modified
DS01279A-page 31
AN1279
Mains-to-Inverter Switchover Routine
When mains is present, the UPS software keeps comparing the measured mains voltage with the corresponding data in the mains reference array. The
quadrant information is also saved in a variable. On
every sample, the error between the expected voltage
and the actual voltage is calculated.
If the error is detected to be larger than 20V, a count
is incremented. If the error is detected to be outside the
limit consecutively for about 1 ms, then the Offline UPS
detects that a mains failure has occurred. The system
state is changed to Inverter mode and the relay is
switched immediately to disconnect the mains from the
FIGURE 35:
UPS output. The push-pull converter is then enabled

and the soft-start routine is executed. After the softstart routine is complete, the mains voltage is
measured again.
Using a binary search algorithm, the appropriate sample number from the sine lookup table is selected,
which is in the appropriate quadrant and has a value
closest to the mains voltage. The inverter is then
enabled starting at this sample number so that there is
no sudden change in voltage on the UPS output. The
mains-to-inverter switchover sequence is described in
Figure 35.
MAINS-TO-INVERTER SWITCHOVER SEQUENCE

Mains Failure
detected
Mains Failure
Occurred
Push-pull Soft-start
Routine Completed
Inverter turned ON
at the last measured
mains voltage
UPS
Output
Battery
Charger
Mode (AC
Mains
Inverter Mode
Present)
DC
Link
Voltage
DS01279A-page 32
AN1279
System Error
The UPS goes into the System Error state if a combination of the system variables is detected to be in a
fault state. The state diagram in Figure 21 illustrates all
conditions under which a system error is detected.
The dsPIC DSC device has built-in fault and current
limit features that enable automatic shutdown of power
converters with no software overhead. This feature is
critical in power conversion applications and is useful in
protecting the user, system hardware, and downstream
electronics.
The System Error mode is designed to handle any
faults after the respective power stage has been disabled. When the system enters this mode, the type of
fault is displayed on the LCD module. When the UPS
enters the System Error mode, the system needs to be
restarted again before it can function normally.
All non-critical functions of the Offline UPS are categorized as auxiliary tasks. These tasks have a relatively
slow execution rate and therefore are assigned the lowest execution priority in the Offline UPS software.
The auxiliary tasks are executed in the main loop of the
code. These tasks are performed only when other highpriority tasks like power conversion control loops and
the UPS state machine are not active. In other words,
the auxiliary tasks are performed during the idle time
for the power conversion routines and state machine.
As a result, the main loop is also referred to as the idle
loop. The auxiliary tasks are numerously interrupted
by high-priority tasks like the control loops and the state
machine. Each of the auxiliary tasks is described briefly
in the following sections.
OUTPUT VOLTAGE/CURRENT RMS

CALCULATION
The RMS Calculation routine provides the output
voltage and current information for the LCD display
as well as for output overcurrent and output
overvoltage/undervoltage protection.
The measured current and voltage are stored in data
memory in an array of 256 points each. When the RMS
calculation routine is called, the respective array is
passed to the function, while the output of the function
is the true RMS value of the parameter.
Signal
Name
SDO
SDI
SCK
The RMS calculation is called in the idle loop since it is

executed over the AC mains cycle, and therefore,
requires a relatively slow execution rate. The results
are then scaled appropriately to produce a number in
volts or amperes.
In order to display the result on the LCD display, each
decimal digit of the RMS calculation result is stored as
a character variable. The character variables are then
concatenated into a string in order to display the data
on the LCD module.
LCD DISPLAY
Auxiliary Tasks
TABLE 8:
The DSP instructions of the dsPIC DSC device are utilized to efficiently execute the RMS calculation routines. The Q15 library includes functions for calculating
sum-of-squares and square-root. Both of these operations are available in the Q15 library, and are used for
implementing the RMS calculation in the offline UPS
reference design.
The LCD control code for the dsPIC DSC device is

implemented as independent functions for writing pixels, bytes, words, or strings to the LCD module. The
LCD display routines are called in the main loop.
The Offline UPS Reference Design uses a 4x20 character LCD display module controlled by a dedicated
MCU (PIC18F2420). The dsPIC DSC device communicates with the LCD controller via a Serial Peripheral
Interface (SPI).
The dsPIC DSC device is configured as the SPI master
device and transmits all LCD commands to the LCD
controller. The LCD controller converts the serial
commands from the dsPIC DSC device into parallel
data and also manages the timing controls for the LCD
module.
Note:
Operation of the LCD controller is beyond

the scope of this reference design. Visit
www.microchip.com/lcd for LCD design
solutions.
The LCD controller operates with a 5V supply and the

dsPIC DSC operates on a 3.3V supply. However direct
connections between the dsPIC DSC and LCD controller can be made because the digital-only pins of the
dsPIC DSC are 5V tolerant. Also the digital outputs of
the dsPIC DSC can be operated in open-drain configuration and produce logic high for the 5V LCD controller
using just a pull-up resistor.
The resource allocation for LCD control is summarized
in Table 8.
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR LCD DISPLAY

Description
SPI Data Output
SPI Data Input
SPI Clock Output
Type of Signal
dsPIC DSC
Resource Used
Sample Rate/Frequency
Digital Output
Digital Input
Digital Output
RP22
RP19
RP21
156.25 kHz when active

DS01279A-page 33
AN1279
Signal
Name
SS
Description
SPI Slave Select
Output
Type of Signal
dsPIC DSC
Resource Used
Digital Output
RP20
USB COMMUNICATION
The Offline UPS also includes a USB communication
interface to enable power management for a computer
or server connected to the UPS. The USB communication is performed by a separate USB controller MCU
(PIC18F2450). The USB controller communicates with
the dsPIC DSC device via an opto-isolated UART
interface.
TABLE 9:
Asserted only when data is

transmitted to LCD controller
The resource allocation for the USB communication

interface is summarized in Table 9.
dsPIC DSC DEVICE RESOURCE ALLOCATION FOR USB INTERFACE
Signal
Name
Tx
RX
Description
UART Transmit
UART Receive
DS01279A-page 34
Type of Signal
dsPIC DSC
Resource Used
Digital Output
Digital Input
RP27
RP28
9600 bps
9600 bps
AN1279
Fault States and Protection Schemes
Operation with Rectifier Loads
There are a number of fault sources that can cause the

system to turn off all outputs and enter the System
Error mode. Any system fault can trigger the Offline
UPS to enter the System Error mode. These include
the following:
One of the most important applications of the Offline

UPS is to provide uninterrupted power to computers
and servers. Most computers and servers implement a
switch-mode AC-DC power supply that implements
Power Factor Correction (PFC). Such a load usually
contains a front-end bridge rectifier and is therefore
classified as a rectifier load.
Push-pull primary overcurrent

DC Link undervoltage
DC Link overvoltage
Battery undervoltage
Battery overvoltage
Output overcurrent
Overtemperature
If PFC is not implemented, the load appears as a highly

capacitive load, resulting in high peak currents and a
low power factor. A block diagram of the connections
for such a configuration is shown in Figure 36.
The system will enter the System Error mode due to

either a single fault or a combination of faults,
depending on the operating modes. For example, a DC
Link undervoltage condition will not cause the system
to enter the System Error mode if the soft-start routine
is active. Similarly, transient loads may cause the pushpull primary current to exceed the limit for a short
duration. Therefore, a push-pull overcurrent fault will
only be generated if the overcurrent condition persists
for an extended duration.
The typical configuration of such a power supply contains a PFC boost converter as shown in Figure 37.
The boost converter usually contains a large output
capacitor. As seen from the circuit diagram, a low
impedance path exists from the AC input to the output
capacitor. As a result, the output capacitor draws a
large inrush current when the load is first connected to
the UPS output.
All faults that are fast-acting and destructive to the system and user's load are handled in the high-priority
control loops. The push-pull overcurrent fault is an
example of a very high-speed signal that must be
detected as quickly as possible. As a result, this fault is
detected at the same time as the push-pull control loop.
Other signals like the battery voltage are not very highspeed signals and therefore the faults are handled in
the UPS state machine.
When a fault condition happens, the system enters the
System Error mode and the type of fault is displayed on
the LCD module.
FIGURE 36:
TYPICAL RECTIFIER LOAD FOR THE OFFLINE UPS

Computer/Server Power Supply
AC
Offline UPS
UPS
Output
AC
Input
EMI Filter
PFC Boost
Converter
DC-DC
Converter
DS01279A-page 35
AN1279
FIGURE 37:
PFC BOOST CONVERTER
AC
Load
If PFC is not implemented, the current is drawn by the

load in a very discontinuous nature with high peaks,
causing the load to appear highly capacitive, as shown
in Figure 38.
FIGURE 38:
RECTIFIER LOAD INPUT CURRENT WAVEFORMS (NO PFC)

Diode
ON
Diode
OFF
Diode
ON
Diode
OFF
Diode
ON
Diode
OFF
Diode
ON
Input Voltage
Output Voltage
Input Current
DS01279A-page 36
AN1279
Due to the presence of a large capacitor on the output
of the PFC boost converter, the Offline UPS needs to
implement a special algorithm to handle load steps and
startup conditions for rectifier loads.
The current draw during a rectifier load startup can be
up to 20 times the maximum rated current. One option
to support these high current surges is to design the
hardware with sufficient design margin. However, this
approach is usually not cost effective and may also
cause a drop in performance or efficiency. The dsPIC
DSC provides a number of flexible features to overcome this problem. The PWM Current-Limit feature can
be used to limit the current on a cycle-by-cycle basis.
This feature, along with software can help charge the
output capacitor in a controlled manner so that the
inrush current is limited.
In the Offline UPS Reference Design, an external interrupt is generated when an overcurrent condition
occurs. This causes the PWM module to automatically
shut down. Inside the Interrupt Service Routine, the
PWM is configured for a very small duty cycle and then
re-enabled. As the duty cycle is small, the current
drawn during one PWM switching cycle is automatically
limited. The duty cycle is incremented in small steps to
charge the output capacitor in a controlled manner.
While the current-limit fault handling routine is being
executed, the inverter control loop is overridden. The
inverter control loop resumes operation when the sine
voltage reference of the inverter becomes equal to the
actual voltage on the inverter output.
If the first current limit fault is caused by a short circuit
condition on the inverter output, the current limit fault
will be triggered immediately for a second time. This
will cause the system to shut down with an overcurrent
error. The error state is displayed on the LCD display
module and is reset only when the system is turned
OFF and back ON.
Peak Current Limiting Function

If the power factor of the rectifier load is too low, it will
result in a high crest factor for the inverter current. The
Offline UPS Reference Design is rated for a maximum
crest factor of 3:1. If the crest factor of the load exceeds
this value, no action is taken by the UPS if the current
is within the maximum peak current rating. However, a
high crest factor warning is displayed on the LCD
display module.
If the peak current required by the load exceeds 15A, a
current limiting function overrides the inverter control
loop. This function limits the maximum current on the
output by clamping the duty cycle to a maximum value.
DC Offset Elimination
A side-effect of operating with a high crest factor is that
the current drawn may become asymmetric. This is
caused by the presence of a small DC offset on the
inverter output voltage. The DC offset occurs due to the
tolerance limits of the feedback components.
A typical analog implementation requires the use of
trimming resistors to eliminate the DC offset. This
solution requires trimming of each UPS system during
manufacturing, and therefore becomes expensive and
time consuming. It may also need periodic adjustment
via a servicing schedule to account for effects of long
term degradation of components. The dsPIC DSC
helps overcome this problem with an active algorithm
to eliminate the DC offset.
The Offline UPS Reference Design implements an offset elimination routine by comparing the positive and
negative peak of the measured output voltage. If an
imbalance is detected, a correction factor is applied to
the output voltage to cancel the DC offset. The peaks
are determined by averaging the maximum and minimum recorded voltages over a number of sine wave
cycles. Doing so helps to ignore the effects of load
steps on the output.
DS01279A-page 37
AN1279
HARDWARE DESIGN
TOPOLOGIES CONSIDERED AND REASONS

FOR CURRENT CHOICES
Push-Pull Boost Converter
In Figure 39 and Figure 40 all possible push-pull boost

circuits are shown. The combination of a push-pull
inverter (Figure 39(C)) and a full-bridge rectifier
(Figure 40(B)) was chosen, which provides the best
price performance ratio. For the inverter only the lowside drive circuitry is required and simple PWM signals
(see Figure 41) can drive the inverter.
DESIGN SPECIFICATIONS
A push-pull boost converter needs to convert the wide
range battery link input voltage to a stabilized high-voltage DC-Link. The design specifications used in the
Offline UPS Reference Design are:
Input voltage range: 30-45 VDC

Output voltage: 380 VDC
Continuous power: 1 kVA
Peak power for two seconds: 1.3 kVA
Switching frequency: 100 kHz
FIGURE 39:
PRIMARY DRIVE CIRCUITS
Q1
Q2
C1
(A) Full-Bridge Inverter
UB
Q3
Q4
C1
Q1
(B) Half-Bridge Inverter
UB
T1
T1
+
C2
Q3
T1
UB
(C) Push-Pull Inverter

Q
DS01279A-page 38
AN1279
FIGURE 40:
RECTIFIER CIRCUITS
T1
L1
(A) Half-Bridge Rectifier
R1
C1
D1
D2
L1
(B) Full-Bridge Rectifier
T1
D3
C1
D1
FIGURE 41:
CONTROL SIGNALS FOR

PUSH-PULL INVERTER
D4
R1
D2
The output voltage is calculated by Equation 6, where

N2 N1 is the transformer windings ratio, and d is the
duty cycle of the PWM signal. The duty cycle must be
limited to the given boundary. In a real application, the
duty cycle must be limited to 0.1 < d < 0.42. This is
done due to the switching behavior of the MOSFETs
and transformer. Due to allowed oscillation and losses
in the system, the calculation using Equation 6 is not
exact. When no load is applied to the push-pull boost
stage, the controller has to switch into Burst mode, and
when heavy load is applied, the duty cycle must be
increased to compensate for various losses.
EQUATION 6:
For the secondary, a full-bridge rectifier was chosen for
the following reasons:
Reducing the leakage inductance by using only
one secondary winding on the transformer
Reducing cost of transformer
Rectifier diodes can be rated lower in reverse
breakdown voltage, such diodes have better
forward and switching characteristics.
Synchronous rectification is not required due to
high-voltage and low current operation.
N2
U DC = U BAT ------ 2d
N1
where:
the transformer
DS01279A-page 39
AN1279
DESIGN OF POWER-TRAIN COMPONENTS
from FERROXCUBE was selected. From core loss,

maximum flux density can be calculated, as shown in
Equation 7. The factors used in this equation are
provided in Table 10.
The push-pull transformer has been designed using a

ferrite magnetic core. The transformer design is based
using the area product (WaAc) approach and is
designed to meet the following conditions:
EQUATION 7:
Minimum input voltage: Vimin = 30V

Maximum DC link voltage: Vo = 380V
Maximum output power: Pomax = 2000W
Primary RMS current: IPrms = 30.5A
Maximum duty cycle: Dmax = 0.42
Switching frequency: f = 100 kHz
Core loss density is normally selected around 150 mW/

cm3. The calculated maximum flux density must be limited to less than half of B at saturation. This B level is
chosen because the transformer core will develop
excessive temperature rise at this frequency when the
flux density is close to saturation. Maximum flux density
can now be calculated, as shown in Equation 8.
The manufacturers data sheet is used to help select

the appropriate material for the desired application. For
the given range of materials, frequency, core loss, and
maximum flux density of the material should be
considered. From the research data, 3C90 material
TABLE 10:
P l = a f B max
FACTORS APPLIED TO EQUATION 7 (CORE LOSS EQUATION)
Material
Frequency
R, 35G, N87, 3C90
f < 100 kHz
0.074
1.43
2.85
P, 45G, N72, 3C85
F, 25G, N41, 3C81
100 kHz f < 500 kHz
0.036
1.64
2.68
f 500 kHz
0.014
1.84
2.28
f < 100 kHz
0.158
1.36
2.86
100 kHz f < 500 kHz
0.0434
1.63
2.62
f 500 kHz
7.36e-7
3.47
2.54
f < 10 kHz
0.790
1.06
2.85
10 kHz f < 100 kHz
0.0717
1.72
2.66
100 kHz f < 500 kHz
0.0573
1.66
2.68
f 500 kHz
0.0126
1.88
2.29
EQUATION 8:
1000
B max
DS01279A-page 40
1000
----------
----------d
2.68
Pl
150
= ---------------------------c
= ------------------------------------------------= 1339G
1.64
f
100000
a ----------
1000-
0.036 ----------------1000
AN1279
For selecting the right size core, the area product of the
core must be calculated by Equation 9. This equation is
derived from the flux linkage equation ( = N * ) and
represents the power handling ability of the core.
Therefore, each core has a number that is a product of
its window area, Wa, and the core cross-sectional area,
Ac.
FIGURE 42:
HYSTERESIS LOOP OF
MAGNETIC CORE
B
BSAT
EQUATION 9:
BMAX
8
10 P omax
W a A c = ------------------------------K t B f J
B
B in Equation 9 is equal to 2Bmax due to bidirectional
core excitation as seen in Figure 42. Current density of
a winding is estimated to be 500A/cm2, and maximum
output power Pomax is 2000W. Therefore, the calculated
area product is shown in Equation 10.
H
B
BMAX
EQUATION 10:
8
10 2000
4
W a A c = ------------------------------------------------------------------ = 5.9cm
0.254 2678 100000 500
BSAT
The selected core must have an area product larger

than calculated. ETD54 shape and size of a core was
selected with WaAc = 12.6 cm2. A larger size was
selected due to the primary and secondary windings,
which fit to the winding area of that core.
The primary turns are calculated by Equation 11. Given
result is then rounded up or down to the integer value.
In this case it is rounded to 4 turns for one-half of the
primary.
EQUATION 11:
NP
8
2
8
2
10 V imin --- Dmax 10 30 ------------------ 0.42
f
100000
= --------------------------------------------------------- = -------------------------------------------------------------- = 3.4
B AC
2678 2.8
DS01279A-page 41
AN1279
The secondary turns are calculated by Equation 12.
The result is rounded to the value 60 of secondary
turns.
not be much higher due to the short winding. Primary

RMS current is IPrms = 30.5A. Secondary current can be
calculated by Isrms = IPrms * Np Ns = 2.03A.
EQUATION 12:
EQUATION 13:
I Prms
2
A cuP = ------------- = 3.81mm
JP
Vo
380
--------------------------------2D max
2 0.42
N s = ---------------- N p = ------------------ 4 = 60.3
V imin
30
I Srms
2
AcuS = ------------ = 0.41mm
JS
The cross section of the primary and secondary windings is calculated by Equation 13. Different current densities are used (JP = 8A/mm2 and JS = 5A/mm2) to fit the
windings into the transformer bobbin and because the
length of one-half of the primary is very short compared
to the secondary. In that case, it is allowed to use higher
current density for primary as temperature of winding will
FIGURE 43:
Because of the high switching frequency, f = 100 kHz,

litz wire must be selected to reduce winding losses
(losses by skin and proximity effect). Litz wire must also
be designed for that frequency.
Figure 43 shows the transformer winding diagram and
construction diagram.
TRANSFORMER ELECTRICAL AND MECHANICAL CONSTRUCTION
NS
NP
NP
NP
NS
Bobbin
Insulation and Shield
CORE
NP
NP
NP
NS
DS01279A-page 42
AN1279
PUSH-PULL MOSFETS
Peak Current
When choosing the right MOSFETs the following must

be considered:
The peak current must be calculated at maximum

power and the form of the current waveform must also
be taken into account. When we assume that the current waveform will have a sawtooth waveform with the
given duty cycle (d), we can calculate the resulting
peak current using Equation 16. The duty cycle (d) is
calculated using Equation 17.
Maximum Breakdown Voltage

Continuous Current
Peak Current
Package Thermal Performance
Maximum Breakdown Voltage

In the chosen configuration, a MOSFET must be able
to hold more than twice the battery voltage, as
expressed in Equation 14. In this calculation, a safety
factor of 30% overrating was chosen. Therefore, the
selected devices need to have a drain-to-source
breakdown voltage higher than 117V.
EQUATION 16:
I pm
EQUATION 17:
EQUATION 14:
VBRDSS 2VBAT
2 45V 1.3 117V
Continuous Current
To calculate the current rating of the devices, peak and
average currents have to be estimated. The peak and
average currents can be estimated from the power ratings and input voltage. The average current is calculated using Equation 15, where PC is the continuous
power and UBAT is the battery voltage.
EQUATION 15:
I a Pc / U bat
The highest current will flow at the lowest battery
voltage so the continuous current is:
I = 1000W 30V = 33.34A. And per leg, the continuous
drain current is half of this: ID = 16.67A.
Pmax
U bat d
U DC N 2
2 U bat N1
When we use a transformer with windings ratio of 16

the peak current is that of Equation 18:
EQUATION 18:
I pm
2000W
160.3 A
30V 0.416
Therefore, we have to design the MOSFETs for continuous drain current of 16.67A and peak drain current of
160.3A. Because the waveform shape will not be an
exact sawtooth, these calculations are only an estimate. To be on the safe side, these numbers are
increased by 30%.

To design the thermal performance, the rms current
value must be calculated. If the waveform shape and
peak current are known, the rms can be calculated
using Equation 19.
EQUATION 19:
rms
I pc
d
3
The rms current can now be calculated and is shown in

Equation 20:
EQUATION 20:
rms
80.15
2
.416 42.13 A
3
DS01279A-page 43
AN1279
Per leg, the current is half of this: IDRMS = 21.07A . This
is the most critical design consideration; therefore, an
overrating of 50% should be done IDRMS = 21.07A * 1.5
= 31.5A, and all current leading traces and the
transformer should also be rated for this current.
Now the MOSFETs can be selected. In the reference

design, a TO-220 package is used for the MOSFETs.
Typical junction-to-heat sink thermal resistance of
these devices is Rt = 2.5C/W when using silicone
pad insulation.
The conductive losses on the MOSFETS are

calculated using Equation 21.
We will allow a continuous junction temperature of

110C and a heat sink temperature of 60C. From this
and the power dissipation, we can calculate the needed
thermal resistance, which provides the number of
parallel MOSFETs to use.
EQUATION 21:
2
Pc I Drms
RDSon
For a switching frequency of 100 kHz and with the

push-pull configuration also switching, losses have to
be taken into account. If the current waveform is near
sawtooth, turn-on losses can be neglected. Turn-off
losses depend on the peak current and leakage inductance. To limit the voltage spikes at turn-off a voltage
clamp circuit is used. This circuit enables the MOSFETs to operate without RC snubbers. Snubbers are
only used to suppress high frequency oscillation, and
not to dissipate the energy stored in the leakage inductance of the transformer. Therefore, all of the energy is
dissipated on the MOSFETs. Equation 22 can be used
to estimate the power dissipation at turn-off.
The number of necessary devices is calculated as

n = Rt RJH = 2.7. According to the calculation
shown in Equation 25, three parallel FDP2532 devices
from Fairchild Semiconductor were selected.
EQUATION 25:
RJH
50
0.91C / W
Ptot 55
EQUATION 22:
Poff f SW
WL
4
In Equation 22, WL is the energy stored in the leakage

inductance at turn-off and is calculated using
Equation 23.
EQUATION 23:
WL
i2 L
2
A typical transformer in this range should have not

more than L = 0.5 H of leakage inductance.
Therefore, the turn off power would be that of
Equation 24:
EQUATION 24:
Poff 100e3
1.6e3
40W
4
Total dissipation on the MOSFETS is then Ptot = Poff +

PC, and it is estimated to be 55W per leg.
DS01279A-page 44
AN1279
FULL-WAVE RECTIFIER
FIGURE 44:
RECTIFIERS WITH CURRENT FLOW

L1
T1
D3
D4
(A) D3 and D2 Conduct

D1
C1
R1
C1
R1
D2
L1
T1
D3
D4
(B) D1 and D4 Conduct

D1
When selecting diodes, the following must be

considered:
Diode Breakdown Voltage

Average Forward Current
Peak Forward Current
Switching Characteristics
Diode Breakdown Voltage

The transformer secondary voltage is calculated as
VS = VBAT * N2 N1. The maximum secondary voltage
at the highest battery voltage is VS = 45 * 16 = 720V .
Because of transformer leakage inductance, diode
internal inductance, and DC link inductor inductance,
voltage spikes appear on diodes when switching. Due
to this, the calculated breakdown voltage is increased
by 30% and should be more than 936V.
D2
Average Forward Current

Average forward current per leg is easily calculated
using Equation 26 from the desired DC link voltage and
continuous output power.
EQUATION 26:
I avg
Peak Forward Current

Peak current is calculated using the transformer
current ratio and peak MOSFET current previously
calculated in Equation 9.
EQUATION 27:
I pD I P
Pc 1000
2.6 A
VDC 380
N1
160.3 0.625 10 A
N2
DS01279A-page 45
AN1279
Switching Characteristics
Diode switching characteristics are determined by
forward recovery time and reverse recovery time.
FIGURE 45:
DIODE SWITCHING CHARACTERISTICS

i[A]
u[V]
tfr
PDoff
PDon
t1
t[s]
t3
t2
Diode switching
Equation 28.
loss
can
be
estimated
using
EQUATION 28:
Total power loss is estimated by adding conduction

losses and switching losses, as shown in Equation 29.
EQUATION 29:
PswD Qc VDC f SW
For diodes, an isolated TO-220-2 package is used.
Continuous working junction temperature should not
exceed 130C at a heat sink temperature of 60C. Typical thermal junction-to-heat sink resistance of the junction-isolated TO-220-2 package is Rt = 3.5C/W.
Therefore, the maximum allowed power dissipation per
part is PMAX = 70 3.5 = 20W.
The STTH1210DI from STMicroelectronics meets the
voltage and current requirements. Power loss calculation can now be done looking at the diode data sheet.
Ptot PswD PfD 10W

The estimation shows that the power losses are within
the set criteria.
Output Inductor
This inductor is optional and is not required. Its use
depends on the transformer construction and control of
DC-link voltage, and the inductor value that must be
used. This section describes the design of a 50 H
output inductor.
The design of the output inductor uses the area product
approach with the following conditions:
Inductance: L = 50 H
Peak DC current: Ip = 13A
Operating flux density: Bm = 300 mT
Current density: J = 500A/cm2
Window utilization: Ku = 0.4
First, the energy handling capability must be calculated

by Equation 30.
DS01279A-page 46
AN1279
EQUATION 30:
L I p2
2
EQUATION 34:
50 106 132
0.0043Ws
2
Then, to select the appropriate size of ferrite core, the

area product calculation must be done, as shown in
Equation 31.
EQUATION 31:
2 E 104
Wa Ac
1.43cm 4
Bm J K u
The selected core was the P36/22 pot core from FERROXCUBE due to its small size and shape, which produces less interference into surrounding components.
The area product of this core is 1.46 cm4 and can be
calculated from the data in the manufacturers data
sheet.
The number of turns required to get the desired
inductance of the coil is calculated by Equation 32. The
Core cross section Ac = 172 mm2 is obtained from the
manufacturers data sheet.
EQUATION 32:
LIp
Ac Bm
12.6
The calculated number of turns is then rounded to the

nearest integer value, which is 13.
To get the desired inductance, 3C81 material with an
air gap was selected to control the flux density. If an air
gap is distributed into the magnetic path of the core, the
effective permeability of material changes and inductance factor AL. From the AL value and number of turns,
the inductance is calculated by Equation 33. The AL
value is obtained from the material data sheet and is
315 nH at 0.97 mm air gap.
EQUATION 33:
L N 2 AL 53 H
The new operating flux density is verified by
Equation 34 and must be lower than the saturation
point of the selected material.
Bnew
LIp
N Ac
308mT
The 3C81 material has a saturation point at 320 mT

(100oC).
If the criteria are not fulfilled, different material, air gap,
number of turns, or even a bigger core must be
selected.
The cross-section of a wire is calculated by
Equation 35, where RMS current through the inductor
is calculated from primary RMS current of push-pull
transformer and turns ratio. This current is twice as
large as primary because for half of a switching period,
the first primary winding is conducting and in the other
half, the second primary winding.
EQUATION 35:
Acu
I rms
2 I Prms
NP
NS
0.82mm2
The calculated value is the minimum cross-section of a

wire (100 kHz litz wire must be used).
Next, the fill factor must be calculated by Equation 36.
This provides an estimation of whether the winding fits
into the bobbin. The fill factor must be 0.4 or less.
Wb is the bobbin winding area and is 72.4 mm2, and
can be found in the core data sheet.
EQUATION 36:
Ku
N Acu
0.15
Wb
Output Capacitors
When choosing DC-link capacitors, the following must
be considered:
Voltage Rating
Ripple Current
Voltage Rating
The voltage rating is defined by the DC Link voltage:
VDC = 380V. Therefore, the capacitors must be above
this rating.
DS01279A-page 47
AN1279
Ripple Current
EQUATION 39:
When the DC link voltage controller is working as

expected, the low frequency ripple current caused by
the inverter is negligible. Therefore, the capacitors
need only compensate for the reactive load current,
which depends on the device specifications:
S = 1300VA and P = 1000W.
EQUATION 37:
Q S 2 P 2 830.7Var
EQUATION 38:
Ir
Q 830.7
3.6 A
230
VAC
SNUBBERS
Snubbers are used to dampen high frequency oscillation and reduce ringing losses on diodes. Snubbers on
the primary side are placed across the primary windings and are not used to handle voltage spikes at turnoff of the MOSFETs. They only reduce ringing and
transformer in-rush current.
To design the snubber for the primary side, the
capacitance of the MOSFETs and leakage inductance
of the transformer must be known. Both parameters
can be measured; however, MOSFET capacitance is
voltage dependent so only an estimate can be used. In
our case, the capacitance of three parallel MOSFETs is
approximately CDS = 7 nF, and leakage inductance of
the transformer is estimated at LS = 500 nH. A
simplified high frequency circuit is shown in Figure 46.
FIGURE 46:
HIGH-FREQUENCY CIRCUIT
RS
LS
.5 H
RC
CDS
6.6 nF
The resonant
Equation 39.
DS01279A-page 48
frequency
is
calculated
1
2.7 MHz
2 CDS LS
Damping of the system is very low because of the low

primary winding resistance (RS) and the series
resistance of the battery link capacitors (RC), which are
both in the range of milliohms. To reduce this high
frequency ringing, a series RC snubbers were added
across the primary winding. The capacitance should be
one to three times the capacitance of the MOSFETs,
and the series resistor value should be chosen so that
it grants damping and the power dissipation is within
the resistor rating. To maintain high efficiency of the
system we allow less than 1% of the rated power to be
dissipated on the primary snubbers. The final values of
the RC snubber are evaluated by experimenting and
are C = 10 nF and R = 12. The power rating of the
resistors is 4W.
To design the snubbers for the rectifier diodes, the
capacitance of the rectifier diode must be known. The
simplified high frequency circuit is shown in Figure 47.
FIGURE 47:
HIGH-FREQUENCY CIRCUIT
LSS
CD1
L1
CD3
Here, the capacitor should be in the range from two to

five times the capacitance of the diode. The diode
capacitance can be found in the diode data sheet. For
the selected diodes it is approximately CD = 70 pF.
Therefore, a good starting capacitance value for the
snubber is C = 150 pF. Here we will also limit the maximum waste power to 1% of the rated converter power
to keep the efficiency of the converter as high as possible. Thus, the resistor ratings will also be 4W. The
resistor value should be selected so that the main
switching voltage signal will produce as low as possible
dissipation on the resistor. The dissipation is dependent on the RC frequency characteristics, and selecting
lower resistance or lower capacitance will shift the
characteristic frequency of the RC circuit higher, which
result in the 100 kHz switching voltage producing less
dissipation on the snubbers. However, damping of the
snubbers will also decrease. A good starting value for
the resistor is R = 1 k.
using
AN1279
Calculating the required snubber circuit is very complex
and does not give the expected results. Therefore, the
parameters have to be evaluated by experimenting.
When designing the snubbers the following must be
considered:
To ensure low resistance in the ON state the gates are

driven with 12V signals. The drive circuit is shown in
Figure 48, which consists of the driver shown as S1,
slope control elements, equalization resistors R1, R2,
R3, R4, R5, and C1 turn-off voltage clamp circuit D1,
D2, Q4, R6.
Overall system efficiency

Signal quality
Device power ratings
Device voltage ratings
The elements R5 and C1 are optional. R5 is used to

ensure the MOSFETs do not turn on by themselves. C1
is used to compensate for Miller capacitance and EMI
control. Resistors R1, R2, and R3 are used to equalize
the gate threshold voltage of the MOSFETs to ensure
parallel turn-on. In combination with R4, the turn-on
slope is also controlled. In addition, the turn-off slope is
controlled until the drain-to-source voltage (VDS)
reaches the voltage clamp circuit threshold. When the
voltage clamp circuit becomes active, VDS stays constant and the turn-off slope is reduced. This enables
part of the energy stored in the leakage inductance to
be transferred to the secondary side and the other part
to be dissipated in a controlled fashion by the MOSFETs. Also, overall system oscillation is reduced due to
lower current slopes. However, it must be considered
that the turn on time of the MOSFETs will increase and
that the maximum duty cycle must be reduced.
Design of Drive Circuitry

To drive the MOSFETs, a driver must be used that
amplifies the signal from the dsPIC DSC device and
drives the gates of MOSFETs. The gate of a MOSFET
behaves like a capacitor. The MOSFET drain-to-source
RDS depends on the gate to source voltage, VGS. The
higher the gate-to-source voltage, the lower the drainto-source resistance of the MOSFET. For the selected
MOSFETs:
VGS = 20V
VGS(TH) = 2-4V
CG(TOT) = 10.7 nF
Driver continuous supply current is calculated using

Equation 40. Where n is the number of parallel
MOSFETs.
FIGURE 48:
MOSFET DRIVE CIRCUIT

T
D1 Zener
Q4
R6
D2
S1
+ V1
12V
R1
Q1
R2
Q2
R3
Q3
R4
R5
C1
EQUATION 40:
I Gc 2 n CG (tot ) VDRV f SW 2 3 10.7 109 15 100 103 96.3mA
DS01279A-page 49
AN1279
Peak current estimate is calculated using Equation 41.
EQUATION 41:
I Gp
VDRV VGS (TH )

R 4 ( R11 R 21 R31 ) 1
Driver power dissipation calculation is shown in the

MCP14E3/MCP14E4/MCPE5 4.0A Dual High-Speed
Power MOSFET Drivers With Enable (DS22062) data
sheet. The total power dissipation is calculated to
approximately Ptot = 1W.
Thermal Design
The heat produced by the MOSFETs and diodes must
be transferred to ambient air using heat sinks. Total
power loss estimation which were performed earlier
are:
For MOSFETs, PMOS = 110W
For diodes, PDIODE = 40W. Forced air cooling is
used to dissipate the heat
Full-Bridge Inverter
INVERTER DESIGN SPECIFICATIONS
Design of Voltage and Current Feedback

Circuitry
The inverter is used to generate the UPS output voltage. The specifications are:
For the push-pull stage, battery link, and DC link voltage, measurements are needed. Both measurements
are done differential with the MCP6022 rail-to-rail operational amplifiers. When taking high voltage differential
measurements, the input resistance must be high and
voltage and power rating of the resistors must not be
exceeded. Because of this, 1206 resistors are used on
the input dividers in the reference design. The output
signal for the differential amplifiers is 5V to increase
SNR. Then, a resistor divider is used near the dsPIC
DSC to interface to the 3.3V, 10-bit A/D converter. In
addition, a capacitor is placed near the dsPIC DSC to
enable fast charge of the S&H capacitor. For measurement, 1% tolerance resistors are used. This is especially important for the differential amplifiers to
guarantee the same resistance in both arms to reduce
common mode noise rejection.
The MOSFET drain current and heat sink temperature

are also measured. The current measurement is based
on the voltage drop measurement on the drain-tosource resistance, RDSON. This type of measurement
is temperature dependent so a semiconductor
temperature sensor is placed which has nearly the
same temperature dependency as the MOSFET,
RDSON. The current feedback signal is used to prevent
the transformer from saturating.
PCB Layout Considerations

For the push-pull stage, special care should be taken
with traces leading the primary current. High frequency
currents and high current peak values can produce a
lot of noise and even losses on the PCB. Therefore, the
traces should be as short as possible and they should
contain no sharp edges. It is a good idea to connect the
primary windings with the transformer litz wire that is
used for winding the transformer (fly leads).
Care should be taken to not couple the power and
signal parts with the ground planes.
DS01279A-page 50
Input voltage : 380 VDC

Output voltage: 230 VACrms
Continuous power: 1 kW
Continuous output current: 5.6 Arms
Peak power for 2 seconds: 1300 VA
Maximum output current: 10 Arms
Switching frequency: 50 kHz
Short circuit-proof
INVERTER POWER-TRAIN DESIGN

IGBT Selection
Due to the high switching frequency, IGBTs with low
switching losses must be selected. Their voltage rating
should be 600V with a current rating of 14A or more
continuous. The STGP14NC60KD from STMicroelectronics was chosen and fulfils all of the selected criteria.
Loss estimation can be done using information in the
data sheet and is estimated at P = 17W. The estimated
junction-to-heat sink resistance using SilPad is:
Rt = 3C/W. According to these estimates, the junction temperature will raise 50C above the heat sink
temperature.
The IGBT inverter also acts as a full-wave rectifier
when charging the battery from the power grid.
Output Common-mode Choke

The common mode inductor has two windings on the
same core. It is called common mode because it blocks
common mode interference and switching noise
produced by the inverter to the output. A schematic of
the inductor is shown in Figure 49. The dot on the
windings indicates the start of a winding. When load is
connected to the output, the flux in the core must be
summed; otherwise, the inductor is connected
incorrectly.
AN1279
FIGURE 49:
COMMON MODE INDUCTOR

SCHEMATIC
EQUATION 44:
N
I1
LIp
Ac Bm
39.9
O1
Input
I2
Output
The calculated number of turns is the number for both

windings. The number is rounded to the value of 40, so
that both winding have an equal number of turns, which
is 20.
O2
To get the desired inductance, the AL value is

calculated by Equation 45.
EQUATION 45:
Design of the output common-mode choke is the same
design of that of a DC inductor, with the following
conditions:
Inductance: L = 250 H
Peak AC current: Ip = 17A
Operating flux density: Bm = 380 mT
Current density: J = 500A/cm2
Window utilization: Ku = 0.4
Output power: Po = 1000W
First, the energy handling capability

calculated, as shown in Equation 42.
L
156nH
N2
Now, from the core manufacturers data sheet the

correct air gap can be selected. For the Epcos N87
material, the air gap length is calculated with
Equation 46.
EQUATION 46:
must
be
EQUATION 42:
L I p2
AL
250 106 17 2
0.036Ws
2
After that, to select the appropriate size of the core, the

area product calculation must be done, as shown in
Equation 43.
A k2
s L 3.3mm
k1
The gap is chosen from the data sheet to be 3.5 mm.
The new AL value must be calculated for the new air
gap by Equation 47.
EQUATION 47:
AL K1 s K 2 148nH
EQUATION 43:
2 E 104
Wa Ac
10.3cm 4
Bm J K u
The selected core is an Epcos ETD54 ferrite core. The
area product of that core is 11.5 cm4, and can be calculated from the dimension data in the manufacturers
data sheet.
The number of turns required to get the desired inductance of the coil is calculated by Equation 44. The core
cross-section, Ac = 172 mm2, is obtained from the
manufacturers data sheet.
The new inductance value is shown in Equation 48.
EQUATION 48:
L N 2 AL 237 H
The new operating flux density is verified by
Equation 49 and must be lower than the saturation
point of the selected material.
DS01279A-page 51
AN1279
EQUATION 49:
Bnew
Output Relays
LIp
N Ac
360mT
N27 material has a saturation point of 410 mT (100oC).

The cross section of the wire is calculated by
Equation 50, where RMS current through the inductor
is calculated from the output power and the RMS value
of the output voltage.
EQUATION 50:
Po
I rms 230V
Acu
0.88mm 2
J
J
The calculated value is the minimum cross-section of a
wire (100 kHz litz wire must be used).
Next, the fill factor has to be calculated by Equation 51.
This will give an estimate if the windings will fit into the
bobbin. The fill factor must be 0.4 or less. Wb is the bobbin winding area and is 315.6 mm2. This information
can be found in the core data sheet.
EQUATION 51:
Ku
N Acu
0.11
Wb
Output Capacitor Selection

The Inverter switching transistors produce the
sinusoidal pulse width modulated voltage waveform
that has a fundamental frequency of 50 Hz or 60 Hz.
The low-pass filter comprises an output inductor and an
output capacitor to pass only the low-frequency
component (50 Hz or 60 Hz) of the sinusoidal pulse
width modulated voltage waveform, in order to produce
a low-frequency sinusoidal output voltage.
The value of the output capacitor must be large enough
to pass the fundamental frequency and low enough so
that it should need high reactive current. To get a cutoff frequency of ~100 Hz, the value of the output capacitor selected is 4.7 F. The output capacitor should be
able to take the high inductor ripple current as well as
suppress the switching noise. The B32924C3475M
MKP series film capacitor from Epcos fulfils all of the
selected criteria.
DS01279A-page 52
Two relays are used in the system. Relay K1 is used to

control charging of the DC link capacitors from the
power grid. During operation this relay is always on.
Relay K2 is used for switchover when the power grid
fails. This relay must have a fast switchover time so
additional components are used to reduce the
switchover time. The R||C combination of R68 and C43
is used to allow high current at turn-on, and then
reduce current during the ON state to allow for faster
turn-off. Resistor R72 is used to deplete the energy
stored in the relay coil for faster turn-off. Transistor
Q11s switching speed is increased using R-C||R
combination, which allows for a higher base current at
turn-on and negative voltage on the base current at
turn-off.
DESIGN OF GATE DRIVE CIRCUITRY

A half-bridge driver with fault- and short-circuit protection must be used to fulfill the design specification. The
selected IGBT can withstand a short circuit of 10 s. If
the driver detects a short-circuit, it will perform a soft
turn-off for the IGBTs. In addition, a bootstrap with a
600V floating channel is needed to drive the high-side
IGBTs. To be able to meet the EMI requirements, the
turn-on and turn-off slopes should be tunable with gate
resistors. The IR2214 from International Rectifier
meets all of these requirements. Looking at the data
sheet of the IGBTs the allowed gate voltage is VGMAX
= 20V and the gate threshold voltage is VG(TH) = 4.56.5V. The driver is supplied by VCC = 12V to ensure
IGBT turn-on. To ensure that the IGBT does not turn on
due to internal IGBT Miller capacitance when VCE
rises with high slope, gate to collector capacitors are
used.
DESIGN OF VOLTAGE AND CURRENT

FEEDBACK CIRCUITRY
For voltage feedback, differential amplifiers are used,
which are built with the MCP6022 operational amplifier.
To measure power grid and output voltage, bipolar
measurements are needed. To enable the differential
amplifiers to measure a bipolar signal voltage, an offset
of Voff = 2.5V is used as the positive reference point.
Therefore, the operational amplifier gives 2.5V to its
output when the differential measured voltage is zero.
When the differential measured voltage is negative, the
output goes to 0V and conversely, the output voltage
goes to 5V when the measured differential voltage is
positive.
AN1279
Because of the high differential input voltage, a series
of 1206 resistors were used to stay within the voltage
and power rating of the devices. All of the resistors
used were 1% tolerance to guarantee the exact measurement and reduce common mode noise rejection.
For current measurement, a Hall effect-based sensor
from LEM is used. The sensor is bipolar and signal
output is 0.5V. At zero current, the output is 2.5V.
For all of the 5V signals, a resistor divider was
added near the dsPIC DSC to interface with the 3.3V
10-bit A/D converter. In addition, a capacitor was
added near the dsPIC DSC to fast-charge the SH
capacitor.
PCB LAYOUT CONSIDERATIONS

Traces leading the output current should be held as
short as possible. Special care should be taken
because of high voltage. Around the IGBT driver the
logical level and gate drive components should be separated, and care should be taken to not couple the
parts with ground planes.
THERMAL DESIGN
IGBTs must be placed on a heat sink to dissipate the
produced heat. Total power dissipation is estimated as
PIGBT = 68W. The devices must be mounted on the heat
sink using thermal conductive and electric insulating
material.
Battery Charger Design

DESIGN SPECIFICATIONS FOR BATTERY
CHARGER SPECIFICATIONS
A battery charger is used to charge the batteries from
the power grid. Three series lead acid batteries were
used in the system. The charger design specifications
are:
Input voltage: 95-260 VAC

Output voltage: 30-45V
Output current: 0-2.5A
Current control
Voltage limit
The clamping elements are designed using design

tools from the manufacturer of the TOP250Y.
Flyback Transformer
The flyback transformer is designed to the desired output power and output current ripple, to enable current
source operation. For the flyback converter, a transformer with air gap is needed. The transformer is
designed for the following conditions:
Minimum DC link voltage: Vimin = 130.6 V

Maximum DC link voltage: Vimax = 364 V
Nominal DC link voltage: Vinom = 247.4 V
Nominal duty cycle: dn = 0.24
Output current: Io1max = 2.5A
Nominal output voltage: Vo = 40V
Secondary current ripple: Is[%] < 25 %
Switching frequency: f = 132 kHz
The primary to secondary turns ratio is calculated with

Equation 52.
EQUATION 52:
N PS (
Vinom VDSon
d
) n 1.9
VO VDf
1 dn
To limit the current ripple, the inductance of primary and

secondary windings must be calculated with
Equation 53.
EQUATION 53:
LS
(Vo VDf ) (T TON max )
LP LS N PS 2
Is
684 H
196 H
Now, the primary current can be calculated with

Equation 54, where transformer efficiency is estimated
at 90%, and for secondary current with Equation 55.
DESIGN OF POWER-TRAIN COMPONENTS

To realize the flyback converter primary drive stage, an
integrated solution TOP250Y from Power Integrations
was selected. Maximum output power is calculated as
PCH = UBmax * IBmax - 112.5W . The flyback works
with a switching frequency of f = 132 kHz. Therefore, a
fast rectifier and primary clamp diode must be used.
The transformer ratio is N2 N1 = 28 52. Based on
this ratio and the maximum input voltage, the rectifier
reverse voltage rating should be higher than the result
of Equation 66, where VF(IGBTD) is the voltage drop
across the IGBT anti-parallel diode, which are used for
power grid voltage rectification.
DS01279A-page 53
AN1279
EQUATION 54:
I S
I Sc
(VO ) (T Ton max )

I O I S % 1A
LS
IO
4A
(1 d max )
I Speek I Sc
I S
4.5 A
2
I S rms (1 d max )( I Speek ( I Sc
I S
I
1
) ( I Speek ( I Sc S ))2 3.2 A
2
3
2
EQUATION 55:
I P
I Pc
(Vi min ) Ton max

0.55 A
LP
VO I O
2.4 A
(Vi min ) 0.9 d max
I Ppeek I Pc
I P
2.7 A
2
I Prms d max ( I Ppeek ( I Pc
I P 1
I
) ( I Ppeek ( I Pc P )) 2 1.5 A
2
3
2
Now, the required wires for primary and secondary can

be selected. We will design the flyback transformer to
run a current density of J = 4 A/mm2. Therefore, the
required copper area for the primary and secondary
can be calculated with Equation 56 (litz wire for
132 kHz must be used).
EQUATION 56:
I Prms
0.375mm 2
J
I
Srms 0.8mm 2
J
ACuP
ACuS
The selected core needs to have a higher area product

than what has been calculated. From the magnetics
side, ETD34 and above will be sufficient; however,
there needs to be enough space to fit the windings. For
this in iterations for different cores, the number of turns
and from this the window utilization and fill factor has to
be calculated. If the window utilization is higher than
90% or a fill factor higher than 0.4, the windings will not
fit. The transformer construction winding diagram and
mechanical diagram are shown in Figure 50.
A winding factor of K = 0.2 is selected for the transformer and N87 material for the core. The maximum
core flux density is set to B = 130 mT. To select the
core, the area product has to be calculated with
Equation 55.
EQUATION 57:
Wa Ac
100 PO max
0.65cm 4
Kt 2 B f J
DS01279A-page 54
AN1279
FIGURE 50:
TRANSFORMER ELECTRICAL AND MECHANICAL CONSTRUCTION

Primary
Secondary
Primary
NP
NS
Bobbin
Insulation and Shield
CORE
NP
Primary
Secondary
Primary
For the windings, litz wire is used to grant low copper

losses at high frequency. For switching frequency f =
132 kHz, a litz wire made of AWG38 wires is used to
eliminate skin and proximity effect. The required number of parallel wires is calculated with Equation 58.
EQUATION 58:
nwP
ACuP
47.7
ACuw
nwS
ACuP
101.8
ACuw
For both, we have to select standard litz wires. So, for

the primary, 45xAWG38 is selected and for the secondary, 105xAWG38 is selected. The diameter of selected
wires with silk isolation is DP = 1 mm and DS = 1.5 mm.
For the used ETD39 core with an air gap, the required
number of turns can now be calculated from the
required primary inductance, turns ratio, and core data.
EQUATION 60:
N tP
25
25 25
DP
N tS
25
16.7 16
DS
EQUATION 61:
N lP
NP
2.32 3
N tP
N lS
NS
1.875 2
N tS
The window utilization is shown in Equation 62 and fill

factor in Equation 63.
EQUATION 62:
Primary turns are calculated with Equation 59.
Wu ( DP N lP DS N lS ) / Wa 86%
EQUATION 59:
NP
NS
104 LP I Ppeek
2 B Ae
58.1 58
NP
30.5 30
N PS
Now, the window utilization and fill factor can be calculated for the selected core and wires. The bobbin window is 25x7 mm. From this we can calculated how
many turns for the primary and secondary
(Equation 60) and the number of required layers
(Equation 61).
EQUATION 63:
K u ACuP N P ACuS N S / Wa 0.25

According to this the windings fit to the selected core.
The required air gap can be calculated from the core
data sheet. To calculate the required air gap the AL
value of the core has to be calculated. The AL value is
air gap dependent. From knowing the primary inductance and number of winding turns, the required AL
value can be calculated with Equation 64.
DS01279A-page 55
AN1279
EQUATION 64:
AL
L
203.3nH
N2
Now, from the core manufacturer data sheet, the correct air gap can be selected. For the used EPCOS
ETD39 N87 core, the correct air gap is calculated with
Equation 65.
EQUATION 65:
1
k2
A
s L 0.95mm
k1
The nearest standard air gap values are 0.7 mm and
1 mm. Our calculated value is close to 1 mm so we
select an air gap of 1 mm and do not need to change
the windings. If an air gap of 0.7 mm is selected, the
number of winding turns must be corrected.
Battery Selection
The battery selection will depend on the DC voltage
and the required backup time of the Offline UPS
system. The Offline UPS Reference Design has been
designed for 36V input DC voltage, being able to
produce one hour of backup time with a 35 AH battery.
VOLTAGE, CURRENT AND TEMPERATURE

SENSE CIRCUITRY
The battery charger works as a current source delivering the requested charge current to the battery, independent of battery voltage. For current measurement
and control, a resistor and a high-side current shunt
monitor (INA168 from Texas Instruments) were used.
For current control, a discrete analog PI controller was
built that controls the duty cycle of the TOP250Y. In
addition, the measured current is fed through a differential amplifier stage to the dsPIC DSC device. Parallel
to the current feedback loop, a voltage feedback loop is
used to limit the output voltage in case the battery is not
connected. In addition, a header is placed on the PCB
to interface with a temperature sensor to monitor the
battery temperature and allow battery management
software to know the state of the batteries.

Precaution must be taken due to high voltage signals.
Also the primary clamp components should be placed
as near as possible to the transformer and the
TOP250Y to reduce stress of the switching components. Care should also be taken to not couple the
power, control, and measurement parts with ground
planes.
THERMAL DESIGN
The top switch and rectifier diode must be mounted on
a heat sink. Assuming efficiency of the battery charger
to be 70%, nearly 50W of loss will be dissipated. Those
losses consist of clamp losses, transformer losses,
primary switch (TOP250Y), and rectifier losses.
Therefore, we can estimate that near 30W of losses
need to be dissipated on the heat sink. Both elements
TOP250Y and the rectifier diode must be mounted on
the heat sink using thermal conductive electrical
insulating material.
EQUATION 66:
VBR ( rect ) Vin 2
DS01279A-page 56
N2
28
Vbat 2 VF ( IGBTD ) 260 2 45 2 1.3 240.4V
N1
52
AN1279
Design of Auxiliary Power Supply
CONCLUSION
DESIGN SPECIFICATIONS
The Microchip dsPIC DSC device provides all of the

necessary power peripherals used for power conversion applications. Its highly flexible Intelligent Power
Peripheral (IPP), ADC, Comparator, and PWM modules simplify the hardware schematic and reduces the
number of components in the design of a high-performance UPS system. The built-in DSP engine and IPP
help in optimizing control loop design, being able to
produce a clean sine wave output (THD less than 3%)
even with a rectifier load and a crest factor of 3:1.
The auxiliary power supply provides power, which is

taken from the battery link, to all of the on-board
electronics. The design specifications are:
Input voltage: 30V-45V
Output: 150 mA @ 3.3V, 300 mA @ 5V, 500 mA
@ 12V
CHOICE OF COMPONENTS
Because of a wide range of input voltage and power
losses, a buck converter was used to generate 12V
from the battery voltage. For 3.3V and 5V, linear
regulators are used because of simplicity and price. All
the voltage regulators are connected in series so the
12V buck converter needs to deliver 1A of current. For
the buck converter, an LM5575 from National
Semiconductor was used with the switching frequency
set at f = 500 kHz. Components were selected
according to the LM5575 data sheet. For the linear
voltage regulators, power dissipation must be
calculated to select the right package in the PCB
layout. For the 5V regulator, maximum power
dissipation is calculated to P5V = (VIN - VOUT) * IOUT =
3.15 mW and for 3.3V to P5V = (VIN - VOUT) * IOUT = 255
mW. For the 5V regulator, a (KE7805ER) TO-263
package with a PCB mount heat sink was selected, and
for the 3.3V regulator, a (TC1262) SOT223 package
was selected. For the analog circuits, additional chip
inductors and capacitors were added to separate digital
and analog supply voltages.
The auxiliary power supply will start when DC link
voltage is present or when the button is pressed.

For the buck converter, due to very high frequency current, care should be taken when designing the output
traces. The inductor, Schottky diode, and low-ESR output capacitors should be as close as possible to the IC.
Also input capacitors should be placed close to the IC
to block the noise produced by the buck converter.
With the help of optimized instruction sets, like MAC,

there is enough time left to perform all of the auxiliary
tasks, fault protection, housekeeping, and communication with the external world. The dsPIC33F enables
power conversion design with all advance features
within the target price.
REFERENCES
MCP14E3/MCP14E4/MCPE5 4.0A Dual HighSpeed Power MOSFET Drivers With Enable
(DS22062), Microchip Technology Inc.
TC1262 500mA Fixed Output CMOS LDO
(DS21372), Microchip Technology Inc.
Power Electronics Converter, Applications and
Design by N.Mohan, T.M. Undeland, and W.P.
Robbins
Control Topology Options for Single-Phase UPS
Inverter by M.J Ryan, W.E. Brumsickle, and R.D.
Lorenz, IEEE transaction on industry application,
Vol. 33, No. 2, March/April 1997.
A Current Mode Control Technique with Instantaneous Inductor Current Feedback for UPS
Inverter by H.Wu, D.Lin, D. Zhang, K. Yao,
J.Zhang, IEEE transaction, 1999.
A High Performance Sine Wave Inverter Controller with Capacitor Current Feedback and BackEMF coupling by M.J Ryan and R.D. Lorenz,
IEEE transaction, 1995.
For linear regulators, adequate PCB and copper area

must be provided to keep the devices cool.
DS01279A-page 57
AN1279
NOTES:
DS01279A-page 58
AN1279
APPENDIX A:
SOURCE CODE
Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the Company) is intended and supplied to you, the
Companys customer, for use solely and exclusively with products manufactured by the Company.
The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.
Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR
STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE
FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
All of the software covered in this application note is

available as a single WinZip archive file. This archive
can be downloaded from the Microchip corporate Web
site at:
www.microchip.com
DS01279A-page 59
AN1279
APPENDIX B:
CONTROL SYSTEM
DESIGN
The Offline UPS Reference Design implements full digital control of the push-pull converter and full-bridge
inverter. MATLAB was used to design the compensators based on the hardware and to generate optimal
coefficients to be used in the software.
MATLAB SIMULINK
The simulation files contain the models for various subsystems. Some subsystems are presented as nested
blocks to simplify the main diagram. Simulink provides mathematical blocks for the time domain simulations.
There are typically two models in each file.
Analog implementation
Digital implementation
Each SIM file analog implementation typically consists
of the following sections:
Reference Block
Feedback System Block
Power System Block
Control System Block
Modulation Inverse Block
Modulation Block
Load System Block
Special Blocks
The Simulink blocks will vary based on the converter

topology and control scheme implemented (i.e., current
mode, voltage mode). The following sections describe
each block used within the models.
REFERENCE BLOCK
C circuit. The system implementation of L and C is

based on integrators and saturations. The input is
typically voltage given by the modulation block
(conversion of duty ratio to actual excitation voltage).
Depending on the topology, the power system block will
change. Parasitic components such as capacitor ESR
and inductor DCR are included in the system here. In
addition, loading of the system will be accounted here.
CONTROL SYSTEM BLOCK

This block generates the duty ratio that drives the
power section block. The feedback signals from the
feedback block is the input and the output as a number
between 0 and 1, which represents the duty cycle ratio.
This block may consist of various cascaded PID loops
based on the control scheme (voltage mode or current
mode control). In digital implementation integrators and
differentiators are replaced by their digital equivalents.
MODULATION INVERSE BLOCK

This block may be part of the control system block as it
converts the output of the PID loops from voltage and
current quantities to duty ratio quantities between 0 and
1. Different topologies have different implementations.
Typically, it involves division with a voltage quantity
(e.g., input voltage for buck converter and output
voltage for boost converter). It is just the inverse
operation of modulation performed by the physical
system in converting duty ratio into voltage.
These models typically have a division with a voltage
quantity (divisor) with little variation. Sometimes in software these routines are not implemented, but in an
actual system, the quantity is assumed to be constant
and gains are prescaled appropriately.
MODULATION BLOCK
This system provides the input for the control system.

Typically, it is only a DC constant for DC-DC converters
or a sine wave generator for UPS-type models. The
control system is required to track the reference waveform. This block may or may not be labeled as such in
the actual models.
This block represents the average model of the switching system. This block converts the duty applied to
physical system to voltage quantity. Its input is the duty
cycle ratio /parameter (0 to 1) that gets converted to
voltage quantity. It usually takes the system input voltage and duty cycle as input and generates an output
voltage.
FEEDBACK SYSTEM BLOCK
LOAD SYSTEM BLOCK
Various signals are typically measured in a system.

These include the voltages and currents for performing
the control operations.
This block is used to generate different types of load

current. For example, a step load with DC offset can be
created, which is useful for step loading. Sinusoidal
loads for UPS-type systems with variable phase (inductive, resistive, etc.), amplitude, and frequency can also
be used depending on the choice of test conditions.
In digital implementation, additional blocks may be

needed to account for quantization due to the presence
of an ADC and zero order holds for sampling the signal
at a constant frequency.
POWER SYSTEM BLOCK

This is the actual physical system. This system
represents energy states and is what actually gives the
output to be controlled. Typically, it will consist of an L-
DS01279A-page 60
SPECIAL BLOCKS
Second order effects like saturation of inductor and
dead-time are modeled for systems where these
become important like UPS. These are indicated by
saturation and dead-time blocks.
AN1279
MATLAB .m File
Depending on implementation, input voltage may be

assumed constant and lumped together with some of
the gains.
The .m file is used to generate the coefficients that are

used in the MATLAB model (.mdl). It also generates
the scaled values to be used in the software. The generated values are in fractional format. In software they
must be represented as Q15(x), where x is a fractional
value.
Bode plots are generated by the .m file for a graphical

representation. The following are typical plots:
Loop gain plot (A x ) this is used to determine
phase and gain margin
Closed loop plot (A x ) / (1 + A x ) or Vo / Vo*
used to determine the closed loop response and
bandwidth of the system
Disturbance rejection plot Io(s) / Vo(s) used to
determine the stiffness of the system and
expected amount of voltage ripple when a load is
applied as a function of frequency
The following parameters are typically used:
The input voltage

L (equivalent inductor value)
C (equivalent capacitor value)
ESR (capacitor ESR)
LSR (lumped series resistance includes tracks +
switch + cable resistance, etc.)
Push-Pull Compensator
Based on the topology used, these parameters can

vary from the actual values. For example, if three converters are in parallel, then simulation is performed for
a single converter (instead of (3x) the capacitor value,
only a single capacitor is modeled and the inductor
value will remain the same).
For the push-pull converter, a PID control algorithm

has been implemented using voltage mode control.
This means that the output voltage is measured and
compared to a reference set point. The difference is
then passed through the PID compensator. The PID
control algorithm will look at the error, the previous
error, and the control history to determine the output
value. The output of the PID will determine the ON
time for the PWM duty cycle. Figure B-1 provides a
push-pull converter control scheme.
The input voltage may vary especially when

transformers are involved. Typically, all quantities are
then referenced to primary or secondary based on
convenience. In either case, the input voltage will vary.
FIGURE B-1:
PUSH-PULL CONTROL SCHEME

1:16
VREF
Voltage
Error
X
+
PID
Control
Output
Duty
Cycle
PWM
+
VIN
VOUT
1001010111
Voltage Feedback
ADC
S&H
DS01279A-page 61
AN1279
Figure B-2 shows the MATLAB Simulink block
diagram. For further details of each block refer to the
MATLAB (.mdl) file.
FIGURE B-2:
MATLAB DIGITAL IMPLEMENTATION (PUSH-PULL)

VO
390
VO*1
540
VIN D
VO*
Digital
Control System
D
VIN.D
VIN1
Buck Modulation1
L_C
Voltage
iLoad
VO1
IL
L_C Circuit1
Scope1
VIN1
Out1 In1
ADC
VO ILOAD
Inverter Load Generator1
x
Product3
Expected Input
Current1
The following bode plots are generated from the

MATLAB (.m) file. Each plot is used to describe the
behavior of the system. The disturbance rejection plot
is defined as: I(s) / VO(s).
Figure B-3 describes the amount of load current amplitude needed to be applied to generate one unit voltage
sag as a function of frequency. The higher this absolute
figure of merit, the stiffer (better) the power supply will
be. The minimum is -4 db, which will correlate to a 1A
load producing 1.5V dip on the output.
FIGURE B-3:
DS01279A-page 62
DISTURBANCE REJECTION PLOT (PUSH-PULL)
AN1279
The loop gain voltage plot shown in Figure B-4 is used
to find phase and gain margin. From the plot it can be
seen that the phase margin (difference between 180
degrees and the phase angle where the gain curve
crosses 0 db) is 90 degrees.
To prevent the system from being conditionally unstable, it is imperative that the gain plot drops below 0 db
when the phase hits 180 degrees.
The blue curve is for the analog implementation and
the green curve is for the digital implementation. It is
generally recommended to have a phase margin of at
least 40 degrees to allow for parameter variations.
The gain margin is the difference between gain curve
at 0 db and where the phase curve hits 180 degrees.
The gain margin (where the green line on the phase
plot hits 180 degrees) is -20 db.
FIGURE B-4:
LOOP GAIN VOLTAGE PLOT (PUSH-PULL)
DS01279A-page 63
AN1279
Figure B-5 shows the closed loop bode plot. The point
where the gain crosses -3 db or -45 degrees in phase
is usually denoted as the bandwidth. In this system, the
bandwidth of the voltage loop is approximately 1250 Hz
(8000 rad/s), which is closely matched by the bode plot.
FIGURE B-5:
CLOSED LOOP (PUSH-PULL)
Full-Bridge Inverter Compensator
rent reference value. The measured current value is

subtracted from the reference and the difference is
passed to the current error compensator (P). The output of the compensator is used to control the PWM outputs. Current mode control is the preferred method as
it has better transient response and stability of the output. However, current mode control is usually harder to
implement as there are two control algorithms instead
of just one as in voltage mode control.
Current mode control has been implemented for the

Inverter using two control algorithms: PI and P.
In current mode control, the current as well as the voltage is measured. The inverter output is generated by
varying the input voltage reference using a sinusoidal
lookup table. The difference is passed through the voltage error compensator (PI) and the output is the cur-
FIGURE B-6:
FULL-BRIDGE INVERTER CONTROL SCHEME
Sinusoidal Reference
X
+
Voltage
Error
PI
Current
Reference Current
Error
X
+
AC Out
PWM
Output Filter
Current
Feedback
1011010011
Duty
Cycle
Control
Output
S&H
1001010111
Voltage Feedback
ADC
S&H
DS01279A-page 64
AN1279
Figure B-7 shows the MATLAB Simulink block diagram
for the inverter. For further details of each block, refer
to the MATLAB (.mdl) file.
FIGURE B-7:
MATLAB DIGITAL IMPLEMENTATION (INVERTER)
Sine Wave
(input variation)
++
VO
VIN
390
IL
Dtop
Dtop
VIN
VO*
Sine Wave
VO*1
Zero-order
Hold2
ILoad
Digital
Control System1
ILZX
VIN
(2.D-1)
Full-Bridge
Modulation Model1
Out1 In1
++
Out2 In2
++
D.VIN VO
iLoad IL
L_C Circuit1
Scope2
Out1
The disturbance rejection plot as previously described

in the Push-Pull section is defined as: I(s) / VO(s).
For the inverter, the minimum is -30 db, which implies
that for 1A load amplitude @ 1000 Hz (6280 rad/s), the
output voltage will exhibit a sinusoidal variation of 31V.
FIGURE B-8:
DISTURBANCE REJECTION PLOT (INVERTER)
DS01279A-page 65
AN1279
Figure B-9 shows the loop gain bode plot for the
inverter. From the plot, it can be seen that the phase
margin (difference between 180 degrees and the
phase angle where the gain curve crosses 0 db) is 47
degrees.
The gain margin is the difference between the gain
curve at 0 db, and where the phase curve hits 180
degrees. In the plots below, the gain margin (where the
green line on the phase plot hits 180 degrees) is -10 db.
FIGURE B-9:
Figure B-10 shows the closed loop bode plot for the
inverter. The point where the gain crosses -3 db or -45
degrees in phase is usually denoted as the bandwidth.
In this system, the bandwidth of voltage loop is 1250 Hz
(8000 rad/s), which is closely matched by the bode
plots.
FIGURE: LOOP GAIN VOLTAGE PLOT (INVERTER)
FIGURE B-10: FIGURE: CLOSED LOOP (INVERTER)
DS01279A-page 66
AN1279
Scaling
The gains calculated from MATLAB are based on real
units (volts, amps, etc.). The dsPIC DSC has a fixed
point processor and the values in the processor have a
linear relationship with the actual physical quantities
they represent.
The gains generated by MATLAB being in real units,
cannot be directly applied to these scaled values (representation of physical quantities). Therefore, for consistency, these gains themselves need to be scaled.
The following sections present general concepts
behind proper scaling.
The basic idea behind scaling is quantities that need to
be added or subtracted should be of the same scale.
Scaling does not affect the structure of the control system block diagram in any way. Scaling only effects the
software representation of various quantities.
SCALING FEEDBACK
To properly scale the PID gains, it is imperative to
understand the feedback gain calculation. The feedback can be represented in various formats. Fractional
format (Q15) is a very convenient representation.
Fractional format allows easy migration of code from
one design to another with completely different ratings
with most changes only in the coefficients defined in the
header file.
To completely use the 16 bits available in the
processor, the Q15 format is most convenient as it
allows signed operations and full utilization of the
available bits (maximum resolution). Other formats are
also possible, but resolution is lost in the process. Q15
allows us to use the fractional multiply MAC operation
of the dsPIC DSC effectively.
The feedback signal (typically voltage or current) is
usually from a 10-bit ADC. Based on the potential
divider/amplifier in the feedback circuitry, actual voltage
and currents are scaled.
Typically, the feedback 10-bit value (0 -1023) is brought
to +/- 32767 range by multiplying by 32. This format is
also known as Q15 format: Q15(m) where -1 < m < 1
and is defined as (int) (m * 32767).
These formulas will have some error as we need 2^15
= 32768, but due to finite resolution of 15 bits we use
only +/- 32767. From a control perspective, for most
systems these hardly introduce any significant error.
As an example, we are trying to measure 100V. We

have a potential divider such that 100V would give
1.65V on the analog pin. Then, the value read in Q15
format is 16383 or Q15(0.5), which is equivalent to
Q15(100 / 200). Therefore, 200 becomes the base
voltage.
The base (or normalizer) is denoted as VN. In other
words, VN is the voltage that will produce 3.3V or fullrange voltage on the analog ADC pin.
At this point, voltage has been scaled as a fraction
(V / VN) in software.
Similarly, other physical quantities that are read via
ADC feedback are also represented in Q15 format.
GAIN SCALING
In simulation the control gains are calculated in real
units. For example, in current mode control, the output
of voltage loop is the current reference (in amps).
Therefore, the gain is Amps/Volts or in units of 1/ohms:
V Gain IREF
The goal is to obtain IREF in an appropriate format like
Q15(I/IN) to enable implementation of the current loop
in software.
In theory, the Q15 voltage V/VN is first multiplied by
VN, and then gain (G), and then the IREF that is
obtained is divided by IN to get current in the correct format. Since VN and IN are constants, the gain
G is scaled as: G * VN / IN. This value can be used
in software to act on voltage quantity and give out a
current quantity.
The input quantity should be in fractional format (this
has to be ensured in code). Then, the output current
quantity will automatically be in the correct fractional
quantity. This essentially solves the objective of
scaling. The same logic applies to any control block.
By considering the input and output units and scale of
each block to be implemented in software, the proper
scaled values can be arrived at.
SAMPLING TIME
In calculation of the derivative and integral term in the
discrete time domain, TS (sampling time) factors show
up. Since sampling time is usually constant, it can also
be lumped together with the gains. For example, if GS
is the integral gain in real units, GS * TS * VN / IN is the
scaled value.
In this format, +32767 corresponds to +3.3V and 0

corresponds to 0V.
The feedback circuitry and the left shift by 5 (x32) is
effectively taking the physical quantity and dividing it by
a larger base quantity. The fractional value is then represented as Q15 in software. Our goal is to find that
larger base quantity.
DS01279A-page 67
AN1279
PRESCALER
Modulation and Duty Generation
As most physical quantities are represented as Q15

format for easy multiplication with gains, the gains also
need to be in fractional format. If the value of gain
(G * VN / IN) is between -1 and +1, it can be easily
represented as fractional format.
The output of a control system after saturation is

brought to 0-32767. Based on the topology, this can be
interpreted as a duty ratio/modulation index
representing 0-1. This can then be used to convert to a
duty cycle value by multiplying it with the PWM period.
This varies with topology, but the idea behind scaling is
the same.
Multiplications can then be performed using

fractional multiply functions like MAC or using
builtin_mul functions and shifting appropriately.
For example, z = (__builtin_mulss(x,y) >> 15)
results in z = Q15(fx,fy), where all x, y, and z are in
Q15 format (fx and fy are the fractions that are
represented by x and y).
In many instances, the gain terms are greater than
unity. Since 16-bit fixed point is a limitation, a prescaler
may be used to bring the gain term within the +/- range.
For example, if the value that needs to be used is 2.5,
it is predivided by 4 to bring it within 1 range.
If a prescaler is used for P term in a control block, it also
must be used for the I and D term in the control block
as all of the terms get added together.
Again, the following equation can be used where

PERIOD corresponds to 100% duty :
Duty = ( __builtin_mulss(m, PERIOD) >> 15)
Division By VIN
The output of the controller in the MATLAB model is
usually a voltage quantity. This needs to be converted
to a duty/modulation quantity. To do this, the control
output needs to be divided by the input voltage VIN. To
avoid division, VIN can be assumed to be constant and
1/VIN can be used as a constant multiplier and bundled
along with the gains in the previous blocks.
To prevent number overflows, PID output and I output

individually have to be properly saturated to 32767.
The saturation limits for the PID output must be set at
one-fourth of the original 32767 to account for the
prescaler. Therefore, they are set at 8192.
Finally after saturation, the output has to be postscaled
by 4 to bring it to proper scale again.
DS01279A-page 68
AN1279
APPENDIX C:
ELECTRICAL
SPECIFICATIONS
This Appendix provides an overview of the UPS electrical specifications as well as scope plots from initial test
results.
TABLE C-1:
Parameter
OFFLINE UPS REFERENCE DESIGN ELECTRICAL SPECIFICATIONS

Description
Min
Typ
Max
Units
VIN
Input Voltage
210
220
242
fIN
Input Frequency
47
50
53
Hz
VOUT
Output Voltage
fOUT
Output Frequency
49
50
51
Hz
Battery Input Voltage
34
36
45
POUT
Continuous Output Power
1000
VA
OLP
Over Load Protection
>100
135
1350 VA for 2 seconds

Full load (resistive)
VBATTERY
THD
tTRANSFER
ICHARGE
I_BATTERY
T
220
Comments
Output Voltage THD
Battery Charger Mode

System Efficiency
84
Inverter Mode System Efficiency
84
Mains to Inverter Transfer Time
10
ms
Inverter to Mains Transfer Time
ms
Battery Charge Current
2.5
Battery Input Current (note 1)
40
Operating Temperature
25
CF
Crest Factor
3:1
PF
Power Factor (Inductive Load)
.65
Power Factor (Rectifier Load)
.65
Note 1:
>50% load
@ 100% load
Only tested at .8 PF
UPS run time will vary with output load current and the batteries discharge rate. Refer to the battery data
sheet for specific discharge times.
DS01279A-page 69
AN1279
FIGURE C-1:
EFFICIENCY CHART ACROSS LOAD SPECTRUM

220V UPS Efficiency Chart
90
Percentage (%)
85
80
75
70
65
60
10
25
50
60
70
80
90
100
% Load
FIGURE C-2:
DS01279A-page 70
OUTPUT VOLTAGE WAVEFORM NO LOAD
AN1279
FIGURE C-3:
OUTPUT VOLTAGE AND OUTPUT CURRENT FULL LOAD
FIGURE C-4:
OUTPUT VOLTAGE AND OUTPUT CURRENT 500 VA REACTIVE LOAD
DS01279A-page 71
AN1279
FIGURE C-5:
MAINS TO INVERTER SWITCH OVER 400W LOAD
FIGURE C-6:
INVERTER TO MAINS SWITCH OVER 400W LOAD
DS01279A-page 72
AN1279
FIGURE C-7:
DYNAMIC LOAD RESPONSE 400W UNLOAD
FIGURE C-8:
DYNAMIC LOAD RESPONSE 400W LOAD STEP
DS01279A-page 73
AN1279
APPENDIX D:
FIGURE D-1:
DS01279A-page 74
SCHEMATICS AND BOARD LAYOUT
OFFLINE UPS REFERENCE DESIGN BOARD LAYOUT (TOP)
Charger-
P2
IC4
1206
390k
R109
R108
1206
390k
R102
1206
390k
R100
1206
390k
R99
1206
390k
TOP250YN (TO220-7)
PGND
C82
0.22uF 630V
PGND
Charger+
P4
R97
4.7nF 1000V
C83
T2
DNP
C84
R98
DNP
PGND
Q14
BC817
R110
12k
C88
DNP
R114
4k7
PGND
100nF 100V
TP14
EFB
47uF 25V
C89
R107
6.8e
ETD39 Flyback transformer N1:N2 = 52:28 Lp=700uH
BYV26E
D26
6k8 4W
W2
2
X
3
F
5
R105
180e
C85
100uF 100V
100V
12V
C143
100nF
R104
3k3
1k5
R115
GND
GND
C91
12V
100nF 25V
47nF
C93
U7A
LM358
D49
Zener 47V
1SMB5941BT3G
R101
3k3
BAR43C PGND
D27
Q12
BC817
PGND
C86
0.68uF 100V
GND
R202
2k2
R113
10k
R111
24k
TP13
8
4
Udc
8
4
GND
C92
1uF
U7B
LM358
Iref
GND
R106
R103
6.8k 1%
GND
GND
Uch
C144
12V
100nF 25V
R112
2k2
C147
1uF
Ibatm+
GND
1k5 1%
Ibatm-

5
U6
INA168
R96
0.33e 5W
Ubat
Imax=2.5A
Vmax=48V
FIGURE D-2:
D25
STTH8R06D
AN1279
OFFLINE UPS REFERENCE DESIGN SCHEMATIC (SHEET 1 OF 8)
DS01279A-page 75
SDI
SDO
SCLK
SS
GND
dsICSPD
R15
DNP
D30
DNP
S2
DNP
R26
DNP
R206
DNP
3V3
GND
D33
DNP
R127
DNP
DNP
D34
GND
R201
DNPC140
100nF
ICSP
No galvanic isolation!
Do not connect when UPS is connected to AC Line!
dsICSPC
3V3
AGND
0e
BR4
GND
S5
S6
S1
S2
10uF 6V Tant
C139
10e
R207
FLT_CLR
11
10
PWM2L
PWM2H
PWM3L
PWM3H
VDDCORE
Vss
RP19
RP22
RP21
RP20
PGC1
C25
1uF
dsI CSPC
2
4
6
EPP
44
3V3
100nF
C94
1uF
C99
C141
100nFAGND
3V3A
dsI CSPD
41
1
3
5
40
P3
43
RP6
13
PWM 1H
12
S4
GND
38
PS
RP5
PWM 1L
S3
42
RP15
RP16
14
A2
RP8
RP29
15
FAULT/SD
39
VDD
AVSS
16
Vss
/SYS_FLT
3V3
C142
100pF
dsVpp
10k
R118
GND
18
AVDD
17
EFB
37
RP24
MCLR
19
Iref
35
Tb
36
RP23
RP2 7
TX
20
AN9
RP2 8
RX
PWM4L
34
PWM4H
AN1
22
AN0
21
I
DS01279A-page 76
ACo
AN2
AN3
AN4
AN5
AN11
AN10
VDD
Vss
AN8
OS CI
OSCO
23
24
25
26
27
28
29
30
31
32
33
IP
Udcm
Ib
Ub
ACi
A1
3V3
1
1uF
GND
100nF
C98
C97
U15
dsPIC33FJ16GS504
R116
20MHz
Y1
10k
12pF
L10
Q15
IRLL2705
4.7uH 1.5A
GND
GND
GND
R11712pF
1M DNP
C96
C95
AR1
100
ES1B
D29
12V
C59
C22
10uF 25V
1uF 25V
e10
FAN
1
2
P_FAN
FIGURE D-3:
dsVpp
AN1279
E2
GND
C102
33pF
R131
1M
GND
C103
33pF
R136
10k
5V
C101
2.2nF
Y2
7.3728MHz
2
1
GND
BTN
R122
10k
5V
GND
DB6
DB7
A0
E1
VPP
8
19
5V
2
3
4
5
6
7
10
9
LCD
GND
R130
10k
E1
DB0
DB2
DB4
DB6
2
4
6
8
10
12
14
16
18
20
A0
E2
DB1
DB3
DB5
DB7
5V
PIC18F2420-E/SO
VSS
VSS
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
OSC2/CLKO/RA6
OSC1/CLKI
U8
1
3
5
7
9
11
13
15
17
19
P5
R120
10k
R123
4k7
R121
4k7
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5/PGM
RB6/PGC
RB7/PGD
VDD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
LED1
LED2
DB0
DB1
DB2
DB3
DB4
DB5
ICSP C
ICSP D
GND
C104
100nF
11
LED1
12
LED2
13
14
15
16
17
BTN
18
5V
20
21
22
23
24
25
26
27
28
D31
4k7
R134
5V
0R
0R
R133
0R
R132
0R
R129
R203
DNP
R126
DNP
R128
R204
DNP
1
2
R125
DNP
1
3
5
P6
2
4
6
5V
ICSP D
GND
R135
DNP
ICSP
No galvanic isolation!
Do not connect when UP S is connected to AC L
ICSP C
P_BZ
R124
DNP
5V
GND
Vpp
SDI
SDO
SCLK
SS
ine!
FIGURE D-4:
C100
100nF
R119
220e
AN1279
DS01279A-page 77
PGND
C146
1uF 25V
DSL2
LON2
LOP2
SDDL2
DSL1
LON1
LOP1
SDDL1
S4
S3
FLT_CLR
/SYS_FLT
FAULT/SD
PGND
GND
12V
PGND
C145
1uF 25V
GND
R46
4k7
GND
S6
S5
FLT_CLR
/SYS_FLT
FAULT/SD
PGND
GND
12V
FLT_CLR
GND
R43
4k7
GND
R44
4k7
1206
1e
R67
IR2214
1206
HIN
LIN
FLT_CLR
/SYS_FLT
/FAULT/SD
Vss
SSDL
COM
LON
LOP
Vcc
DSL
U5
1e
R66
IR2214
HIN
LIN
FLT_CLR
/SYS_FLT
/FAULT/SD
Vss
SSDL
COM
LON
LOP
Vcc
DSL
U3
FAULT/SD
/SYS_FLT
S4
S3
EGP10J
D19
DSH
Vb
N.C.
HOP
HON
Vs
SSDH
N.C.
N.C.
N.C.
N.C.
N.C.
EGP10J
D18
R49
4k7
DSH
Vb
N.C.
HOP
HON
Vs
SSDH
N.C.
N.C.
N.C.
N.C.
N.C.
R47
4k7
3V3 3V3
GND
R42
4k7
SDDH1
HOP1
HON1
DSH1
SDDH2
HOP2
HON2
DSH2
1uF 25V
C35
Plug AC Male
Not on P CB
PACin
2
3
1
1uF 25V
C41
L2
L1
R41
4k7
GND
F2
SDDL1
LON1
LOP1
DSL1
SDDL2
LON2
LOP2
DSL2
SDDH1
HON1
HOP1
DSH1
SDDH2
HON2
HOP2
DSH2
1kR65
3.3nF 25V
C37
3.3nF 25V
C33
Not on P CB
SW-DPST
S1
R62 12e
R61 47e
R60 1k
R59 12e
R58 47e
R57 1k
R54 12e
R53 47e
R51 1k
R48 12e
R45 47e
Filter
A2
R70
3k3
K2
R71
10k
J5
ACInN
C42
470pF
STGP14NC60KD
Q9
STGP14NC60KD
Q7
GND
Q11
BC817
J6
ACInL
PGND
3.3nF 25V
C38
C34
3.3nF 25V
Phoenix Contact DP DT MR...21- 21
R69
100e
PE
Not on PCB
GND
10k
R63
EGP10J
L1
D16
R55
10k
EGP10J
D13
A Ci1 m
S5
A Ci2 m
1N4148
D20
10k
R64
Q8
R72
12e
R40
1N4148
D15
100e 4W
12V
100nF
C39
AGND
J3
ACOutN
100nF
C40
R52
10k
Q6
BC817
R50
J4
ACOutL
5VA
A1
C36
4.7uF 305V
L2
250uH ETD54
3k3
U4
HXS 20-NP/SP2
GND
K1
Phoenix Contact DP DT MR...21- 21
C132
4n7 AGND
AGND
C43
10uF 25V
Im
Q10
STGP14NC60KD
STGP14NC60KD
R68
33e 12V
1206
EGP10J
L2
D17
R56
10k
EGP10J
D14
UDC
ref
12
gnd
1
3
5
7
1
3
5
7
out
11
2
4
6
8
2
4
6
8
Vc
9
DS01279A-page 78
10
FIGURE D-5:
A Co1m
S6
AN1279
A Co2m
No t on PCB
R165
82k 1%
1206
R172
82k 1%
1206
R164
82k 1%
1206
R171
82k 1%
1206
2k2 1%
AGND
2k2 1%
R186
R182
Tm+
82k 1%
1206
82k 1%
1206
5VA
R152
R151
C123
4.7nF
ACo2m
ACo1m
ACi2m
82k 1%
1206
82k 1%
1206
82k 1%
1206
R154
82k 1%
1206
82k 1%
1206
R153
82k 1%
1206
82k 1%
1206
82k 1%
1206
3k3 1%
R197
2k2 1%
R192
C130
100nF
AGND
AGND
AGND
2k2 1%
R178
2k2 1%
R158
2V5A
U11A
100nF
AGND MCP6022
1
C121
R174
R173
5VA
82k 1%
1206
82k 1%
1206
2V5A
R167
R166
2V5A
R145
R144
C118
4.7nF
C111
4.7nF
AGND
U11B
MCP6022
Tr
R198
3k3 1%
R176
2
A
C129
100nF
AGND
AGND
3V3
3V3
D38
BAR43S
ACo
100k 1%
R179
C122
3k3 1%
1
2
3
5VA
D42 Bat Temp AGND

BAR43S
T
P7
R161
C115
4.7nF
3V3
Udcm+
Udcm-
C125
4.7nF
C128 R195
100nF
100k
AGND
AGND
R194
1k
3k3 1%
R185
IPm
D39
BAR43S
Ib
33k 1%
1206
R170
33k 1%
1206
R163
AGND
D41
BAR43S
Tb
C127
220pF
3V3
DNP
AGND
3V3
Ubm+
Ubm-
56k 1%
1206
56k 1%
1206
56k 1%
1206
D36
BAR43S
I
R150
R149
56k 1%
1206
56k 1%
1206
56k 1%
1206
R148
R141
R140
R139
AGND AGND
1k69 1%
R183
AGND AGND AGND
1k69 1%
R159
AGND
C120
4.7nF
Im
D35
BAR43S
ACi
U12A
100nF
AGND MCP6022
1
5VA
C119
4.7nF
3V3
AGND
C124
4.7nF
100k 1%
AGND
R188
AGND AGND
3k3 1%
C112
4.7nF
AGND AGND
1k69 1%
R169
33k 1%
1206
R184
3k3 1%
R156
AGND AGND
1k69 1%
R147
33k 1%
1206
R181
1k69 1%
R196
Ibatm+
Ibatm-
U10B
MCP6022
2k2 1%
R162
C114
4.7nF
3k3 1%
R193
C108
2k2 1%
R138
U10A
100nF
AGND MCP6022
1
5VA
8
4
8
4
ACi1m
R143
R142
8
4
8
4
10k
R190
AGND
C107
2k 1%
R137
C105
4.7nF
AGND
U12B
MCP6022
2k2 1%
R180
U9B
MCP6022
2k2 1%
R160
C113
4.7nF
U9A
100nF
AGND MCP6022
1
AGND
2k2 1%
R191
C116
4.7nF
AGND
2k2 1%
R177
C109
4.7nF
AGND
2k 1%
R157
5VA
8
4
8
4

8
R155
3k3 1%
R175
3k3 1%
R189
3k3 1%
4.7nF
C126
3V3
AGND AGND AGND
1k69 1%
R187
3V3
AGND
4.7nF
C117
AGND AGND
1k69 1%
R168
D40
BAR43S
IP
D37
BAR43S
Ub
D12
BAR43S
Udcm
AGND
C110
4.7nF
AGND AGND
1k69 1%
R146
3V3
FIGURE D-6:
C106
4.7nF
AN1279
DS01279A-page 79
Ubat
DS01279A-page 80
GND
R87
4k7
1206
R84
1206
150k
R80
1206
150k
R79
1206
150k
GND
68k
R78
0e
2
1
PAGND1
BR2
TEST
P10
BC856
Q13
GND
S3
SW-PB
R75
47k
R74
10k
GND
EGND
100pF 2kV
C80
GND
PGND
EGND
100pF 2kV
C81
3
2
4
8
10
7
5
6
9
PAGND1
EGND
EGND
UDC
LM5575
VIN
/SD
SYNC
RAMP
SS
RT
COMP
FB
AGND
IC1
C78
100pF 2kV
UBAT
1nF 25V
C56
100k
R77
0.33uF 100V
C45
2.2nF 25V
C57
R88
24k
1uF 25V R85

12K
C54
PAGND1
680pF 25V
C55
GND
1uF 25V
C48
C44
0.33uF 100V
C79
100pF 2kV
PGND
OUT
VCC
BST
SW
PRE
IS
GND
GND
12
11
1
16
14
15
13
C46
470nF 25V
GND
VOUT
GND
GND
TC1262-3.3
VIN
VR2
VOUT
GND
LM2904S-5.0
VIN
Needs heatsink on P CB
VR1
220nF 25V
C47
D22
ES3B
GND
GND
2.2uF 10V
C60
GND
C73
C75
2.2uF 10V 68uF 25V
LowESR
R81
10e
1206
C49
330pF
47uH 2.6A
L3
R82
10k
R221
1k
R220
2k2
R18
4k7
PAGND1
D47
D46
D45
R86
3k3
D21
BAV99
GND
GND
C50
power
1
3
5
7
P1
L8
L5
0805
BLM21PG221
3V3
0805
BLM21PG221
5V
GND
C51
C52
68uF 25V
LowESR
12V
12V
5VA
3V3A
AGND
C62
C61
2.2uF 10V 68uF 25V
LowESR
AGND
3V3A
D44
BZX85C16
GND
C68
C72
2.2uF 10V 68uF 25V
LowESR
AGND
5VA
0805
BLM21PG221
L6
68uF 25V
LowESR
2
4
6
8
68uF 25V
LowESR
C64
68uF 25V
LowESR
GND
C66
1uF 25V
R83
1k2
C53
1uF 25V
12V
5V
3V3
GND
FIGURE D-7:
R76
1206
150k
W1
R73
2-position header
1206 external ON/OFF switch F1
SMD075F/60
150k
(on enclosure)
Udc
AN1279
4k7
S2
C16
68uF 25V
LowESR
12e 1206
R19
D8
PS
TP7
R37
2k2
10k
GND
C30
68pF DNP
GND
IPm
ref1
U1A
5
ref2
U1B
Current sense to dsPIC

R39
10k DNP
7
3V3
LM393
GND 1
100nF C27 5V
DNP
R20
TP5
GND
C29
DNP
R36
1k
BAS21
D11
PGND
BAS21
D43
Q1C
FDP2532
GND
R38 R38a DNP
Q1B
FDP2532
1uF 100V
C13 C14
e5
e5
1uF 100V
Q1A
FDP2532
D4
current sense
1k
R10
12V
C12
1200uF
100V
PGND
1000uF 100V HT 105C
C11
1200uF
100V
PGND
BAS21
Ubm-
C20
PGND
D23
BAR43S100V
Q18
BC817
DNP
BAT-
J2
Cycle-by-cycle Current-Limit to dsPIC
GND
Fext
Ubm+
Ubat
2x20A
BAT+ Slow Blow (on enclosure)
J1
EPP
3.3nF 25V
10k
R23
D7
BAS21
U2
MCP14E4
TP6
C28
Vvercurrent shutdown to driver
100pF DNP
C15
1uF 25V
12V
GND PGND
BR1
0e
R6
S1
4
3
2
1
I N_B
GND
I N_A
ENB_A
OUT_ B
VDD
OUT_ A
ENB_ B
5
6
7
8
DNP
4.7e R19A
4k7
4.7e R19B
R3
4.7e R19C
1k / 33e(CT)
1206 DNP
R5
1206
0.01uF
100V
D32
BAV99
10k
R24
D10
BAS21
0.01uF
100V
C24
T3 DNP
CT 1:1000
(optional)
12e 1206
R22
10R 3W
R17
10R 3W
R16
C23
1
2
P_CT
D1
D3
D24
100V
BAR43S
D9
D48
BAV99
C21
3.3nF 25V
C6
2.4k 3W
R7
PGND
10k
PGND
Q2B
FDP2532
D5
C8
2.4k 3W
R9
150pF 1kV
C2D05120
D28
150pF 1kV
C4
2.4k 3W
R4
Q2A
FDP2532
R21
BAS21
D2
C2D05120
current sense
1k
R11
12V
150pF 1kV
C2D05120
PGND
C1
2.4k 3W
R1
150pF 1kV
ETD54
C2D05120
T1
Q19
BC817
DNP
4.7e R22A
DNP
33e(CT)
DNP
4.7e R22B

4.7e R22C
Q3C
FDP2532
P9A
C5
C7
Udc
TP2
Udcm+
Tr
Tr
DNP
DNP
10k
R28
D6
GND
Tm+
C26
DNP
ref2
C17
DNP
ref1
Tm-
KTY81/122
DNP
RT1 DNP
Q5
BC807
3k3
R14
12V
DNP
DNP
GND
R30
R29
10k DNP
R25
GND
R13
R12
10k DNP
R8
C3
e15
.1uF 630V
Udcm470uF 400V HT 105C
DCPGND
C2
DC+
BZX84C3V6
P9B
e15
.1uF 630V
200H
L1
FIGURE D-8:
R2
AN1279
DS01279A-page 81
DS01279A-page 82
GNDUSB
GNDUSB
12pF
C135
12pF
C133
UVpp
1M
R200
20MHz
Y3
10k
R199
5VUSB
GNDUSB
GNDUSB
GNDUSB
1nF
C138
14
13
12
11
10
RB3/AN9/VPO
RB2/AN8/INT2/VMO
RA3/AN3/VREF+
RA4/T0CKI/RCV
RC4/D-/VM
PIC18F2450
RC5/D+/VP
VUSB
RC6/TX/CK
RC1/T1OSI/UOE
RC2/CCP1
RC7/RX/CK
VSS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
VDD
OSC1/CLKI
RB0/AN12/INT0
RB4/AN11/KBI0
RA2/AN2/VREF-
Vss
RB5/KBI1/PGM
RA1/AN1
RB1/AN10/INT1
RB6/KBI2/PGC
RA5/AN4/HLVDIN
RB7/KBI3/PGD
UICSP D
MCLR/VPP/RE3
ICSP
5VUSB
RA0/AN0
U14
UICSP C
P8
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GNDUSB
5VUSB
UICSP C
UICSP D
Vcc2
In A
Out B
GND2
Vcc1
Out A
In B
GND 1
ISO7221
J7
GND
D+
D-
VBUS
GNDUSB
C136
100nF
USB B 1-1470156-
1uF 25V
GNDUSB
GNDUSB
5VUSB
C137
L9
BLM21PG221
5VUSB
U13
0805
GND
3V3
C134
TX
RX
C131
100nF
GND
100nF
EGND
FIGURE D-9:
UVpp
AN1279
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
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2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
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and manufacture of development systems is ISO 9001:2000 certified.
DS01279A-page 83
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DS01279A-page 84

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AN1279

Offline UPS Reference Design Using the dsPIC DSC

Application Markets for UPS Systems

Types of UPS Systems

OFFLINE UPS DIAGRAM

If a longer backup period is considered, a larger battery

2009 Microchip Technology Inc.

A Line-Interactive UPS (see Figure 2), always relays

ONLINE UPS DIAGRAM

220V UPS Version Specifications

220 VAC 10%, 50 Hz 3 Hz

3 x 12 VDC (lead acid battery)

220 VAC, 50 Hz 1 Hz,

1000 W/1000 VA,

110V UPS Specifications

110 VAC 10%, 60 Hz 3 Hz

3 x 12 VDC (lead acid battery)

110 VAC, 60 Hz 1 Hz,

1000 W/1000 VA,

2009 Microchip Technology Inc.

After a power failure, the system is switched to UPS

The Offline UPS system shown in Figure 4 operates in

OFFLINE UPS REFERENCE DESIGN

2009 Microchip Technology Inc.

temperature sensor measures heat sink temperature,

PUSH-PULL CONVERTER RESOURCE DIAGRAM

Table 2 lists the resources used by the dsPIC DSC

RESOURCES REQUIRED FOR A DIGITAL PUSH-PULL CONVERTER

Expected Signal Level

T (optional, not implemented

Enable driver, Digital

2009 Microchip Technology Inc.

the DC link capacitors when power grid voltage is fed

DIGITAL FULL-BRIDGE INVERTER RESOURCE DIAGRAM

Table 3 shows the resources used by a dsPIC DSC

RESOURCES REQUIRED FOR A DIGITAL FULL-BRIDGE INVERTER

Expected Signal Level

Digital input (external interrupt)

S3, S4 (gate drive)

S5, S6 (gate drive)

2009 Microchip Technology Inc.

DIGITAL FLYBACK SWITCH MODE CHARGER RESOURCE DIAGRAM

Table 4 shows the resources used by the dsPIC DSC

RESOURCES REQUIRED FOR A DIGITAL FLYBACK SWITCH MODE CHARGER

Expected Signal Level

2009 Microchip Technology Inc.

Selection of a topology depends on careful analysis of

Most UPS designs contain a transformer-type DC/DC

Operation of each of the above topologies is described

Transformer-type DC/DC converters are divided into

The diode D1 on the secondary ensures that only

The Flyback topology operation differs slightly from

where d is the duty cycle of the transistor Q

2009 Microchip Technology Inc.

PWM drive signal), Q2 conducts, current flows through

A push-pull converter is shown in Figure 9. When Q1

There are two important considerations with the

These criteria must be satisfied by the control and drive

2009 Microchip Technology Inc.

2009 Microchip Technology Inc.