Sistemas Embarcados e Tempo Real

ME445M: Embedded and Real Time Systems
Lecture Set #01
EE445M: EMBEDDED AND REAL TIME SYSTEMS Lecture Set

#01
February 15, 2017
Course offered by the Department of
Electrical Engineering at University of Texas
at Austin
Disclaimer: The contents of this document are scribe notes for The University of
Texas at Austin EE445M Spring 2017, Embedded and real Time Systems.
RTOS
RealTimeOperatingSystem
Note Taker: Hilgad Montelo (hilgad.montelo@utexas.edu)
Copyright Hilgad Montelo. All rights reserved.

Lecture Set #01
RTOS Review
RTOS
Real Time Operating System is a software that manages computer system resources
like memory, I/O, data and processors, satisfying all time constraints.
HAL
Hardware Abstraction Layer. A software that simplifies porting application code from
one microcontroller to another.
Response Time or latency

It is the delay from request to the beginning of the service of that request.
Bandwidth
It is the number of information that can be transferred or processed (bytes/sec).
Embedded System
It consist of a smart device with a processor that has a special and dedicated
purpose.
For Embedded Systems, Real Time means that the embedded system must
respond to critical events with a strictly defined time (deadline).
There are 5 (five) types of software functions that the processor can perform in an
embedded system:
1. Mathematical or data processing operations.

2. Handling and managing time.
3. Real Tim input/output for measurement and control
4. DSP (Ex.: Audio, video, radar etc)
5. Communication and Network.
Embedded Systems are classified as:
Transformative: Collect data from inputs, makes decisions and affects its
environment by driving actuators (Ex.: Robots).
Reactive: Collects data from inputs in continuous fashion and produces outputs
in continuos fashion (Ex.: DSP).

Lecture Set #01
Common Embedded System Constraints:
- Small Size,
- Low weight,
- Low power,
- Harsh Environments,
- Safety Critical Systems
- Sensitive Cost.
Computer
It combines a CPU, Random Access memory (RAM), Read Only Memory (ROM), and
I/O ports.
Software
It is an ordered sequence of very specific instructions that are stored in memory,
defining exactly what and when certain tasks are to be performed.
Harvard Architecture
It has a separated data and instruction buses.
Interrupt
It is a hardware-triggered software function, which is extremely important for real
time embedded systems.
Latency of an interrupt Service

It is the time between hardware triggered and software response.
ARM Cortex-M Memory Access (bit banding)

Bit banding allow to read/write memory access.
Ex.01: What address do you use to access bit 3 of the byte 0x2000.1010?
Address = 0x2200.0000 + 0x20 x n + 4 x b
b=3
n = 0x1010
So,
Address = 0x2200.0000 + 0x20 x 0x1010 + 4 x 3 = 2202.020C

Lecture Set #01
Ex.02: What address do you use to access bit 7 of the byte 0x4000.0030?
Address = 0x4200.0000 + 0x20 x n + 4 x b
b=7
n = 0x0030
So,
Address = 0x4200.0000 + 0x20 x 0x0030 + 4 x 7 = 4200.061C
ARM Cortex-M Registers

R0-R12 General Purpose Registers.
R13 Stack Pointer (SP)
Note: there are 2 (two) stack pointers:
- Man Stack Pointer (MSP): Used for the Operating System
- Process Stack pointer (PSP): Used for the User Software.
R14 Link Register (LR). It stores the return location for the functions.
R15 Program Counter (PC). It points to the next instruction to be fetched
in memory.
The ARM Architecture Procedure Call Standard (AAPCS) part of the ARM Application
Binary Interface (ABI):
- Uses R0, R1, R2, R3, and R12 to pass input parameters into a C function or an
assembly sub-routine.
- The place to return parameter is R0.
- Preserve registers R4-R11, which implies save R4-R11, use them, and restore R4-
r11 before returning.
- Keep the stack aligned to 64 bits, by pushing and popping an even number of
registers (multiple of 8 bytes).
Special Registers:
- PSR (Program Status Register),

- Control Register
- PRIMASK*,
- FAULTMASK*,
- BASEPRI* * Exception mask Registers
ARM Program Status Register (PSR)

It contains the flags to represent the program status.
N Z C V Q I I/I T RESERVED ICI/ ISR Number
C T IT
31 3 2 28 27 26 25 2 2 2 2 2 1 1 1 1 15 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
0 9 4 3 2 1 0 9 8 7 6 4 3 2 1 0
N, Z, C, V, and Q represents status of ALU (Arithmetical and Logical Unit) operations.

Lecture Set #01
N Set if the result of a logical or arithmetical operation was

negative
Z If the result was zero
C If a carry happened
V If an overflow happened
Q If a saturation has occurred
T Arm is executing thumb instructions
ICI/T Used by interruptions and IF-THEN instructions
bit 0 of PRIMASK It is the interrupt mask bit or I bit. If is 1, most interrupt and
exceptions are not allowed; if is 0, interruptions are allowed.
STACK
A Last In First Out (LIFO) temporary storage.
Proper use of Stack requires the following rules:
1. Functions should have an equal number of pushes and pops.

2. Stack access should not be performed outside the allocated area.
3. Stack read and write should not be performed within the free area.
4. Stack push decrements SP then store data
5. Stack pop should first reads data then increment SP.
A bus fault will be generated when the software tries to read/write from an address
that does not exists. If a valid address below or above the stack, then further stack
operation will corrupt the data.
When multiple registers are pushed and popped, the data exists in memory with the
lowest numbered register using the lowest memory address (stacks top). Ex.:
If R1, R4, R5, R6 contains the values 1, 4, 5, 6 respectively, then the value of the
lowest numbered register R1 is placed in the lowest stack address.
If four entries are popped like POP {R0, R2, R7, R9}, the value the lowest stack
address is loaded in the lowest numbered register.
ARM Operating Modes

Arm Cortex-M processor has 2 privileged modes: privileged and unprivileged.
Bit 0 on Register Control is the thread Privileged Mode (TPL).
If TPL is 1 processor is in privileged mode. If TPL is 0 runs in unprivileged mode.
Bit 1 on the Register Control is the Active Stack Pointer Selection (ASPSEL).

Lecture Set #01
If ASPSEL is 1 then processor uses PSP.
If ASPSEL is 0 then processor uses MSP.
ARM Defines
- Foreground (main program) as thread Mode.
- Background (ISR) as handler Mode.
Switching between thread and handler mode is automatic.
The processor begins in thread mode, i.e. ISR_NUMBER = 0.
Whenever it is serving an interrupt, it switches to handler mode; i.e. ISR_NUMBER =

Interrupt being processed.
All ISR runs using the MSP stack pointer.
Note: The context is saved whichever stack pointer is active, but during the
execution of ISR, the MSP is used.
RESET
After a reset.
1. Processor is thread mode

2. Run in privileged mode
3. Uses MSP stack pointer
4. Load the 32 bit value located in position 0 of ROM into the SP
5. Load the 32 bit value located in position 4 of ROM into the PC
6. Thumb bit (T bit in Control register) is always 1 in Cortex-M.
7. LR is set to 0xFFFFFFFF.
I/O
Pin Specific wire on the microcontroller unit (MCU) that can be used for
specific input/output operations.
Port A collection of pins grouped by common functionalities
Interfa Collection of I/O ports, external electronics, physical devices, and
ce softwares.
I/O Interfaces
I/O interfaces can be classified in 4 (four) categories:
1. Parallel/Digital: Binary data available simultaneously on a group of lines.

2. Serial: Binary data is available 1 bit of the time.
3. Analog: Data are encoded as electrical, voltage or power.
4. Time: data are encoded as a period, frequency, pulse width or phase shift.

Sistemas Embarcados e Tempo Real

Uploaded by

Copyright:

Available Formats

Sistemas Embarcados e Tempo Real

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Sistemas Embarcados e Tempo Real

Uploaded by

Copyright:

Available Formats

ME445M: Embedded and Real Time Systems

Lecture Set #01

EE445M: EMBEDDED AND REAL TIME SYSTEMS Lecture Set

Note Taker: Hilgad Montelo (hilgad.montelo@utexas.edu)

Copyright Hilgad Montelo. All rights reserved.

Response Time or latency

1. Mathematical or data processing operations.

Embedded Systems are classified as:

Copyright Hilgad Montelo. All rights reserved.

Common Embedded System Constraints:

Latency of an interrupt Service

ARM Cortex-M Memory Access (bit banding)

Address = 0x2200.0000 + 0x20 x n + 4 x b

Address = 0x2200.0000 + 0x20 x 0x1010 + 4 x 3 = 2202.020C

Copyright Hilgad Montelo. All rights reserved.

Address = 0x4200.0000 + 0x20 x n + 4 x b

Address = 0x4200.0000 + 0x20 x 0x0030 + 4 x 7 = 4200.061C

ARM Cortex-M Registers

- PSR (Program Status Register),

ARM Program Status Register (PSR)

N, Z, C, V, and Q represents status of ALU (Arithmetical and Logical Unit) operations.

Copyright Hilgad Montelo. All rights reserved.

N Set if the result of a logical or arithmetical operation was

Proper use of Stack requires the following rules:

1. Functions should have an equal number of pushes and pops.

ARM Operating Modes

Bit 0 on Register Control is the thread Privileged Mode (TPL).

If TPL is 1 processor is in privileged mode. If TPL is 0 runs in unprivileged mode.

Copyright Hilgad Montelo. All rights reserved.

If ASPSEL is 1 then processor uses PSP.

If ASPSEL is 0 then processor uses MSP.

Switching between thread and handler mode is automatic.

The processor begins in thread mode, i.e. ISR_NUMBER = 0.

Whenever it is serving an interrupt, it switches to handler mode; i.e. ISR_NUMBER =

All ISR runs using the MSP stack pointer.

1. Processor is thread mode

1. Parallel/Digital: Binary data available simultaneously on a group of lines.

Copyright Hilgad Montelo. All rights reserved.

You might also like