3-Wire RTD Measurement System Reference Design, - 200°C To 850°C

Ryan Andrews, Collin Wells
TI Designs Precision: Verified Design

3-Wire RTD Measurement System Reference Design,
-200C to 850C
TI Designs Precision Circuit Description

TI Designs Precision are analog solutions created This ratiometric temperature acquisition system
by TIs analog experts. Verified Designs offer the accurately measures temperature over a wide range
theory, component selection, simulation, complete of -200C to 850C. The design uses a resistance
PCB schematic & layout, bill of materials, and temperature detector (RTD) in a 3-wire configuration
measured performance of useful circuits. Circuit to minimize the errors introduced by the lead
modifications that help to meet alternate design goals resistances of a remotely located RTD. A 24-bit delta-
are also discussed. sigma () analog-to-digital converter (ADC) is used
in this design which features two integrated precision
current sources that excite the 3-wire RTD. The
differential voltage that develops across the RTD is
converted into a digital output code and translated
into a final temperature result.
Design Resources
Ask The Analog Experts
Design Archive All Design files WEBENCH Design Center
TINA-TI SPICE Simulator TI Designs Precision Library
ADS1247 Product Folder
TPS7A4901 Product Folder
ADS1247
IDAC
AIN0/IEXC1 Excitation
RI1 CI_CM1
Current
AIN1 Sources
RRTD CI_DIFF AIN2
RI2 AIN3/IEXC2
CI_CM2

MUX PGA
ADC
Reference
Buffer/MUX
REFP REFN
CR_CM1 CR_CM2
CR_DIFF
RR1 RR2
RREF
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and
other important disclaimers and information.
TINA-TI is a trademark of Texas Instruments
WEBENCH is a registered trademark of Texas Instruments
SLAU520A-December 2013-Revised November 2014 3-Wire RTD Measurement System Reference Design, -200C to 850C 1
Copyright 2013, Texas Instruments Incorporated
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1 Design Summary
The design requirements are as follows:
RTD Type: 3-Wire Pt100
Temperature Measurement Range: -200C to 850C
Temperature Measurement Accuracy: 0.05C at TA = 25C
System Supply Voltage (VDUT): 5 V
ADC Supply Voltage (AVDD): 3.3 V
The design goals and performance are summarized in Table 1. Figure 1 depicts the measurement
accuracy of the design.
Table 1. Comparison of Design Goals and Measured Performance

Goal Calculated Measured
Unadjusted Resistance Measurement 0.1 0.082 0.096
Accuracy
Calibrated Resistance Measurement 0.01925 0.0049 0.00415
Accuracy
Calibrated Temperature Measurement 0.05C 0.013C 0.0106C
Accuracy
0.05
0.0375
0.025
Temperature Error (C)
0.0125
Calibrated Results
-0.0125
-0.025
-0.0375
-0.05
0 50 100 150 200 250 300 350 400
RRTD ()
Figure 1. Measured Temperature Accuracy with Resistive Input Representing -200C to 850C
2 3-Wire RTD Measurement System Reference Design, -200C to 850C SLAU520A-December 2013-Revised November 2014
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2 Theory of Operation
2.1 Resistance Temperature Detector (RTD) Overview

An RTD is a sensing element made of a metal with predictable resistance characteristics over
temperature. The temperature of an RTD can therefore be calculated by measuring the resistance. RTD
sensors offer wide temperature ranges, good linearity, and excellent long-term stability and repeatability,
making them suitable for many precision measurement applications.
The relationship between resistance and temperature of an RTD is defined by the Callendar-Van Dusen
(CVD) equations which can be found in Appendix A.4.
Compared to a thermocouple, the main disadvantages of RTD sensors are their cost and required
excitation source. The small change in resistance of an RTD over temperature also places demands on
the accuracy of the acquisition circuit requiring a precision signal chain. Thermistors have larger changes
in resistance over temperature but are much less linear, reducing their effectiveness at measuring wider
temperature ranges.
2.2 RTD Resistance Measurement

Most RTD applications use a current source as excitation for the RTD element. By driving a known current
through the RTD, a voltage potential is developed that is proportional to the resistance of the RTD and the
excitation current. This voltage potential is amplified and then fed to the inputs of an ADC, which converts
the voltage into a digital output code that can be used to calculate the RTD resistance.
I1
VIN+

GAIN
RRTD VDIFF ADC
VIN-
Figure 2. Simplified RTD Application
VDIFF VIN VIN I1 RRTD (1)
2.2.1 Ratiometric Measurements
An ADC requires a reference voltage to convert the input voltage into a digital output. In most applications,
this reference is fixed and either internally generated or externally applied to the ADC. This 3-wire RTD
system uses what is known as a ratiometric configuration to create the reference voltage, increasing
system accuracy.
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In the ratiometric configuration shown in Figure 3, the excitation current that flows through the RTD returns
to ground through a low-side reference resistor, RREF. The voltage potential developed across RREF, VREF,
is fed into the positive and negative reference pins (REFP and REFN) of the ADC. VREF serves three
purposes in this design: it sets the input common-mode voltage (VCM), the differential ADC input range
(typically VREF), and it is also used to convert the input voltage into digital output codes. See Equations
( 2 ) ( 6 ).
Setting VREF to mid-supply results in optimal input circuit performance for the ADC. R REF should be
selected with low tolerance and low drift since errors in the reference voltage will directly translate into
errors in the conversion result.
I1
VIN+

RRTD VDIFF GAIN
ADC
VIN- REFP REFN
RREF
Figure 3. Ratiometric RTD Measurement
VREF VCM I1 RREF (2)
VREF VREF
VDIFF (3)
Gain Gain
The voltage drop across the RTD and RREF resistors is produced by the same excitation source in a
ratiometric configuration as shown in Equations ( 4 ) - ( 5 ). Therefore, any changes in the excitation
source are reflected in both the RTD differential voltage and the reference voltage. Since the ADC output
code is a relationship between the input voltage and the reference voltage, the final conversion result is
simply a ratio of the RTD and RREF resistances as shown in Equation ( 6 ). Consequently, inaccuracies due
to magnitude, temperature drift, and noise of the current source cancel without affecting the final
conversion result. The ratiometric configuration also helps reduce the effects of external noise that
appears common to both the inputs and the reference because it should cancel as well.
VDIFF VRTD I1 RRTD (4)
VREF I1 RREF (5)
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V Gain RRTD Gain

CodeIDEAL CodesTOTAL DIFF CodesTOTAL (6)
2 VREF 2 RREF
2.2.2 Current Sources
Two precision current sources are typically used in 3-wire RTD applications to provide an easy way to
cancel the RTD lead resistances (RLEAD) as shown in Figure 4. This technique works best when the two
current sources are well-matched, both in initial accuracy and temperature drift. For additional information
on other RTD configurations, refer to Reference 2.
Equations ( 7 ) ( 10 ) derive the final differential input voltage and prove that RLEAD is excluded from the
final result.
I1
RLEAD VIN+
I1

RRTD VDIFF GAIN
ADC
RLEAD
REFP REFN
I2 VIN-
I1 + I2
RLEAD I2
RREF
Figure 4. 3-Wire RTD Lead Resistances Canceled by Excitation Currents
I1 I2 I (7)
VIN = I (RLEAD RRTD ) + 2 I (RLEAD + RREF )

(8)
VIN = 3 I RLEAD + 2 I RREF + I RRTD
VIN- = I RLEAD 2 I (RLEAD + RREF )

(9)
VIN- = 3 I RLEAD + 2 I RREF
VDIFF = VIN - VIN- = I RRTD ( 10 )
With two current sources flowing through RREF in this 3-wire RTD system, the VREF voltage doubles as
shown in Equation ( 11 ). Therefore, the final conversion result transfer function also changes as shown in
Equation ( 12 ).
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VREF 2 I RREF ( 11 )
R Gain
CodeOUTPUT CodesTOTAL RTD ( 12 )
4 RREF
The magnitude of the current sources directly affects the magnitude of the RTD voltage. While maximizing
the magnitude of the excitation current would seem desirable, higher excitation currents create a concern
for violating the compliance voltage of the current source as well as errors due to self-heating.
The current sources will have a compliance voltage limitation based on the topology and supply voltage.
The voltage on the positive input (VIN+) must be limited to a level below the compliance voltage for the
current sources as defined by Equation ( 13 ).
VIN VCM (I1 RRTD ) VCompliance ( 13 )
The power-dissipation in the RTD leads to self-heating errors that cannot be easily corrected and should
be kept lower than 25% of the total error budget as a general practice. Keeping the excitation current small
will also minimize the heat produced in other signal path components, reducing drift and other additional
measurement errors. Figure 5 displays the self-heating errors in degrees Celsius versus applied excitation
current for both small and large RTD elements. The typical range of RTD self-heating coefficients is 2.5
mW/C for small, thin-film elements (shown in blue) and 65 mW/C for larger, wire-wound elements
(shown in red).
Self-Heating Error of an RTD vs. Exc itation Current
10
0.1
Temperature (C)
0.01
Error65mW( I)
3
110
Error2.5mW( I)
4
110
5
110
6
110
7
110
5 4 3
110 110 110 0.01
I
Excitation Current (A)
Figure 5. RTD Self-Heating vs. Excitation Current for Different RTD Types
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The effects of self-heating on measurement accuracy are also based on the placement of the RTD in the
application. The effects of self-heating are reduced if the RTD is placed in a moving fluid medium because
the moving fluid will keep the RTD close to the temperature of the fluid. However, in open-air temperature
measurements, or other applications where the RTD is surrounded by an insulator, the RTD will self-heat
and cause errors.
2.2.3 Amplification Stage
The full-scale input range of an ADC is bounded by the reference voltage, VREF. By choosing a smaller
value for the excitation current to reduce self-heating, the RTD produces a smaller change in voltage over
the span of the temperature measurement that will not use the full ADC input range. Therefore, a gain
stage is required to amplify the RTD voltage to a level that utilizes more of the range of the full-scale ADC
input, VIN_ADC, and maximizes the measurement resolution.
VIN _ ADC I1 RRTD Gain ( 14 )
The gain must be selected such that neither the full-scale input voltage nor the common-mode input
voltage is violated. Both limitations are typically found in the device specifications section of the data
converter datasheet.
2.2.4 Input and Reference Low-Pass Filters
Using differential and common-mode low-pass filters at the input and reference paths improves the
cancellation of excitation and environmental noise. However, it is important to note that the corner
frequency of the two differential filters must be well-matched as stated in Reference 1. The input and
reference filters are shown in Figure 6.
I1
RI1 CI_CM1

RRTD CI_DIFF GAIN
RI2 ADC
CI_CM2 REFP REFN

I2
CR_CM1 CR_CM2
CR_DIFF
RR1 RR2
RREF
Figure 6. Input and Reference Low-Pass Filtering
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3 Component Selection
3.1 ADC ADS1247

As shown in Figure 7, the ADC chosen for this application is the ADS1247. This device not only has the
resolution and accuracy needed to achieve the aforementioned design goals, but also features all the
internal sub-circuits required to realize the design.
The ADS1247 is a 24-bit, delta-sigma () ADC that offers a complete front-end solution for RTD
applications. It comes from a product family of highly integrated precision data converters, featuring a low-
noise programmable gain amplifier (PGA), a precision modulator, a digital filter, an internal oscillator,
and two digitally controlled precision current sources (IDACs). It is a popular industry choice for precision
temperature measurement applications. Other popular choices listed in Table 10 and Table 11 showcase
similar functionality and performance.
ADS1247
IDAC
AIN0/IEXC1 Excitation
RI1 CI_CM1
Current
AIN1 Sources
RRTD CI_DIFF AIN2
RI2 AIN3/IEXC2
CI_CM2

MUX PGA
ADC
Reference
Buffer/MUX
REFP REFN
CR_CM1 CR_CM2
CR_DIFF
RR1 RR2
RREF
Figure 7. Ratiometric RTD System Featuring the ADS1247
3.1.1 Current Source (IDAC) Configuration
The ADS1247 features two IDAC current sources capable of outputting currents from 50 A to 1.5 mA.
Based on Figure 5, the excitation currents will be set to 1 mA to maximize the RTD sensor output while
keeping the errors due to self-heating less than the desired goal of 0.05C.
The internal reference voltage must be on while using the IDACs, even if an external ratiometric reference
is used for ADC conversions. Table 2 displays the required register settings to set the IDACs to 1 mA and
configure them for the proper output channels.
Table 2. Register Settings for Current Sources

Register (Address) Register Bits Bits Name Bit Values Comment
MUX1 (02h) MUX1[6:5] VREFCON[1:0] 01 Internal Reference ON
IDAC0 (0Ah) IDAC0[2:0] IMAG[2:0] 110 IDACs = 1 mA
IDAC1 (0Bh) IDAC1[7:4] I1DIR[3:0] 0000 IDAC1 AIN0
IDAC1 (0Bh) IDAC1[3:0] I2DIR[3:0] 0011 IDAC2 AIN3
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3.1.2 IDAC Multiplex Chopping
As the equations in Section 2.2.2 show, the two current sources must be exactly matched to successfully
cancel the lead resistances of the RTD wires. While initial matching of the current sources is important,
any remaining mismatch in the two sources can be minimized by using a multiplexer to swap, or chop,
the two current sources between the two inputs. Taking measurements in both configurations and
averaging the readings will greatly reduce the effects of mismatched current sources. This design uses the
digitally-controlled multiplexer in the ADS1247 to realize this technique. The multiplexer also affords the
user some additional flexibility when routing the input voltage signals and excitation current sources on
their printed circuit board (PCB) layout.
3.1.3 Programmable Gain Amplifier (PGA) Configuration
In this application, the ADC uses a 3.3 V supply for both the analog (AVDD) and digital (DVDD) power
supplies. The excitation currents and RREF have been selected to produce a 1.64 V reference, allowing for
a differential input signal range of 1.64 V into the modulator. The maximum allowable PGA gain
setting is based on the reference voltage, the RTD resistance change, and the excitation current as shown
in Equations ( 15 ) ( 17 ).
RRTD@ 850C 390.48 ( 15 )
VIN _ MAX RRTD@ 850C IIDAC 390.48 1 mA

( 16 )
VIN _ MAX 390.48 mV
VREF 1.64 V V
GainMAX 4.2 ( 17 )
VIN _ MAX 0.39048 V V
The PGA gain is set to the closest ADS1247 PGA gain that is below the maximum value calculated in
Equation ( 17 ). The PGA will be set to 4 V/V, as shown in Table 3.
Table 3. Register Settings for PGA

Register (Address) Register Bits Bits Name Bit Values Comment
SYS0 (03h) SYS0[6:4] PGA[2:0] 010 PGA = 4 V/V
3.2 Passive Components
3.2.1 RREF
The value of RREF is selected based on the IDAC setting and the desired VREF voltage of 1.64 V, as shown
in Equations ( 18 ) ( 19 ).
VREF
RREF ( 18 )
2 IIDAC
1.64 V
RREF 820 ( 19 )
2 1 mA
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An 820 RREF resistor was chosen based on the results of Equation ( 19 ). Since the voltage across the
RREF sets the reference voltage for the ADC, the tolerance and temperature drift of R REF directly affect the
measurement gain error as shown in Section 4.2.2.1 and Appendix A.5.1. To meet the un-calibrated
accuracy requirement of 0.1 (or 0.027% of the full-scale resistance range), a resistor with 0.02%
maximum tolerance was selected.
Note that, as with any amplifier, it is necessary to ensure that the input voltage stays within the specified
common-mode input range listed in the device datasheet specification table. The common-mode input
voltage (VCM) to the PGA must stay within the range shown in Equation ( 20 ) based on the maximum RTD
voltage.
VIN _ MAX Gain VIN _ MAX Gain

AVSS 0.1 V VCM AVDD 0.1 V
2 2
( 20 )
881 mV VCM 2.42 V
For the IDACs to remain operational, the AIN0 and AIN3 inputs of the ADS1247 must satisfy the IDAC
compliance voltage found in the ADS1247 datasheet (see Equation ( 21 )). The largest voltage will be
seen at AIN0 as it equals the sum of the common-mode voltage and the maximum RTD voltage shown in
Equation ( 22 ).
AIN0 AVDD 0.7 V 2.6 V ( 21 )
AIN0 VCM VIN _ MAX 1.64 V 390.48 mV 2.03 V ( 22 )
In this ratiometric configuration, VREF sets the input common-mode voltage at 1.64 V, satisfying the
requirements for both the input common-mode voltage and the IDAC compliance voltage of the ADS1247.
3.2.2 Input and Reference Low-Pass Filters
The differential filters chosen for this application were designed to have a -3 dB corner frequency at least
10 times larger than the bandwidth of the ADC. The selected ADS1247 sampling rate of 20 SPS results in
a -3dB bandwidth of 14.8 Hz. The -3dB filter corner frequency was set to be roughly 250 Hz at mid-scale
measurement resistance. For proper operation, the differential cutoff frequencies of the reference and
input low-pass filters must be well matched. This can be difficult because as the resistance of the RTD
changes over the span of the measurement, the filter cutoff frequency changes as well. To mitigate this
effect, the two resistors used in the input filter (RI1 and RI2) were chosen to be two orders of magnitude
larger than the RTD. Input bias currents of the ADC will cause a voltage drop across the filter resistors that
will show up as a differential offset error if the bias currents and/or filter resistors are not equal. Limiting the
resistors to at most 20 k will reduce dc offset errors due to input bias current.
RI1 RI2 9.09 k ( 23 )
The input filter differential capacitor (CI_DIFF) can be calculated as shown in Equation ( 24 ).
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1
f 3dB _ DIFF
2 CI _ DIFF (RI1 RRTD RI2 )
( 24 )
CI _ DIFF 33 nF
To ensure that mismatch of the common-mode filtering capacitors is not translated to a differential voltage,
the common-mode capacitors (CI_CM1 and CI_CM2) were chosen to be ten times smaller than the differential
capacitor, making them 3.3 nF each. This results in a common-mode cutoff frequency that is roughly
twenty times larger than the differential filter, making the matching of the common-mode cutoff frequencies
less critical.
CI _ CM1 CI _ CM2 3.3 nF ( 25 )
1
f 3dB _ CM
2 CI _ CM1 (RI1 RRTD RREF )
( 26 )
f 3dB _ CM = 4.76 kHz
1
f 3dB _ CM
2 CIN _ CM2 (RI2 RREF )
( 27 )
f 3dB _ CM = 4.87 kHz
The differential reference filter is designed to have a -3 dB corner frequency of 250 Hz to match the
differential input filter. The two reference filter resistors were selected to be 20 k, several times larger
than the value of RREF. The reference filter resistors should not be sized larger than 20 k or dc bias errors
will become significant.
RR1 RR2 20 k ( 28 )
The differential capacitor for the reference filter can be calculated as shown in Equation ( 29 ).
1
f 3dB _ DIFF
2 CR _ DIFF (RR1 RREF RR2 )
( 29 )
CR _ DIFF 15 nF
To ensure that mismatch of the common-mode filtering capacitors is not translated to a differential voltage,
the reference common-mode capacitors (CR_CM1 and CR_CM2) were chosen to be ten times smaller than the
reference differential capacitor, making them 1.5 nF each. Again, the resulting cutoff frequency for the
common-mode filters is roughly twenty times larger than the differential filter, making the matching of the
cutoff frequencies less critical.
CR _ CM1 CR _ CM2 1.5 nF ( 30 )
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1
f 3dB _ CM
2 CR _ CM1 (RR1 RREF )
( 31 )
f 3dB 5.10 kHz
1
f 3dB _ CM
2 CR _ CM2 RR2
( 32 )
f 3dB 5.31 kHz
3.3 Low-Dropout (LDO) Linear Regulator

The RTD acquisition board in this design interfaces with an external PC GUI through a USB interface
board to post-process the ADC digital output and display the temperature result. Power for the acquisition
board comes from the USB power supply rail (VDUT). This supply may be passed through a high-PSRR
low-dropout regulator (LDO) to create the AVDD and DVDD supplies and to avoid inaccuracies due to
power supply noise.
The TPS7A4901 comes from a series of high-voltage, ultra-low noise LDOs that are ideal for precision
applications. A resistor divider at the LDO output sets the output voltage (V LDO_OUT) proportional to the
LDOs internal reference voltage (VLDO_REF). For this device, VLDO_REF = 1.188 V. In order to set VLDO_OUT to
the desired output voltage of 3.3 V, the resistor divider components are selected using Equation ( 33 ).
R1
VLDO _ OUT VLDO _ REF 1
R2
( 33 )
R1 140 k
R2 78.7 k
VDUT VOUT
IN OUT
10F 0.1F 0.01F 140k
EN TPS7A4901 FB
0.1F 10F
78.7k
NR/SS GND
0.01F
Figure 8. LDO Configuration for +3.3 V Output
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4 Simulation and Error Calculation
4.1 Simulation
Figure 9 shows the TINA-TI circuit used to simulate the behavior of the RTD, input filtering, and PGA in
this system. The RTD has been modeled with a Pt100 macromodel that converts an input voltage
representative of the RTD temperature into the correct output resistance using the CVD equations. The
simplified ADS1247 PGA does not accurately represent the internal circuitry to the ADC; however, it does
represent the ideal behavior of the internal PGA.
IDAC1 VREF_INT ADS1247 PGA

VREF
IDAC1 1m
IOP4
R8 4k
CI_CM1 3.3n -
Pt100 RTD RI1 9.09k AINP
U1 RTD3 +
R7 1k
VT+ RTD+ +
+ +
TEMP 100 V 2_V_RTD
CIN_DIFF 33n VIN_PGA VIN_ADC+
VT- RTD-
-
Mon+ Mon- AINN -
RI2 9.09k IOP1
+
Temp (C)
+ R9 1k
(Volts = degrees C) V -
CI_CM2 3.3n IOP3
1_R_RTD R10 4k
RTD Resistance
IDAC2 VREF_INT +
(Volts = Ohms) 3_VIN_ADC
-
IDAC2 1m
4_VREF
VREF
- IOP2
RR1 20k CR_CM1 1.5n
VREFP VIN_ADC-
+
+
RREF 820 CR_DIFF 15n VREF_ADC
VREFN -
RR2 20k +
CR_CM2 1.5n
- IOP5
TM
Figure 9. TINA-TI Simulation Circuit for the RTD and ADS1247 Inputs
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4.1.1 RTD Transfer Function
Figure 10 displays the RTD resistance, RTD voltage, ADC input voltage, and the V REF voltage as the RTD
temperature is swept from -200C to 850C. The results are displayed on the image for the minimum, mid-
scale, and maximum temperatures. The RTD voltage spans from 18.51 mV to 390.48 mV and with the
PGA set to 4 V/V, the differential ADC input is from 74.03 mV to 1.56 V. The VREF voltage is also displayed
and is the expected value of 1.64 V.
T 400
RTD ( )
0 R_RTD A:(-200; 18.51)

400m V_RTD A:(-200; 18.51m)
VIN_ADC A:(-200; 74.03m)
V_RTD (V) VREF A:(-200; 1.64)
R_RTD A:(0; 100)

0 V_RTD A:(0; 100m)
2 VIN_ADC A:(0; 400m)
VREF A:(0; 1.64)
VIN_ADC (V)
R_RTD A:(850; 390.48)
0 V_RTD A:(850; 390.48m)
VIN_ADC A:(850; 1.56)
3
VREF A:(850; 1.64)
VREF (V)
0
-200 -50 100 250 400 550 700 850
o
Temperature ( C)
Figure 10. RTD, ADC, and VREF from -200C to 850C
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4.1.2 Low-pass Filter Response
The frequency response of the input and reference filters was tested using an ac current generator in
place of the IDAC1 source and is shown in Figure 11. The -3 dB cutoff frequency of the filters is roughly 20
Hz different when the RTD is at the maximum value near 390 . The dc magnitude of the results is based
on the current-to-voltage transfer function (I*R) as the excitation currents pass through the passive
resistors in the signal chain.
T
60.00
VIN_PGA
VREF_ADC
-3dB = 246.11 Hz
40.00 -3dB = 246.24 Hz
Gain (dB)
20.00
0.00
-20.00
1.00 10.00 100.00 1.00k 10.00k 100.00k 1.00M
Frequency (Hz)
Figure 11. Simulated Filter Frequency Response
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4.2 Error Calculations
4.2.1 Measurement Resolution
The smallest signal an n-bit data converter can theoretically resolve is given by its LSB size (least-
significant bit). An increase in input voltage by one LSB will increment the ADC output by one code.
Equation ( 34 ) calculates the weight of one LSB referred to the input of the PGA using VREF, Gain, and the
number of codes.
2 VREF 2 1.64 V
LSB ( V ) 48.88 nV
Gain 2 n
4
V
224
( 34 )
To calculate the theoretical achievable code step size in terms of resistance, divide the LSB size by the
excitation current used to excite the RTD, as shown in Equation ( 35 ).
LSB( V ) 48.88 nV
LSB() 48.88 ( 35 )
IIDAC 1 mA
Since the input-referred peak-to-peak noise of the ADS1247 at 20 SPS and Gain = 4 V/V is greater than
one LSB, a more appropriate resolution calculation replaces the converter LSB weight with the input-
referred noise specification. The ADC datasheet will typically provide the input-referred noise (in VPP or
VRMS) for different supply voltages, reference voltages, data rates, and gain settings.
The ADS1247 input-referred noise specification for the closest configuration to this system is 5.94 VPP
(see Table 5 in the ADS1247 datasheet). Equation ( 36 ) calculates the ADC resistance measurement
resolution based on the input-referred peak-to-peak noise (NoiseRTI_pp). The NoiseRTI_pp value is divided by
factor of two to show the resolution as a deviation from the mean value.
(NoiseRTI _ pp / 2) (5.94 VPP / 2)

ADCRES () 2.97 m ( 36 )
IIDAC 1 mA
The expected temperature resolution in degrees Celsius can be calculated by dividing the expected
resistance resolution by the RTD sensitivity () as shown in Equation ( 37 ). Appendix A.4 explains how
the value of changes over the RTD measurement temperature, ranging from 0.4323 /C at -200C to
0.2927 /C at 850C. Therefore, the temperature resolution will vary over the RTD temperature range,
even though the resistance measurement resolution will remain constant.
Equation ( 37 ) calculates the ADC resolution in degrees Celsius using the Pt100 sensitivity at 0C.
ADCRES () 2.97 m
ADCRES @ 0C (C) 0.0076C
@ 0C ( 37 )
0.39083
C
4.2.2 Measurement Accuracy
The expected accuracy of the design can be calculated using the specifications of the components
selected in Section 3. The units associated with these specifications range from volts, to percent full-scale
range (%FSR), to parts-per-million of full-scale (ppm). In order to calculate the total error, these different
errors sources must be converted to a common unit of measurement. In the following calculations, all
specifications will be converted to volts referred to the input (RTI) of the ADS1247.
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Gain errors will be referenced to the maximum differential input voltage, VIN_MAX = 390.48 mV (calculated in
Equation ( 16 ) in Section 3.1.3), to properly calculate the input-referred voltage errors.
4.2.2.1 Errors due to RREF
The tolerance of RREF will produce gain errors in the ADC transfer function as derived in Appendix A.6.
Assuming the tolerance is specified as a percentage, the transfer function gain error from the R REF
tolerance can be calculated from Equations ( 38 ) ( 39 ).
RREF Tol(%) 0.02% ( 38 )
RREF Tol(%) 0.02

Gain ErrorRREF Tol(%) 100 100 0.019996% ( 39 )
RREF Tol(%) 100 0.02 100
The error in volts due to the RREF tolerance can be calculated from the gain error and the maximum input
voltage.
Gain ErrorR REF Tol(%)

Gain ErrorR REF Tol( V ) VIN _ MAX
100
( 40 )
0.019996
Gain ErrorR REF Tol( V ) 390.48mV 78.0804 V
100
4.2.2.2 Errors due to ADS1247
The ADS1247 will cause errors due to the offset voltage, offset voltage drift, gain error, gain error drift,
integral nonlinearity (INL), and IDAC matching.
Offset voltage error and offset voltage error drift are commonly specified in an input-referred voltage and
can be directly entered from the device performance datasheet, if provided.
Offset ErrorADC( V ) 15 V ( 41 )
Gain errors are usually specified as a percentage of the full-scale ADC input range (%FSR), so the input-
referred voltage error can be calculated by multiplying by VIN_MAX. Equation ( 42 ) uses the typical gain
error of the ADS1247, but similar errors can be calculated using the maximum specifications as well.
Gain ErrorADC (%) 0.005

Gain ErrorADC ( V ) VIN _ MAX 390.48 mV 19.524 V ( 42 )
100 100
The INL is typically specified in either number of ADC codes or in ppm FSR. Because INL is not a gain
error, it must be multiplied by the full-scale input voltage of the ADC rather than VIN_MAX, as shown in
Equation ( 43 ).
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INL 2 VREF 6 ppm 2 1.64 V

INL ErrorADC ( V ) 4.92 V ( 43 )
1,000,000 Gain 1,000,000 V
4
V
The final errors considered for this system are caused by the mismatching of the IDAC current sources
which introduce a gain error in the transfer function as derived in Appendix A.7.
IIDAC Mismatch(%) 0.15

Gain ErrorIDAC (%) 100 100 0.07494% ( 44 )
IIDAC Mismatch(%) 200 0.15 200
Gain ErrorIDAC(%) 0.07494

Gain ErrorIDAC ( V ) VIN _ MAX 390.48 mV 292.626 V ( 45 )
100 100
The errors from the mismatch of the IDAC sources are the largest errors in the system. This reinforces the
importance of chopping the two IDAC current sources to remove these errors as described in Section
3.1.2.
4.2.2.3 Total Error
With all of the input-referred errors calculated in volts, the total error can be calculated by taking the root-
sum-of-square of all of the uncorrelated error terms. A similar calculation can be performed for the
maximum error by replacing the typical specifications with the maximum specifications. For cases where a
typical specification is not available, the maximum specification is used.
2 2 2
Gain ErrorR REF Tol Offset ErrorADC Gain ErrorADC
ErrorTotal( V )
2 2
INL ErrorADC Gain ErrorIDAC ( 46 )
ErrorTotal( V ) 303.903 V
The system errors and their resulting input-referred error in V are summarized in Table 4.
Table 4. Summary of Error Sources and Resulting Voltage Error RTI

Value Error RTI (V)
Error Source
Typ Max Typ Max
RREF Errors
RREF Tolerance - 0.02% - 78.1
ADS1247 Errors
Integrated Nonlinearity (INL) 6 ppm 15 ppm 4.92 12.3
Offset Voltage - 15 V - 15
Gain Error 0.005% 0.02% 19.52 78.1
IDAC Mismatch - 0.15% - 292.6
After removing the IDAC mismatch errors with chopping, a two-point gain and offset calibration can
remove the errors from the RREF tolerance, offset voltage, and gain error, leaving only the error from INL.
Table 5 compares the original unadjusted error with the errors after IDAC chopping and a two-point
calibration.
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Table 5. Total Error Voltage RTI

Total Error RTI (V)
Typ Max
Unadjusted Error at 25C 303.9 313.4
Unadjusted Error at 25C with IDAC 82.02 112.1
Chop
Calibrated Error at 25C 4.92 12.3
The magnitude of the IDAC source can be used to convert the calculated voltage error into a calculated
resistance error as shown in Equation ( 47 ). The results from Table 5 have been converted to resistance
accuracy in Table 6.
Error (V )
Error () ( 47 )
IIDAC (A )
Table 6. Total Error Resistance

Total Error RTI ()
Typ Max
Unadjusted Error at 25C with IDAC 0.082 0.112
Chop
The temperature accuracy can be calculated by dividing the resistance accuracy by the RTD sensitivity ()
at the desired calibration temperature. The RTD sensitivity is worst at 850C (see Appendix A.4). The
results in Table 7 display the Total Error in degrees Celsius at 0C.
Error ()
Error (C) ( 48 )
@ 0C
Table 7. Total Error Temperature

Total Error (C)
Typ Max
Unadjusted Error at 25C with IDAC Chop 0.21 0.287
Table 8 compares the calculated performance with the design goals from Table 1. It is necessary to chop
the IDAC sources to meet the desired un-calibrated precision resistance measurement accuracy.
Table 8. Comparison of Design Goals and Calculated Performance

Goal Calculated
Unadjusted Resistance Measurement 0.1 0.082
Accuracy
Calibrated Resistance Measurement 0.01925 0.0049
Accuracy
Calibrated Temperature Measurement 0.05C 0.013C
Accuracy
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5 PCB Design
Providing proper power supply decoupling, grounding, and minimizing cross-over between the analog and
digital circuitry return currents is required to achieve optimal performance in all mixed-signal PCB designs.
In addition to standard practices, minimizing or balancing PCB trace resistance is a primary concern
because the design is based on accurately measuring the resistance of the RTD. Implementing a 4-wire
Kelvin connection at the RTD and RREF resistors help to minimize PCB resistance in series with the sense
elements by separating the measurement sense and excitation current paths.
As discussed in Section 2.2.2, the lead resistances of the 3-wire RTD are effectively cancelled when they
are equal and the magnitude of the excitation current sources are also equal. The same theory applies to
PCB trace resistance in series with the three RTD leads. Therefore, the PCB trace resistances connecting
the IDAC and ADS1247 inputs to the RTD must be balanced, otherwise additional differential signals will
be formed. The resistance of the trace between the terminal block and the R REF resistor is common to both
the positive and negative inputs and is cancelled by taking a differential measurement. Balancing the RTD
trace resistance is accomplished by creating traces of equal length between the terminal block and the
ADS1247connection points. Figure 12 displays these critical PCB layout areas. The full PCB layout is
shown in Figure 13.
RREF Kelvin
Connection
RR1
CR_CM1
CR_DIFF
RREF
CR_CM2
RTD Terminal Block
RR2
RI1
CI_CM1
CI_DIFF
CI_CM2
RI2
RTD Kelvin
Connection
Figure 12. PCB Layout Highlighting Important PCB Layout Concerns
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Figure 13. Full PCB Layout
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6 Verification & Measured Performance
6.1 Measured Transfer Function with Precision Resistor Input

To test the accuracy of only the acquisition circuit, a series of calibrated high-precision discrete resistors
were used as the input to the system. Figure 14 displays the unadjusted resistance measurement
accuracy of the system over an input span from 20 to 400 . The offset error can be attributed to the
offset of the ADC, while the gain error can be attributed to the accuracy of the R REF resistor and the ADC.
A linear curve-fit has been applied to the results yielding the system gain and offset errors displayed in
Figure 14.
0.12
Resistance Measurement Error ()
0.1
0.08
0.06
Results
0.04
Linear (Results)
y = 0.0002719x - 0.0064178
0.02
-0.02
0 50 100 150 200 250 300 350 400
RRTD ()
Figure 14. Resistance Measurement Results with Precision Resistors Before Calibration
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Precision temperature measurement applications are typically calibrated to remove the effects of gain and
offset errors, which generally dominate the total system error. The simplest calibration method is a linear,
or two-point, calibration which applies an equal and opposite gain and offset term to cancel the measured
system gain and offset errors. Applying a gain and offset calibration yields the calibrated results shown in
Figure 15. More information regarding calibration can be found in Reference 5.
0.01
Resistance Measurement Error ()
0.005
Calibrated Results
-0.005
-0.01
0 50 100 150 200 250 300 350 400
RRTD ()
Figure 15. Resistance Measurement Results with Precision Resistors after Calibration
The results in Figure 15 can be converted to temperature accuracy by dividing the results by the RTD
sensitivity () at the measured resistance. Over the full resistance input range, the maximum total
measured error is 0.00415 . Equation ( 49 ) uses this measurement and the RTD sensitivity at 0C to
calculate the measured temperature accuracy.
Error () 0.00415
Error (C) 0.0106C
@ 0C ( 49 )
0.39083
C
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Figure 16 displays the calculated temperature accuracy of the circuit, not including any linearization related
errors of the RTD.
0.05
0.0375
0.025
Temperature Error (C)
0.0125
Calibrated Results
-0.0125
-0.025
-0.0375
-0.05
0 50 100 150 200 250 300 350 400
RRTD ()
Figure 16. Calculated Temperature Error from Resistance Measurement Error
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6.2 Noise Histogram

The peak-to-peak noise of the acquisition system can be approximated from an output code histogram.
The RTD was replaced with a 220 , 0.01% 0.05ppm/C precision resistor, to represent the RTD
resistance near mid-scale. Then 1,000 samples were recorded to generate the histogram plot shown in
Figure 17. The peak-to-peak voltage deviation in the histogram is roughly 3.45 VPP. The measured noise
is less than the value specified in the ADS1247 datasheet of 5.94 VPP for a 3.3 V supply and a 2.048 V
internal reference; however, the datasheet specifications do not exactly match this configuration.
Histogram
70
60
50
Frequency
40
30
ADC Readings
20
10
0
220043.349
220043.944
220044.538
220045.133
220045.727
220046.322
220046.916
220047.511
220048.105
220048.700
220049.294
220043.646
220044.241
220044.835
220045.430
220046.024
220046.619
220047.214
220047.808
220048.403
220048.997
Output Voltage (V)
Figure 17. Histogram with RRTD = 220
Enter the measured input-referred noise into Equation ( 50 ) to determine the measured resolution in
Ohms.
(NoiseRTI _ pp / 2) (3.45 VPP / 2)

ADCRES () 1.725 m ( 50 )
IIDAC 1 mA
The expected temperature resolution in degrees Celsius can be calculated by dividing the expected
resistance resolution by the RTD sensitivity () at 0C as shown in Equation ( 51 ).
ADCRES () 1.725 m
ADCRES @ 0C (C) 0.0044C
@ 0C ( 51 )
0.39083
C
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The temperature resolution falls well within the accuracy goal of 0.05C and can be observed in the
results in Figure 16. The noise can be further reduced by applying additional averaging or filtering in
software.
Table 9 compares the measured performance with the calculated performance and design goals from
Table 8. It is necessary to chop the IDAC sources to meet the desired un-calibrated precision resistance
measurement accuracy.
Table 9. Comparison of Design Goals, Calculated, and Measured Performance

Goal Calculated Measured
Unadjusted Resistance Measurement 0.1 0.082 0.096
Accuracy
Calibrated Resistance Measurement 0.01925 0.0049 0.00415
Accuracy
Calibrated Temperature Measurement 0.05C 0.013C 0.0106C
Accuracy
7 Modifications
This design can be easily modified for other RTD types and temperature ranges by changing the IDAC,
PGA, and RREF selections using the equations shown in the theory and component selection sections.
There are a few other fully integrated products available from TI that offer the same required building
blocks as the ADS1247 but feature different performance, channel count, and cost. Several of these
devices are listed in Table 10.
Table 10. Alternate Fully-Integrated ADC Solutions

ADC Resolution Differential PGA Range IDACs Noise Power
Inputs Magnitude Consumption
ADS1147(1) 16 2 1 128 V/V 50 A 1.5 mA 15.63 VRMS 1.4 mW
ADS1247(1) 24 2 1 128 V/V 50 A 1.5 mA 1.07 VRMS 1.4 mW
ADS1148(1) 16 4 1 128 V/V 50 A 1.5 mA 15.63 VRMS 1.4 mW
(1)
ADS1248 24 4 1 128 V/V 50 A 1.5 mA 1.07 VRMS 1.4 mW
ADS1120(1) 16 2 1 128 V/V 10 A 1.5 mA 15.63 VRMS 1.4 mW
ADS1220(1) 24 2 1 128 V/V 10 A 1.5 mA 1.15 VRMS 1.4 mW
LMP90100(2) 24 4 1 128 V/V 100 A 1 mA 4.29 VRMS 5.1 mW
(1) AVDD = 3.3 V, AVSS = 0 V, Internal Reference = 2.048 V, Data Rate = 20 SPS, PGA = 4 V/V
(2) AVDD = 3 V, AVSS = 0 V, Internal Reference = 3 V, Data Rate = 13.42 SPS, PGA = 4 V/V
Table 11 features other suitable ADC solutions that offer integrated PGAs.
Table 11. Alternate ADC + PGA Solutions

ADC Resolution Differential PGA Range Noise Power
Inputs Consumption
ADS1146(1) 16 1 1 128 V/V 15.63 VRMS 1.4 mW
ADS1246(1) 24 1 1 128 V/V 1.07 VRMS 1.4 mW
LMP90099(2) 24 4 1 128 V/V 4.29 VRMS 5.1 mW
(1) AVDD = 3.3 V, AVSS = 0 V, Internal Reference = 2.048 V, Data Rate = 20 SPS, PGA = 4 V/V
(2) AVDD = 3 V, AVSS = 0 V, Internal Reference = 3 V, Data Rate = 13.42 SPS, PGA = 4 V/V
Discrete current sources could be comprised of an integrated device such as the REF200 or a circuit such
as the designs featured in TIPD101 or TIPD107.
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8 About the Authors

Ryan Andrews is an applications engineer with the Precision Analog Delta-Sigma ADC team at Texas
Instruments, where he supports industrial and medical products and applications. Ryan received his BS in
Biomedical Engineering and his BA in Spanish from the University of Rhode Island.
Collin Wells is an applications engineer in the Precision Linear group at Texas Instruments where he
supports industrial products and applications. Collin received his BSEE from the University of Texas,
Dallas.
9 Acknowledgements & References

1. Luis Chioye, RTD Ratiometric Measurement and Filtering Using the ADS1148 and ADS1248
Family of Devices SBAA201, March 2013.
2. Robert Burnham and Nagaraj Ananthapadamanabhan, Example Temperature Measurement

Applications Using the ADS1247 and ADS1248 SBAA180, January 2011.
3. Collin Wells, Signal Conditioning and Linearization of RTD Sensors 2011 Texas Instruments
Technology Day Presentation.
TM
4. Omega , The Omega Temperature Measurement Handbook and Encyclopedia, Vol
TM th
MMXIV , 7 Edition.
5. Mock, Mike, 0-1A, Single-Supply, Low-Side, Current Sensing Solution, TIDU040
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Appendix A.
A.1 Electrical Schematic
Figure 18. Electrical Schematic
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A.2 Bill of Materials
Figure 19. Bill of Materials
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A.3 ADS1247 Register Settings

Table 12 lists the complete register settings for the ADS1247 used in this design. Registers with values
marked as xx change based on the internal calibration results specific to every ADS1247.
Table 12. ADS1247 Register Settings

Address Name Hex Value
00h MUX0 0A
01h VBIAS 00
02h MUX1 20
03h SYS0 22
04h OFC0 xx
05h OFC1 xx
06h OFC2 xx
07h FSC0 xx
08h FSC1 xx
09h FSC2 xx
0Ah IDAC0 96
0Bh IDAC1 03
0Ch GPIOCFG 00
0Dh GPIODIR 00
0Eh GPIODAT 00
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A.4 Pt100 RTD Information

The Pt100 RTD is a platinum-based RTD sensor. Platinum is a noble metal and offers excellent
performance over a wide temperature range. Platinum also features the highest resistivity of commonly
used RTD materials, requiring less material to create desirable resistance values. The Pt100 RTD has an
impedance of 100 at 0C and roughly 0.385 of resistance change per 1C change in temperature. The
resistance is 18.51 at -200C and 390.48 at 850C. Higher-valued resistance sensors, such as
Pt1000 or Pt5000, can be used for increased sensitivity and resolution.
Class-A RTDs are a good choice for this application to provide good pre-calibration accuracy and long-
term stability. A Class-A RTD will have less than 0.5C of error at 100C without calibration and the long-
term stability makes accurate infrequent calibration possible. Table 13 displays the tolerance, initial
accuracy and resulting error at 100C for the five main classes of RTDs.
Table 13. RTD Class Tolerance Information

Tolerance Class Tolerance Values (C) Resistance at 0C () Error at 100C (C)
(DIN-IEC 60751)
AAA(1) +/- (0.03 + 0.0005*t) 100 +/- 0.012 +/- 0.08
AA +/- (0.01 + 0.0017*t) 100 +/- 0.04 +/- 0.27
A +/- (0.15 + 0.002*t) 100 +/- 0.06 +/- 0.35
B +/- (0.3 + 0.005*t) 100 +/- 0.12 +/- 0.8
C +/- (0.6 + 0.01*t) 100 +/- 0.24 +/- 1.6
(1) AAA is not included in the DIN-IEC 60751 specification but is an industry accepted tolerance for performance demanding applications.
nd
For positive temperatures the CVD equations is a 2 -order polynomial Equation ( 52 ).
RTD(T) R0 [1 A(T) B(T)2 ] ( 52 )
For negative temperatures from -200C to 0C, the CVD equation expands to a 4th-order polynomial
shown in Equation ( 53 ).
RTD(T) R0 [1 A(T) B(T)2 C(T)3 (T 100)] ( 53 )
The coefficients in the Calendar Van-Dusen equations are defined by the IEC-60751 standard. R0 is the
resistance of the RTD at 0C. For a European standard Pt100 RTD the coefficients are:
R 0 100
A 3.9083 10- 3 C ( 54 )
B -5.775 10 -7
C
C -4.183 10 -12
C
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The change in resistance of a Pt100 RTD from -200C to 850C is displayed in Figure 20.
PT-100 RTD Resistance vs. Temperature

400
360
320
280
Resistance (Ohms)
240
RTD ( Temp) 200
160
120
80
40
0
200 95 10 115 220 325 430 535 640 745 850
Temp
Temperature (C)
Figure 20. Pt100 RTD Resistance from -200C to 850C
While the change in RTD resistance is fairly linear over small temperature ranges, Figure 21 displays the
resulting non-linearity if an end-point fit is made to the curve shown in Figure 20. The results show almost
4.5% non-linearity, or greater than 16C, illustrating the need for digital calibration.
Resistance Error and Nonlinearity %FSR

20 5
18 4.5
16 4
Resistance Nonlinearity (%)

Resistance Error (Ohms)
14 3.5
12 3
Nonlin Ohms( Temp) 10 2.5 Nonlin Error( Temp)
8 2
6 1.5
4 1
2 0.5
0 0
200 95 10 115 220 325 430 535 640 745 850
Temp
Temperature (C)
Figure 21. Pt100 RTD Non-Linearity from -200C to 850C
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Figure 22 displays the change in the sensitivity () of the RTD over the full temperature measurement
range.
Plot Difference Between RTD Resistance and a Linear Endpoint Fit vs. Temperature
0.5
0.47
0.44
0.41
RTD Sensitivity (Ohms/C)
0.38
( Temp) 0.35
0.32
0.29
0.26
0.23
0.2
200 95 10 115 220 325 430 535 640 745 850
Temp
Temperature (C)
Figure 22: RTD Sensitivity () vs. Temperature
The sensitivity of the RTD at a few selected temperatures over the full operating range is listed in Table
14.
Table 14. RTD Sensitivity at Selected Temperatures

Temperature (C) (/C)
-200 0.43233
-100 0.40531
0 0.39083
100 0.37928
200 0.36773
400 0.34463
600 0.32153
850 0.29266
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A.5 Error Calculations Including Temperature Drift

The calculations shown in this section are provided in supplement to the room temperature calculations
shown in Section 4.2.2. The calculations are performed over an operating temperature range of -40C to
+85C. The largest errors due to temperature drift occur at the operating temperature furthest from the
ambient temperature of 25C as shown in Equation ( 55 ).
TMAX 25C (40C) 65C ( 55 )
A.5.1 Errors caused by RREF Temperature Drift
The RREF drift specification must be multiplied by the temperature change and converted to a percentage
before performing the same calculations used for the RREF tolerance.
ppm ppm
RREF Drift 2 ( 56 )
C C
ppm ppm
RREF Drift (ppm) RREF Drift TMAX 2 65C 130 ppm ( 57 )
C C
RREF Drift (ppm) 130

RREF Drift (%) 100 100 0.013% ( 58 )
1,000,000 1,000,000
RREF Drift (%) 0.013

Gain ErrorRREF Drift (%) 100 100 0.01299% ( 59 )
RREF Drift (%) 100 0.013 100
The error in volts due to the RREF drift can be calculated by multiplying the gain error in percent by VIN_MAX.
Gain ErrorR REF Drift (%) 0.01299

Gain ErrorR REF Drift ( V ) VIN _ MAX 390.48 mV
100 100
( 60 )
Gain ErrorR REF Drift ( V ) 50.7234 V
A.5.2 Errors due to ADS1247 Temperature Drift
As the ambient temperature changes, the ADS1247 will produce errors due to offset drift, gain error drift,
and IDAC mismatch drift.
Offset error drift is commonly specified as an input-referred voltage and can be directly entered from the
device performance datasheet. The largest offset drift error will be at a system ambient temperature of
-40C (See Figure 15 in the ADS1247 datasheet).
Offset ErrorADC Drift ( V ) 1 V ( 61 )
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If offset drift is specified in V/C then it will first be multiplied by TMAX to determine the final offset voltage
due to temperature drift.
Like gain error, gain error drift in the ADS1247 datasheet is specified as %FSR. The largest gain drift error
will be at a system ambient temperature of -40C (See Figure 23 in the ADS1247 datasheet).
Gain ErrorADC Drift (%) 0.01

Gain ErrorADC Drift ( V ) VIN _ MAX 390.48 mV 39.048 V ( 62 )
100 100
If gain error drift is specified in ppm/C, then it must first be converted into Gain ErrorADC Drift (%) similar to
the conversion performed in Equations ( 56 ) ( 58 ).
The IDAC mismatch drift is commonly specified in ppm/C. First, calculate the IDAC mismatch in %FSR
based on the drift specification and TMAX.
IIDAC Mismatch Drift (ppm)

IIDAC Mismatch Drift (%) TMAX 100
1,000,000
( 63 )
10
IIDAC Mismatch Drift (%) 65C 100 0.065%
1,000,000C
The gain error caused by the IDAC mismatch drift can be calculated in %FSR using the same calculations
shown in Appendix A.7 and then converted to volts.
IIDAC Mismatch Drift (%) 0.065

Gain ErrorIDAC Mismatch Drift (%) 100 100
IIDAC Mismatch Drift (%) 200 0.065 200
( 64 )
Gain ErrorIDAC Mismatch Drift (%) 0.03249%
Gain ErrorIDAC Mismatch Drift (%) 0.03249

Gain ErrorIDAC Mismatch Drift ( V ) VIN _ MAX 390.48 mV
100 100
( 65 )
Gain ErrorIDAC Drift ( V ) 126.9 V
The error from the IDAC mismatch drift can be removed if the IDAC sources are chopped as described in
Section 3.1.2.
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A.5.3 Total Error over Temperature
With all of the input-referred errors calculated in volts, the total error can be calculated by taking the root-
sum-of-square of all of the uncorrelated ambient temperature and temperature drift error terms.
2 2 2
Gain ErrorR REF Tol Gain ErrorR REF Tol Drift Offset ErrorADC
2 2 2
ErrorTotal( V ) Offset ErrorADC Drift Gain ErrorADC Gain ErrorADC Drift
2 2 2 ( 66 )
INL ErrorADC Gain ErrorIDAC Gain ErrorIDAC Mismatch Drift
ErrorTotal( V ) 303.9 V
The system errors over temperature and their resulting input-referred errors in V are summarized in
Table 15.
Table 15. Summary of Error Sources and Resulting Voltage Error RTI over Temperature
Value Input-Referred Error (V)
Error Source
Typ Max Typ Max
RREF Errors
RREF Tolerance - 0.02% - 164
RREF Drift - 2 ppm/C - 106.6
ADS1247 Errors
Integrated Nonlinearity (INL) 6 ppm 15 ppm 4.92 12.3
Offset Voltage - 15 V - 15
Offset Voltage Drift 1 V 1
Gain Error 0.005% 0.02% 19.52 78.1
Gain Error Drift 0.01% 0.015% 39.05 58.57
IDAC Mismatch - 0.15% - 292.6
IDAC Mismatch Drift - 10 ppm/C - 126.9
The IDAC mismatch errors can be removed by chopping the IDAC sources as described in Section 3.1.2.
A two-point gain and offset calibration can remove the errors from the R REF tolerance, offset voltage, gain
error, and IDAC mismatch leaving only the error from INL and temperature drift errors. Table 16 compares
the unadjusted error with the error after chopping the IDAC sources and performing a two-point gain and
offset calibration at 25C and over temperature.
Table 16. Total Error Voltage RTI over Operating Temperature

Total Error (V)
Typ Max
Unadjusted Error over Temp 335.5 346.9
Unadjusted Error over Temp with IDAC Chop 104.1 136.3
Calibrated Error over Temp 142.2 149.2
Calibrated Error over Temp with IDAC Chop 64.2 78.5
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The magnitude of the IDAC source can be used to convert the calculated voltage error into a calculated
resistance error in Ohms as shown in Equation ( 47 ). The results from Table 16 have been converted to
resistance accuracy in Table 17.
Table 17. Total Resistance Error over Operating Temperature

Total Error ()
Typ Max
With the resistance accuracy known, the final temperature accuracy can be calculated by dividing the
resistance accuracy by the change in the RTD resistance per degree Celsius. The results in Table 18 use
the sensitivity at 0C of 0.3908/C.
Table 18. Total Temperature Error over Operating Temperature

Total Error (C)
Typ Max
A.6 Derivation of the Errors from RREF Tolerance

The ideal transfer function will be compared to a modified transfer function to determine the effects of R REF
tolerance on the system accuracy. The ideal transfer function is shown again in Equation ( 67 ).
RRTD
CodeIDEAL CodesTOTAL ( 67 )
4 RREF
If RREF is substituted with (RREF+RREF*) in the ideal transfer function, then it simplifies to Equation ( 68 ).
RRTD
CodeRREF Error CodesTOTAL
4 RREF RREF
( 68 )
Equation ( 69 ) calculates the gain error caused by the RREF tolerance by comparing the calculated error
transfer function to the ideal transfer function.
CodeRREF Error CodeIDEAL

Gain ErrorRREF Tol(%) ( 69 )
CodeIDEAL 1
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If RREF is substituted with RREF-RREF* to calculate the effects of a decrease in RREF, the polarity of the gain
error will be positive.
Assuming the tolerance is specified in %, the gain error can be calculated as shown:
RREF Tol(%)
Gain ErrorRREF Tol(%) ( 70 )
RREF Tol(%) 100
A.7 Derivation of the Errors from IDAC Mismatch

The ideal transfer function will be compared to a modified transfer function to determine the effects of a
mismatch in the IDAC current sources on the system accuracy. The ideal transfer function is shown again
in Equation ( 71 ).
RRTD
CodeIDEAL CodesTOTAL ( 71 )
4 RREF
However, if I2 is set equal to (I1+ I1*) in Equation ( 7 ), the transfer function simplifies to Equation ( 72 ).
RRTD
CodeIDAC Mismatch Error CodesTOTAL ( 72 )
4 RREF 2
Equation ( 73 ) calculates the gain error caused by the IDAC mismatch by comparing the calculated error
transfer function to the ideal transfer function.
CodeIDAC Mismatch Error CodeIDEAL

Gain ErrorIDAC Mismatch Drift (%) ( 73 )
CodeIDEAL 2
If I1 is substituted with I2+ I2*, the polarity of the gain error will be positive.
Assuming the IDAC mismatch is specified in %FSR, the gain error can be calculated as shown in Equation
( 74 ).
IIDAC Mismatch Drift (%)

Gain ErrorIDAC Mismatch Drift (%) ( 74 )
IIDAC Mismatch Drift (%) 200
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3-Wire RTD Measurement System Reference Design, - 200°C To 850°C

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Ryan Andrews, Collin Wells

TI Designs Precision: Verified Design

TI Designs Precision Circuit Description

RTD Type: 3-Wire Pt100

Temperature Measurement Range: -200C to 850C

Temperature Measurement Accuracy: 0.05C at TA = 25C

System Supply Voltage (VDUT): 5 V

ADC Supply Voltage (AVDD): 3.3 V

Table 1. Comparison of Design Goals and Measured Performance

2.1 Resistance Temperature Detector (RTD) Overview

2.2 RTD Resistance Measurement

Figure 2. Simplified RTD Application

VDIFF VIN VIN I1 RRTD (1)

2.2.1 Ratiometric Measurements

VIN- REFP REFN

Figure 3. Ratiometric RTD Measurement

VREF VCM I1 RREF (2)

VDIFF VRTD I1 RRTD (4)

VREF I1 RREF (5)

V Gain RRTD Gain

2.2.2 Current Sources

Figure 4. 3-Wire RTD Lead Resistances Canceled by Excitation Currents

VIN = I (RLEAD RRTD ) + 2 I (RLEAD + RREF )

VIN- = I RLEAD 2 I (RLEAD + RREF )

VDIFF = VIN - VIN- = I RRTD ( 10 )

VIN VCM (I1 RRTD ) VCompliance ( 13 )

Excitation Current (A)

2.2.3 Amplification Stage

VIN _ ADC I1 RRTD Gain ( 14 )

2.2.4 Input and Reference Low-Pass Filters

CI_CM2 REFP REFN

Figure 6. Input and Reference Low-Pass Filtering

3.1 ADC ADS1247

Figure 7. Ratiometric RTD System Featuring the ADS1247

3.1.1 Current Source (IDAC) Configuration

Table 2. Register Settings for Current Sources

3.1.2 IDAC Multiplex Chopping

3.1.3 Programmable Gain Amplifier (PGA) Configuration

RRTD@ 850C 390.48 ( 15 )

VIN _ MAX RRTD@ 850C IIDAC 390.48 1 mA

Table 3. Register Settings for PGA

3.2 Passive Components

VIN _ MAX Gain VIN _ MAX Gain

881 mV VCM 2.42 V

AIN0 AVDD 0.7 V 2.6 V ( 21 )

AIN0 VCM VIN _ MAX 1.64 V 390.48 mV 2.03 V ( 22 )

3.2.2 Input and Reference Low-Pass Filters

RI1 RI2 9.09 k ( 23 )

CI _ CM1 CI _ CM2 3.3 nF ( 25 )

f 3dB _ CM = 4.76 kHz

f 3dB _ CM = 4.87 kHz

CR _ CM1 CR _ CM2 1.5 nF ( 30 )

f 3dB 5.10 kHz

f 3dB 5.31 kHz

3.3 Low-Dropout (LDO) Linear Regulator

Figure 8. LDO Configuration for +3.3 V Output

4 Simulation and Error Calculation

IDAC1 VREF_INT ADS1247 PGA

4.1.1 RTD Transfer Function