Tidudp 0

TI Designs: TIDA-01527
Discrete Resolver Front-End Reference Design With

C2000™ Microcontroller and ±0.1° Accuracy
Description Features
This reference design is an excitation amplifier and • Minimalist Approach on 1-in2 Four-Layer PCB
analog front end for resolver sensors. The design • Industry Standardized Components
implements only discrete components and standard • Low Cost
operational amplifiers (op amps) on a 1-in2 printed-
circuit board (PCB). The provided algorithm and code • Example Firmware for TMS320F28069M C2000™
example uses a C2000™ microcontroller (MCU) MCU Including Source Code
LaunchPad™ Development Kit with the • Undersampling Algorithm for Angle Calculation
TMS320F28069M MCU for signal processing and • Allows for Performance Upgrade
angle calculation. The reference design uses an
innovative, scattered-signal processing method (see • ±0.25° Angle Readout Accuracy or ±0.1° Using
Section 3). This method improves the system accuracy Innovative Scattering Signal Processing Method
by 250% while maintaining hardware costs and
complexity to a reasonable level. Applications
• AC Drive Position Feedback
The TIDA-01527 is a low-cost companion design for
the TIDA-00796 and TIDA-00363 reference designs. • HEV/EV - Inverter and Motor Control
These designs are based on the PGA411-Q1 and offer • E-Bike
advanced features such as protections and • Servo Drive Position Feedback
diagnostics.
Resources
TIDA-01527 Design Folder

TLV4171 Product Folder
TLV431B-Q1 Product Folder
TMS320F28069M Product Folder
ASK Our E2E Experts
C2000Œ /DXQFK3DGŒ RESOLVER SENSOR

TIDA-01527
PWR EXC+
AMP
ACTIVE LOW-
PHASE
PWM PASS SECOND- ±
SPLITTER
1 ORDER FILTER
PWR EXC+
AMP
Ä
COS
DIFF
ADC1
AMP
COS+
DIFF
ADC2
AMP COS± SIN
CROSSBAR
(OPTIONAL)
SIN+
DIFF
ADC3
AMP SIN±
GPIO
2
Copyright © 2018, Texas Instruments Incorporated
TIDUDP0 – March 2018 Discrete Resolver Front-End Reference Design With C2000™ Microcontroller 1
Submit Documentation Feedback and ±0.1° Accuracy
System Description www.ti.com
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Description
High-performance motor control applications traditionally require a speed or position sensor for the control
loop feedback. Various methods and new algorithms are available which may eliminate the requirement
for a physical sensor; however, many applications cannot achieve the required performance and reliability
through sensorless control. Examples include traction inverters for hybrid-electric vehicles (HEV) and
electric vehicles (EV), electric power steering, motor drives and servos in industrial applications. A resolver
is one of the most popular angular sensors due to its reliability (even in an harsh environment) and the
ratiometric output, which suppresses common-mode noise.
This discrete resolver front-end reference design provides a simple implementation of a resolver interface.
The design uses a small PCB which implements an excitation amplifier for the primary winding and the
analog signal front end for the feedback windings. The PCB connects to the C2000 LaunchPad with the
TMS320F28069M MCU over a flat ribbon cable or by using a small PCB adapter. The provided code
example for the MCU uses the undersampling algorithm for readback signals demodulation and the arc
tangent goniometric function for the angle calculation.
Components used in this design have been rated for automotive applications or have an automotive-
qualified alternative. The guide also suggests more customized components with higher integration for
performance upgrade.
NOTE: The TIDA-01527 reference design has not been tested for any automotive or industrial
requirements (for example, functional safety or electromagnetic compatibility). The design
serves as a practical guidance and inspiration for the customer's system implementation.
1.1 Key System Specifications
Table 1. Key System Specifications

PARAMETER SPECIFICATIONS
Resolver excitation voltage Typically 4 VRMS or 7 VRMS
Input voltage 12 V to 15 V
Resolver excitation frequency Scalable, optimized for 5 kHz
PCB dimensions 25.4 mm × 25.4 mm
Output signal levels 0 V to 2.54 V
Supported excitation current < 80 mA, upgrade possible
Protection mechanisms (e.g. current,
voltage, temperature, electrostatic None
discharge (ESD))
Sine-wave-modulated pulse width modulation (PWM), fixed
Excitation amplifier modulation
frequency f = 312.5 kHz, variable duty cycle
Accuracy ±0.25° angle readout accuracy or ±0.1° using the innovative
scattering signal processing method (see Test Results)
Resolution 12 b
2 Discrete Resolver Front-End Reference Design With C2000™ Microcontroller TIDUDP0 – March 2018
and ±0.1° Accuracy Submit Documentation Feedback
www.ti.com System Overview
2 System Overview
The TIDA-01527 reference design consists of a host MCU and resolver sensor. The host MCU generates
a pulse-width modulated (PWM) signal with a variable duty cycle. The duty-cycle modulation matches the
desired resolver excitation frequency. The second-order active low-pass filter only preserves the excitation
frequency and converts the PWM signal into a harmonic signal. The analog phase-splitter circuit splits the
harmonic signal into two complementary harmonic signals. Two power amplifiers boost these harmonic
signals to match the resolver excitation voltage levels. A set of difference amplifiers monitor all resolver
windings and interface to the analog-to-digital converter (ADC) in the host MCU. The system uses an
optional analog crossbar circuit for advanced analog processing techniques, system calibration, and basic
diagnostics. For details on the scattered signal processing method, see Section 3.
Figure 1 shows the reference design from the top and the bottom side.
Figure 1. TIDA-01527 Board (Top and Bottom)
System Overview www.ti.com
2.1 Block Diagram

Figure 2 shows a block diagram of the TIDA-01527 reference design, host MCU, and resolver sensor.
C2000Œ /DXQFK3DGŒ RESOLVER SENSOR

TIDA-01527
PWR EXC+
AMP
ACTIVE LOW-
PHASE
PWM PASS SECOND- ±
SPLITTER
1 ORDER FILTER
PWR EXC+
AMP
Ä
COS
DIFF
ADC1
AMP
COS+
DIFF
ADC2
AMP COS± SIN
CROSSBAR
(OPTIONAL)
SIN+
DIFF
ADC3
AMP SIN±
GPIO
2
Figure 2. TIDA-01527 Block Diagram
2.2 Highlighted Products
2.2.1 TLV4171
The TLVx171 family of devices is a 36-V, single-supply, low-noise operational amplifier (op amp) with the
ability to operate on supplies ranging from 2.7 V (± 1.35 V) to 36 V (±18 V). This series is available in
multiple packages and offers low offset, drift, and low quiescent current. The single, dual, and quad
versions all have identical specifications for maximum design flexibility.
Unlike most op amps, which are specified at only one supply voltage, the TLVx171 family of devices is
specified from 2.7 V to 36 V. Input signals beyond the supply rails do not cause phase reversal.
The TLVx171 family of devices is stable with capacitive loads up to 200 pF. The input can operate
100 mV below the negative rail and within 2 V of the top rail during normal operation. The device can
operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of
the top rail.
The TLVx171 op amp family is specified from –40°C to +125°C.
2.2.2 TLV431x-Q1
The TLV431x-Q1 device is a low-voltage three-terminal adjustable voltage reference with specified
thermal stability over applicable industrial, automotive, and commercial temperature ranges. The output
voltage can be set to 1.24 V on stand-alone mode or any value between VREF (1.24 V) and 6 V with two
external resistors. These devices operate from a lower voltage (1.24 V) than the widely-used TL431 and
TL1431 shunt-regulator references. When used with an optocoupler, the TLV431 device is an ideal
voltage reference in isolated feedback circuits for 3-V to 3.3-V switching-mode power supplies. These
devices have a typical output impedance of 0.25 Ω. Active output circuitry provides a very-sharp turnon
characteristic, making them excellent replacements for low-voltage Zener diodes in many applications,
including onboard regulation and adjustable power supplies.
2.2.3 C2000™ TMS320F28069M MCU

The F2806x Piccolo™ family of microcontrollers (MCUs) provides the power of the C28x core and control
law accelerator (CLA) coupled with highly-integrated control peripherals in low pin-count devices. This
family is code-compatible with previous C28x-based code, and also provides a high level of analog
integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the high-
resolution pulse width modulator (HRPWM) module to allow for dual-edge control (frequency modulation).
Analog comparators with internal 10-bit references have been added and can be routed directly to control
the ePWM outputs. The ADC converts from a 0- to 3.3-V fixed full-scale range and supports ratio-metric
VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.
2.3 System Design Theory

The following chapters describe the system design in the order which corresponds to the signal flow.
• PWM Generation (C2000, software)
• Active Low-Pass Second-Order Filter and Phase Splitter (hardware)
• Power (Excitation) Amplifiers (hardware)
• Resolver Sensor (hardware)
• Crossbar—Optional (hardware)
• Analog Front-End Difference Amplifiers (hardware)
• A/D Conversion and Signal Processing (C2000, software)
2.3.1 PWM Generation

The C2000 MCU generates a PWM signal with a fixed frequency and variable duty cycle. The PWM
period is significantly higher than the period of the resolver excitation signal. Figure 3 shows the PWM
stream (not in scale).
3.3
PWM STREAM
MODULATION
0
0
255
0
255
Note: X-axis is not in scale
Figure 3. PWM Generation From MCU
Every new period of the PWM triggers an interrupt service routine where the controller calculates a new
duty cycle using the sinus function. The period of the PWM modulator is set as per Equation 1.
TPWM 2n u TSYSCLK (1)
This method allows conversion of the excitation signal into a discrete time signal with an n-bit resolution.
An internal variable-counter counts every interrupt from 0 to 2n – 1 and automatically resets when it
reaches 2n. The software example uses the IQ math library. After casting the internal variable-counter to
IQn number, the result takes the value between 0..1, which corresponds to 0..2π angle on the unity circle.
For this reason, the internal variable-counter is called the excitation angle, or ExcAngle. This variable is
very important because all signal processing refers to it.
The designer can also adjust the PWM duty-cycle modulation index (depth). Typically, the modulation
index is 1.0, which corresponds to a duty cycle from 0% to 100%. When set to 0.5, the duty cycle varies
from 25% to 75%. This variation reduces the output amplitude of the excitation signal. For this reason, the
modulation index variable is called ExcGain and may be used to fine-tune the output amplitude. Note that
lowering the modulation index reduces the effective resolution and increases harmonic distortion of the
excitation signal.
Another important aspect to understand is that the required bit-resolution n and the system clock period
TSYSCLK define the period TPWM of the generated PWM signal, as per Equation 2. A lower resolution
increases the total harmonic distortion (THD) while a lower operating frequency requires a higher-order
low-pass filter.
TEXC
TPWM
2n (2)
Finally, the MCU sets the duty cycle, as per Equation 3:
duty 0.5 u ª¬1 sin ExcAngle u ExcGain º¼
(3)
where,
• duty = 0…1,
• ExcAngle = 0…2π,
• ExcGain = 0…1.
Adding 1 ensures that the duty cycle is always positive with the center at 0.5.
Example calculation for TIDA-01527:
Desired excitation frequency fEXC = 5 kHz → TEXC = 200 µs
System clock fSYSCLK = 80 MHz → TSYSCLK = 12.5 ns
Choosing PWM resolution = 8 b
PWM period as per Equation 4:
TPWM 28 u 12.5 ns 3.2 Ps (4)
The excitation angle variable resolution per Equation 1 then turns into Equation 5
§T · § 200e 6 ·
log ¨ EXC ¸ log ¨ ¸
TPWM
TEXC
on © TPWM ¹ © 3.2e 6 ¹ 5.96 Ÿ 6 bit
2n log 2 log 2 (5)
2.3.2 Active Low-Pass Second-Order Filter and Phase Splitter

Figure 4 shows a simplified magnitude spectrum of the generated PWM signal described in Section 2.3.1.
Magnitude
Resolver Excitation Frequency
PWM carrier and harmonics
1st
Harmonic
2nd
distortion due
to finite PWM 3rd
resolution
4th
...
0
fEXC
fPWM
f [Hz]
Figure 4. Magnitude Spectrum of Generated PWM Signal
A properly-set low-pass filter suppresses the PWM carrier and harmonics to a minimum but passes the
resolver excitation signal content, as Figure 5 shows. This process converts the modulated PWM stream
to a sine wave. Note that increasing the difference between fEXC and fPWM lowers the requirement for filter
rolloff (filter order). Setting the DC gain and the rolloff point is worth the practical experiment. The DC gain
compensates for the excitation frequency attenuation and different combinations provide different results.
Matching the –3-dB cutoff to the excitation frequency is the starting point when designing the filter.
H [dB]
DC Gain
PASS BAND TRANSITION BAND STOP BAND

0
0
fEXC
fPWM
f [Hz]
Figure 5. Suggested Low-Pass Filter Response for PWM Signal Filtering
The reference design uses a second-order low-pass active filter with a multiple feedback topology, as
Figure 6 shows.
VCC
R1 R2
12.0k 10.0k
EXC_P
R5
3.90k
R8
20.0
C3
1000pF
4
U1C
3
PWM R9 R10 9 TLV4171IDR
3.90k 15.0k V+ 8 1 Q3
C
10 V-
fc=9.6 kHz
2
K=-1
11
EXC_N
C4 R11 R12
4700pF 3.00k 10.0k
GND Copyright © 2018, Texas Instruments Incorporated
Figure 6. Multiple-Feedback Filter (MFB) in TIDA-01527
During development, this topology was proven to be a better solution rather than the popular Sallen-Key
topology. Another benefit is that the resistor divider (R1, R11), which sets the DC offset, connects to the
high-impedance non-inverting input of the op amp. The Sallen-Key filter requires buffering for floating
ground (DC offset), which adds to the circuit complexity. R5 and R9 set the DC gain of the filter as per
Equation 6.
R5 3900
ADC 1
R9 3900 (6)
Equation 7 calculates the –6-dB cutoff frequency of the filter.
1
¦c 6 db
2S R5 u R10 u C4 u C3
1
¦c 6 db
2S 3900 u 15000 u 4.7 e 9 u 1e 9
¦c 6 db +] (7)
Equation 8 calculates the more-common approximation of a –3-dB cutoff from the –6-dB point.
§ 1· § 1·
¨n¸ ¨n¸
¦c ¦c © ¹ © ¹ +]
3 db 6 db (8)
NOTE: The cutoff frequency is typically identified as the point where the transfer function of a filter
drops by –3 dB. This drop corresponds to approximately half of the power transfer. However,
higher-order filters have a steeper rolloff (for example: –40 dB/dek for a second-order filter)
and the cutoff frequency is defined as n(–3 dB) where n is the filter order. This definitionoften
causes confusion because some technical articles or online calculators use formulas
referring to the –3-dB point whereas others use n(–3 dB). TI recommends checking the
calculation using a simulation tool.
As Section 2.3.4 describes, a resolver is a transformer. Eliminating any DC current through the primary
winding is important to avoid magnetic circuit saturation. For this reason, the system uses differential
excitation with two output amplifiers with a phase shift of 180°. The resolver then registers only the
differential voltage VR as per Equation 9:
VR VEXC VDC VEXC VDC (9)
where,
VEXC VEXC (10)
and then,
VR 2 u VEXC (11)
A simple analog phase splitter using the transistor Q3 and resistors (R2, R12) creates well-matched
complementary sine waves, as per Equation 10. The resistor R8 compensates for the intrinsic emitter
resistance of Q3. This compensation helps to roughly match output impedances between the collector and
emitter node.
2.3.3 Power (Excitation) Amplifiers

A pair of excitation amplifiers directly drive the primary winding of the resolver sensor. Both amplifiers are
identical, so this documentation only describes the first one. The amplifier is practically a single-supply
audio amplifier with a band-pass filter response. Figure 7 shows the circuit diagram.
VCC
C1
R3 R4
10.0k 4.70k
3
18pF
C2 1 Q1
EXC_P R6 R7 EXC+ BC817-25,215
100k 470k
2
0.01 µF
3
4
U1A 1 Q2 R15
fc1=160 Hz BC817-25,215 10.0
2 TLV4171IDR
K=-4.7
V+ 1 EXC+
2
fc2=18.8 kHz A
2
VCC/2 3 V-
1 Q4 R24
BC807-40LT1G 10.0
11
1 Q5
BC807-40LT1G
3
R13 R14
10.0k 4.70k
GND Copyright © 2018, Texas Instruments Incorporated
Figure 7. TIDA-01527 Excitation Amplifier—Single Channel
Resistors R3 and R13 create a virtual ground and set the DC offset to the middle of the operating voltage
range. Resistors R6 and R7 set the pass-band gain as per Equation 12 . Note that keeping these resistors
reasonably high is important because R6 also defines the input impedance of the power stage.
R7 470e3
APASS BAND 4.7
R6 100e3 (12)
The power stage is AC-coupled because the virtual ground (DC offset) of the power stage does not match
the EXC_P, EXC_N outputs of the phase splitter. The capacitor C2 and resistor R6 set the lower cutoff
frequency as per Equation 13. The cutoff frequency is set significantly lower than the excitation frequency
to prevent signal of interest attenuation.
1 1
¦low 3 dB +]
2S u R6 u C2 2S u 100e3 u 10e 9 (13)
Equation 14 defines the upper cutoff frequency of the amplifier. Similar to the low-pass filter in
Section 2.3.2, the designer must set the cutoff frequency as low as possible to further reduce the PWM
spectral content but high enough to pass the excitation frequency without attenuation.
1
fhigh 3 dB
2S u C1 u R7
1
fhigh 3 dB
2S u 18e 12 u 470e3
fhigh 3 dB 18.81 kHz (14)
Texas Instruments offers integrated power amplifiers that fit this application. An integrated solution solves
many problems, such as:
• Output stage biasing
• Crossover distortion
• Overcurrent protection
• Temperature protection
• Temperature (runaway) stability
Adding these features by using discrete components usually results in very complex circuits which are
typically known for their use in high-end audio amplifiers.
Recommended parts: ALM2402, OPA564-Q1
Verifying the minimal slew rate for the excitation amplifier is also very important. Equation 15 defines the
minimal slew-rate SR.
65min t ¦EXC u S u 9amp (15)
where,
• Vamp is the amplitude (single-ended) of the generated sine wave.
Figure 8 shows the relationship between excitation frequency, resolver excitation voltage, and the
amplifier slew rate for applications using the differential type of an excitation amplifier.
0.33
4-VRMS
0.30 7-VRMS
0.27
0.24
0.21
Slew-Rate (V/Ps)
0.18
0.15
0.12
0.09
0.06
0.03
0.00
1 2 3 4 5 6 7 8 9 10
fexc (kHz) D001
Figure 8. Minimum Required Slew Rate per Amplifier (Single-Ended) for 4-VRMS and 7-VRMS Resolvers
2.3.4 Resolver Sensor

A resolver uses the principle of a rotating transformer with a single primary winding and two secondary
windings positioned in a right angle from each other (see Figure 9). The generated sine wave VR excites
the primary winding and creates the magnetic flux Φ, which is distributed through secondary windings with
respect to the rotor angle ϴ. Equation 16 then calculates the rotor angle ϴ from the ratio of voltages VS,
VC on the secondary windings.
VR
, VR
VS VS
VC
VC
Figure 9. Resolver as Rotating Transformer

VS sin 4 u VR u TS
VC cos 4 u VR u TS
sin 4 u VR u TS sin 4 VS
cos 4 u VR u TS cos 4 VC
VS VS
tan 4 o4 arctan
VC VC (16)
Understanding the spectral content of a resolver sensor is important. The signal that each resolver
winding produces is amplitude modulated with a modulation index of m = 2 (overmodulation). When a
resolver is steady and at a fixed angle (highlighted by the green color in Figure 10), then the output
spectrum only has a single spectral line at the excitation frequency fEXC, unless the output signal has zero
amplitude (every 180°). When a resolver spins with angular frequencyfVELOCITY (highlighted by red color in
Figure 10), then the effect of overmodulation (m = 2) completely suppresses the carrier (excitation)
frequency fEXC. This effect is important to consider when designing a signal processing algorithm.
Magnitude
Resolver Excitation Frequency
Lower and Uper Sideband
fEXC -fVELOCITY
fEXC
fEXC -fVELOCITY
f [Hz]
Figure 10. Magnitude Spectrum of Resolver Sensor Output Signal
For further details on resolvers, see EMC Compliant Single-Chip Resolver-to-Digital Converter (RDC)
Reference Design or Synchro and Resolver Engineering Handbook.
2.3.5 Crossbar—Optional
A pair of CMOS multiplexers (U5, U6) form an analog crossbar, as Figure 11 shows. This crossbar is an
experimental circuitry further used in the signal processing algorithm. This circuit also allows for swapping
input signals between each difference amplifier or the complete disconnection of resolver windings. This
circuitry, together with an advanced algorithm in the MCU, reduces system error and enables basic
diagnostics features. Transistors Q10A, Q10B and resistors R48, R48 convert logic levels from the MCU.
U5 U6
14 O/I AX OR AY I/O AX 12 ISIN- 14 O/I AX OR AY I/O AX 12 ICOS-
I/O AY 13 ICOS- I/O AY 13 ISIN-
SIN- 11 A
COS- 11 A
CTRL_CMOS 15 O/I BX OR BY I/O BX 2 ISIN+ 15 O/I BX OR BY I/O BX 2 ICOS+
I/O BY 1 ICOS+ I/O BY 1 ISIN+
SIN+ 10 B
COS+ 10 B
4 O/I CX OR CY I/O CX 5 4 O/I CX OR CY I/O CX 5
I/O CY 3 I/O CY 3
9 9
GND C GND C
INH_CMOS 6 INH 6 INH
VEE 7 VEE 7
16 8 16 8
VCC VDD VSS VCC VDD VSS
VCC VCC CD4053BPWRG3 CD4053BPWRG3
GND GND
R48 R49
2.20k 2.20k
CTRL_CMOS INH_CMOS
6
CTRL 2 INH 5
1
Q10A Q10B
DMC564040R DMC564040R
GND GND
Figure 11. Analog Crossbar (Experimental)
2.3.6 Analog Front-End Difference Amplifiers

The system uses three difference amplifiers for the feedback.
Figure 12 shows the first amplifier, which monitors the excitation outputs. Monitoring the excitation
amplifier is extremely useful because a diagnostic routine in the MCU can compensate the tolerances of
parts and precisely adjust the output voltage using the ExcGain variable. Additionally, this monitoring
enables the system to measure the phase lag of the active filter and excitation amplifier or detect a faulty
excitation amplifier. Set the DC gain of the difference amplifier per Equation 17.
R19 10k
A 0.1 when R19 R23 and R20 R22
R20 100k (17)
The resistor R21 and capacitor C7 form a charge bucket filter for the ADC. The difference amplifier uses
the DC offset (VREF1/2) to match the bidirectional signal from the resolver with the single-ended ADC
input.
VCC
R19 R20 EXC-

10.0k 100k
4
13
OEXC R21 14 V+
D R22
10.0 V- 12 EXC+
U1D 100k
TLV4171IDR
11
C7 R23
15pF 10.0k
GND
VREF1/2
Figure 12. Excitation Amplifier Output Monitoring
The other two difference amplifiers monitor the sinus and cosinus windings from the resolver sensor.
Because both amplifiers are identical, this documentation only describes the first one (see Figure 13).
VCC
R26
100k
IS IN-
R28 R29 R30 SIN-
DNP
10.0k 51.0k 0
R31 C12
8
100k 1µF
2
OSIN R32 1 V+
A R33 R34
10.0 V- 3 SIN+
DNP
U3A 51.0k 0
IS IN+
TLV2171IDR
4
C15 R35 R36
15pF 10.0k 62.0k
GND
VREF1/2
Figure 13. Resolver Feedback Winding Monitoring
Set the DC gain of the difference amplifier per Equation 18. The resistor R32 and capacitor C15 form a
charge bucket filter for the ADC. The difference amplifier uses the DC offset (VREF1/2) to match the
bidirectional signal from the resolver with the single-ended ADC input.
R28 10k
A 0.196 when R28 R35 and R29 R33
R29 51k (18)
The signal from the resolver secondary winding is floating. Resistors R26, R31, and R36 provide the
appropriate DC biasing. Keeping the inputs of the op amps within the specified common mode range is
important. C12 is an optional filtering capacitor (do not assemble). The 0-Ω resistors R30, R34 must be
populated when the analog crossbar circuitry is not in use.
Two inexpensive voltage references U2, U4 create a 1.24 V and 2.48 V for the ADC. Resistor R27
provides biasing and capacitors C13, C14 provide basic filtering.
NOTE: Always check the stability boundary conditions and minimal bias current for the x431 series
of shunt references. The criteria is subject to change between manufacturers.
Texas Instruments recommends the use of integrated difference amplifiers such as the INA1650-Q1 as a
potential performance upgrade. An integrated multichannel solution provides better channel matching and
precise gain setting without the requirement of expensive precision resistors.
2.3.7 A/D Conversion and Signal Processing

The system uses the undersampling method for demodulating the signals from the resolver sensor. This
technique is one of the simplest, yet very effective. An example of another method is to use a digital
envelope detector and various digital filters. Such a solution is also effective, especially in a noisy
environment; however, every filter causes phase lag and a delay in the system, which is often undesirable
in high-performance feedback control loops.
Figure 14 shows the typical waveforms of a resolver spinning at angular speed as per Equation 19.
2uS
Z
TVELOCITY (19)
TEXC
VR (excitation)
,SAMPLE
VC (COSINE)
TSAMPL = TEXC 90°

VS (SINE)
TVELOCITY
Figure 14. Typical Resolver Waveforms
The physical placement of the secondary windings defines the phase shift between the sine and cosine
signal, which is ideally 90°.
Sampling VS and VC with period TSAMPL = TEXC demodulates the signal and preserves only the signal
envelope that is required for angle calculation, as per the previous Equation 16. The ADC converter is set
in such a way that it always samples the signal when the amplitude reaches the maximum. This setting
increases the signal-to-noise ratio and delivers the best results. The ADC sampling time derives from the
ExcAngle parameter described in Section 2.3.1. For this reason, the code uses the name SamplAngle.
Ideally, the sampling time SamplAngle occurs when ExcAngle is 0.25, 0.75, or both. However, two
sources of phase lag exist for which the system must compensate. The first source of phase lag is on the
active low-pass filter and the excitation amplifier. Resolver impedance, which varies with every model,
defines the second source of phase lag. A diagnostic routine, which sweeps the SamplAngle variable
during the start-up and picks the time point when either VC or VS is highest, makes the system compatible
with various resolvers with different impedance. The ADC samples both resolver signals ideally at the
same time. The MCU offers two independent sample-and-hold circuits which enable this simultaneous
sampling. For this reason, VC and VS connect to ADCINA0 and ADCINB0, respectively.
Scattered Signal Processing Method www.ti.com
3 Scattered Signal Processing Method

A typical resolver system uses a difference amplifier, which interfaces with the ADC for each output (VS,
VC), as Figure 15 shows.
VOUT(A) = G(A) · VIN(A) + VOFFSET(A)
§V ·
VC T arctg ¨¨ S ¸¸
ADC1 A © VC ¹
E
V
VOUT(B) = G(B) · VIN(B) + VOFFSET(B)
VS
ADC2 B
Figure 15. Typical Resolver-to-Digital Signal Chain
Matching the transfer function of the difference amplifiers is critical for system accuracy. Any difference
between the gain or DC offset creates a non-linear error in angle measurement, as per Equation 20.
§V · § G B u VS VOFFSET B ·
4 arctg ¨ S ¸ arctg ¨ ¸
© VC ¹ ¨G u VC VOFFSET A ¸
© A ¹ (20)
The blue trace in Figure 16 shows how a 1% gain imbalance between the amplifiers contributes to the
angle error. The red trace shows the effect of the DC offset on the angle error when VOFFSET(A) = 0.05 ×
VS(MAX).
0.5
0.4
0.3
0.2
Angle Error (q)
0.1
-0.1
-0.2
-0.3
-0.4 GAIN Error

OFFSET Error
-0.5
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360
Resolver Angle (q) D001
Figure 16. Effect of DC Offset and Gain Imbalance on Angle Error
Higher accuracy systems require precision components for the difference amplifiers and system
calibration, which increases system and manufacturing costs. This consideration is valid for discrete as
well as integrated circuits.
The reference design implements a novel method called scattered signal processing. The method uses
the analog crossbar described in Section 2.3.5 and a modified algorithm in the firmware.
www.ti.com Scattered Signal Processing Method
The scattered signal processing method adds an inexpensive analog multiplexer with an inhibit function
(for example, the CD4053) between each resolver output and difference amplifier. This analog multiplexer
allows disconnecting the resolver outputs or swapping them between the difference amplifiers on-the-fly
when the system is running. Swapping resolver outputs scatters the signal between two signal paths,
which is the key action of this concept.
The system operates in the following three steps, which repeat periodically:
1. DC offset calibration with disconnected resolver sensor
2. Sampling the output of both differential amplifiers with the normally-connected resolver outputs VS, VC
(direct mode)
3. Sampling the output of both differential amplifiers with swapped resolver outputs VS, VC (inversed
mode)
Figure 17 shows the first step, which is DC offset calibration. The resolver sensor is completely
disconnected and the output of each difference amplifier corresponds to the DC offset VOFFSET(A,B).
§V ·
© VC ¹
ADC1 A
C
EX
V
CTRL
VS
ADC2 B
CTRL
Figure 17. Scattered Signal Processing Method—Step 1:DC Offset Calibration
In the next step, the ADC samples the output of both differential amplifiers in direct mode (see Figure 18).
§V ·
© VC ¹
ADC1 A
C
EX
V
CTRL
VS
ADC2 B
CTRL
Figure 18. Scattered Signal Processing Method—Step 2: Direct Mode
Scattered Signal Processing Method www.ti.com
In the last step, the ADC samples the output of both differential amplifiers in inversed mode (see
Figure 19).
§V ·
© VC ¹
ADC1 A
C
EX
V
CTRL
VS
ADC2 B
CTRL
Figure 19. Scattered Signal Processing Method—Step 3: Inversed Mode
Table 2 lists the values that the ADC reads during all three steps.
Table 2. ADC Samples Taken During Steps 1 Through 3

ADC INPUT STEP 1 STEP 2 STEP 3
ADC1 VOFFSET(A) G(A) × VC + VOFFSET(A) G(A) × VS + VOFFSET(A)
ADC2 VOFFSET(B) G(B) × VS + VOFFSET(B) G(B) × VC + VOFFSET(B)
The angle calculation algorithm uses all three results for gain imbalance and DC offset elimination. First,
the algorithm adds the results from step 2 and step 3, as per Equation 21.
§V · § G B u VS VOFFSET B G A u VS VOFFSET A ·
© VC ¹ ¨ G u VC VOFFSET G B u VC VOFFSET B ¸
© A A ¹ (21)
The system obtains the DC offset information for both channels from step 1 and compensates it. This
compensation results in the simplified formula as per Equation 22.
§V · § G B u VS G A u VS ·
© VC ¹ ¨ G A u VC G B u VC ¸
© ¹ (22)
Mathematical manipulation eliminates the gain variables from the formula as per Equation 23.
§V u G G ·
§V · ¨ S B A ¸ §V ·
4 arctg ¨ S ¸ arctg ¨ ¸o4 arctg ¨ S ¸
© VC ¹ ¨ VC u G A GB ¸ © VC ¹
© ¹ (23)
At this point note that the gain imbalance and DC offset no longer contribute to the error calculation. Also
note that the method compensates for any imperfections in the ADC transfer function (gain or offest).
NOTE:
• Embedded algorithms typically use Atan2 function which is defined at ±π radians.
• The scattered-signal processing method is effective for signals with a significantly lower
bandwidth than the ADC sampling and algorithm execution frequency.
• The current firmware implementation only performs step 1 during the system start-up.
www.ti.com Scattered Signal Processing Method
The scattered-signal processing technique has additional positive side effects. The system allows for "limp
mode" operation due to the redundant signal path and allows for additional diagnostics, the process for
which is as follows:
1. The hardware engineer calculates the worst-case tolerances for the DC offset and gain imbalance and
parametrizes the system (for example, a 1.5% tolerance span).
2. The algorithm then periodically checks if readout data are within the given tolerance boundaries,
typically for:
• DC offset for both channels
• Maximum acceptable difference between ADC samples taken in step 2 and step 3
• VS and VC amplitude
3. If one of the diagnostic results fails, the system is able to detect the defective channel and eventually
work in the "limp mode" with reduced performance, using only one analog front-end channel. This
measureis important and beneficial in robust systems and in safety-critical applications (SIL/ASIL).
Hardware, Software, Testing Requirements, and Test Results www.ti.com
4 Hardware, Software, Testing Requirements, and Test Results
4.1 Required Hardware and Software
4.1.1 Hardware
The following hardware is necessary for exploring the TIDA-01507 reference design:
• The TIDA-01527 discrete resolver front-end board
• The LAUNCHXL-F28069M LaunchPad development board (or similar)
• The adapter board or a custom ribbon cable for interfacing the TIDA-01527 with the LaunchPad
• A resolver sensor matching the system specification
• Laboratory power supply specified at 0 V to 15 V, 0 mA to 200 mA, preferably with current limitation or
overcurrent protection
• A computer capable of running Code Composer Studio™ (CCS) software
Figure 20 shows the reference design pinout and Table 3 lists the connections to the LaunchPad and the
pin mapping. To access the quick start guide for the LAUNCHXL-F28069M including a pins overview, see
TMS320F28069M LaunchPad Development Kit Quick Start Guide.
14:GND 13:CTRL
12:GND 11:OEXC EXC-
EXC+
10:GND 9:OCOS
COS-
8:VREF1/2 7:INH
COS+
6:GND 5:OSIN
SIN-
4:VREF 3:VCC SIN+
2:GND 1:PWM
Figure 20. TIDA-01527 Pinout
Figure 21 shows a properly-assembled TIDA-01527 reference design with the LaunchPad adapter and
LAUNCHXL-F28069M development board.
Figure 21. LAUNCHXL-F28069M Development Board With TIDA-01527 and LaunchPad™ Adapter
www.ti.com Hardware, Software, Testing Requirements, and Test Results
Table 3. TMS320F28069M Pin Mapping for TIDA-15027 Reference Design

SIGNAL DESCRIPTION TMS320F28069M (LAUNCHXL PIN)
PWM Sine-modulated PWM EPWM1A (J4 pin 40)
GND Common ground GND (J2 pin 20, J3 pin 22)
VCC Power supply 12 V to 15 V Provided externally
OSIN Sinus difference amplifier output ADCINA0 (J3 pin 27)
INH Analog crossbar inhibit GPIO02 (J4 pin 38)
OCOS Cosinus difference amplifier output ADCINB0 (J3 pin 28)
OEXC Excitation amplifier monitoring output ADCINA1 (J3 pin 29)
CTRL Analog crossbar control GPIO01 (J4 pin 39)
VREF1/2 Voltage reference 1.24 V (Optional) ADCINB2 (J3 pin 26)
VREF Voltage reference 2.48 V (Optional) ADCINA2 (J3 pin 25)
4.1.2 Software
This reference design comes with a complete example software package with a precompiled binary file
and source codes. The following software tools were used during development with the LAUNCHXL-
F28069M development board.
1. Code Composer Studio v7 with C2000 compiler TI v16.9.1 LTS
2. controlSUITE™ software (optional) – Provides extensive database of schematics, libraries, code
examples, and manuals for C2000-based solutions
3. C2000Ware (optional) – A lightweight version of the controlSUITE package
Texas Instruments also offers a set of free-of-charge online development tools at dev.ti.com that can be
used for programming the MCU or code modifications.
NOTE: For detailed tutorials on how to program, compile, and debug using TI's MCUS, see
processors.wiki.ti.com. Alternatively, TI also offers live support within the E2E™ online
community.
4.1.3 Quick-Start With TIDA-01527

Software:
1. Install the CCS software and import the TIDA-01527 project files using the File→ Import menu and
then select the CCS Project.
2. Connect the C2000 LaunchPad to the PC and make sure that the device drivers have been properly
installed.
3. Compile the TIDA-01527 code. The compilation process proceeds with no errors or warnings.
4. Run the code using the Run→ Debug menu, then click the Resume button. The binary code loads to
the MCU. The code then executes, even without the TIDA-01527 connected.
5. Add system variables to the Expressions window and activate an automatic refresh. This action
enables real-time monitoring and allows for modifications to system variables.
Hardware:
1. Connect the TIDA-01527 board to the LaunchPad using either a flat ribbon cable or the provided
adapter board.
2. Connect a resolver to the TIDA-01527 board.
3. Set the laboratory power supply to 14 V with the current limitation set to 100 mA and power the TIDA-
01527 board.
4. The light-emitting diode (LED) on the TIDA-01527 board illuminates.
5. Run the software from CCS. Check the resolver waveforms and compare them with the results from
Test Results.
4.2 Testing and Results
4.2.1 Test Setup

Figure 22 shows the test setup used during the TIDA-01527 reference design development. The test
bench uses the following:
• Keithley 2230-30-1 multiple-output laboratory power supply
• R&S®RTB2004 (Rohde & Schwarz) or Tektronix TDS5054B oscilloscope
• TIDA-00176 reference design with ROD480-1024 Sin/Cos encoder as the reference encoder
• TIDA-01527 reference design (test subject) with LTN58 (R58CURE151B04-021-07AX) resolver
Figure 22. TIDA-01527 Test Setup Used for Development and Measurements
4.2.2 Test Results
D0 – Input PWM from the C2000 MCU; D1, D2 – Control (CTRL) and Inhibit (INH) signals for the analog crossbar;
CH1, CH2 – Generated sine wave after the analog phase-splitter (EXC_N, EXC_P); CH3, Ch4 – Excitation amplifier
outputs (EXC+, EXC–)
Figure 23. Active Low-Pass Filter and Excitation Amplifier Waveforms
D0 – Input PWM from the C2000 MCU; D1, D2 – Control (CTRL) and Inhibit (INH) signals for the analog crossbar;
CH1 – Exciter voltage monitoring (OEXC), CH2 – Sine-winding voltage monitoring (OSIN), CH3 – Cosine winding
voltage monitoring (OCOS)
Figure 24. Analog Front-End Waveforms (Steady Operation)
CH1 – Exciter voltage monitoring (OEXC); CH2 – Sine-winding voltage monitoring (OSIN); CH3 – Cosine-winding
Figure 25. Analog Front-End Waveforms (Resolver Spins at ≈ 2625 RPM)
CH1 – Exciter voltage monitoring (OEXC); CH2 – Sine-winding voltage monitoring (OSIN); CH3 – Cosine-winding
Figure 26. Analog Front-End Waveforms (Resolver Spins at ≈ 2625 RPM With Detail)
D0 – Input PWM from the C2000 MCU; D1, D2 - Control (CTRL) and Inhibit (INH) signals for the analog crossbar;
CH1 – Exciter voltage monitoring (OEXC), CH2 – Sine-winding voltage monitoring (OSIN); CH3 – Cosine-winding
voltage monitoring (OCOS).
Note that the provided example performs offset calibration (step 1) during the start-up and then alternates only to step
2 and step 3.
Figure 27. Analog Front-End Waveforms With Scattered Signal Processing Enabled
Figure 28 shows the result of the diagnostic routine described in Section 2.3.7, which finds the right
sampling time for the envelope detector. The rising edge on the debug pin GPIO3 represents the OSIN
and OCOS sampling, and the falling edge represents the sampling of the OEXC signal.
Figure 28. Sampling Times for OSIN, OCOS, and OEXC Signals
Figure 29 shows the accuracy plot. Figure 30 and Figure 31 show the same data in a different format.
0.5
TIDA-01527 (Normal Mode)
0.4 TIDA-01527 (Scattered Mode)
PGA411-Q1 (TIDA-00796)
12-b Resolution (MAX)
0.3 12-b Resolution (MIN)
0.2 Scattered Mode

± 0.1°
Angle Error (°)
0.1
0 ± 0.044°
-0.1 Theoretical
minimum error
Normal Mode for 12-b resolution
-0.2 ± 0.24°
PGA411-Q1
± 0.30°
-0.3
-0.4
-0.5
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360
Resolver Angle (°) D002
Figure 29. TIDA-01527 Accuracy Plot
90 90
135 45 135 45
180 0 180 0
0.2 0.4 0.6 -0.2 0 0.2
TIDA-01527 (Normal Mode)

225
TIDA-01527 (Scattered Mode) 315 225
TIDA-01527 (Normal Mode) 315
PGA411-Q1 (TIDA-00796) TIDA-01527 (Scattered Mode)
PGA411-Q1 (TIDA-00796)
270 270
D021 D020
Figure 30. TIDA-01527 Unity Circle Accuracy Plot Figure 31. TIDA-01527 Unity Circle Accuracy Plot
(Absolute to Zero)
As mentioned in Section 2.3.1, the system uses the IQ math library in the angle calculation routine. The
plot in Figure 32 shows the calculation error due to the finite Q-number resolution. The reference data use
RAW results from the ADC with post processing (calculation) in the PC using Microsoft® Excel. The error
is negligible and significantly below the system resolution.
0.03
0.02
0.01
Angle Error (q)
-0.01
-0.02
-0.03
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360
Resolver Angle (q) D003
Figure 32. Effect of Fixed Point IQ-Math Library on Error
Figure 33 shows a photo from the thermal imaging camera when the TIDA-01527 reference design drives
the LTN58 resolver at 5 kHz with a 7-VRMS excitation at a 22°C ambient temperature. Not many options
are available for reducing the dissipation of an AB-class amplifier other than lowering voltage drop across
and current through the power stage.
Figure 33. TIDA-01527 Thermal Imaging Camera Picture
www.ti.com Design Files
5 Design Files
5.1 Schematics
To download the schematics, see the design files at TIDA-01527.
5.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-01527.
5.3 PCB Layout Recommendations

The design does not require any special PCB layout considerations. The TIDA-01527 uses a four-layer
PCB with double-side component placement. The top side (Figure 34) primarily carries circuitry for the
excitation amplifier and voltage references. Signal conditioning amplifiers for the resolver secondary
windings and the system connector are located on the bottom side (Figure 35). The other two internal
layers (Figure 36 and Figure 37) carry the power, ground, and signals, too.
Figure 34. Top PCB Side and Components Placement Figure 35. Bottom PCB Side and Components
Placement
Figure 36. Internal Layer 1 With Common Ground GND Figure 37. Internal Layer 2 With Power Rail VCC and
and Signals Signals
Design Files www.ti.com
5.3.1 Layout Prints

To download the layer plots, see the design files at TIDA-01527.
5.4 Altium Project

To download the Altium project files, see the design files at TIDA-01527.
5.5 Gerber Files

To download the Gerber files, see the design files at TIDA-01527.
5.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-01527.
6 Software Files
To download the software files, see the design files at TIDA-01527.
7 Related Documentation
1. Texas Instruments, TLVx171-Q1 36-V, Single-Supply, General-Purpose Operational Amplifier for Cost-
Sensitive Automotive Systems Data Sheet
2. Texas Instruments, TLV431x-Q1 Low-Voltage Adjustable Precision Shunt Regulator Data Sheet
3. Texas Instruments, TMS320F2806x Piccolo™ Microcontrollers Data Manual
4. Texas Instruments, Automotive Resolver-to-Digital Converter for Safety Applications Design Guide
5. Texas Instruments, EMC Compliant Single-Chip Resolver-to-Digital Converter (RDC) Reference
Design
6. Texas Instruments, Reduce system costs with resolver-to-digital conversion implementation on
C2000™ microcontrollers (white paper)
7. Texas Instruments, TMS320F240 DSP Solution for Obtaining Resolver Angular Position and Speed
Application Note
8. Texas Instruments, C28x IQmath Library Module User's Guide
9. (2004) Synchro and Resolver Engineering Handbook . Moog Components Group. Retrieved from
http://www.moog.com/literature/MCG/synchrohbook.pdf
7.1 Trademarks
C2000, LaunchPad, Piccolo, Code Composer Studio, controlSUITE, E2E are trademarks of Texas
Instruments.
Microsoft is a registered trademark of Microsoft Corporation.
R&S is a registered trademark of Rohde & Schwarz USA, Inc..
All other trademarks are the property of their respective owners.
8 Glossary
ADC— Analog-to-digital converter
CCS— Code Composer Studio™
CLA— Control law accelerator
ESD— Electrostatic discharge
EV— Electric vehicle
HEV— Hybrid-electric vehicle
HRPWM— High-resolution pulse width modulator
www.ti.com About the Author
LED— Light-emitting diode

MCU— Microcontroller
Op Amp— Operational amplifier
PCB— Printed-circuit board
PWM— Pulse-width modulation
RMS— Root mean square
9 About the Author

JIRI PANACEK is a systems engineer in the Powertrain Automotive Systems team at Texas Instruments
where he develops reference designs. Jiri has five years of field experience in the industrial automation
and most recently the EV/HEV automotive segment. Jiri earned his master's degree in microelectronics
from the Brno University of Technology in the Czech Republic.
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TI Designs: TIDA-01527

Discrete Resolver Front-End Reference Design With

TIDA-01527 Design Folder

ASK Our E2E Experts

C2000Œ /DXQFK3DGŒ RESOLVER SENSOR

Copyright © 2018, Texas Instruments Incorporated

1.1 Key System Specifications

Table 1. Key System Specifications

Figure 1. TIDA-01527 Board (Top and Bottom)

2.1 Block Diagram

C2000Œ /DXQFK3DGŒ RESOLVER SENSOR

Copyright © 2018, Texas Instruments Incorporated

Figure 2. TIDA-01527 Block Diagram

2.2 Highlighted Products

2.2.3 C2000™ TMS320F28069M MCU

2.3 System Design Theory

2.3.1 PWM Generation

Note: X-axis is not in scale

Figure 3. PWM Generation From MCU

2.3.2 Active Low-Pass Second-Order Filter and Phase Splitter

PWM carrier and harmonics

Note: X-axis is not in scale

Figure 4. Magnitude Spectrum of Generated PWM Signal

PASS BAND TRANSITION BAND STOP BAND

Note: X-axis is not in scale

Figure 5. Suggested Low-Pass Filter Response for PWM Signal Filtering

GND Copyright © 2018, Texas Instruments Incorporated

Figure 6. Multiple-Feedback Filter (MFB) in TIDA-01527

2.3.3 Power (Excitation) Amplifiers

GND Copyright © 2018, Texas Instruments Incorporated

Figure 7. TIDA-01527 Excitation Amplifier—Single Channel

2.3.4 Resolver Sensor

Figure 9. Resolver as Rotating Transformer

Lower and Uper Sideband

Figure 10. Magnitude Spectrum of Resolver Sensor Output Signal

Figure 11. Analog Crossbar (Experimental)

2.3.6 Analog Front-End Difference Amplifiers

R19 R20 EXC-

Figure 12. Excitation Amplifier Output Monitoring

Figure 13. Resolver Feedback Winding Monitoring

2.3.7 A/D Conversion and Signal Processing

TSAMPL = TEXC 90°

Figure 14. Typical Resolver Waveforms

3 Scattered Signal Processing Method

Figure 15. Typical Resolver-to-Digital Signal Chain

-0.4 GAIN Error

Figure 16. Effect of DC Offset and Gain Imbalance on Angle Error

VOUT(B) = G(B) · VIN(B) + VOFFSET(B)

Figure 17. Scattered Signal Processing Method—Step 1:DC Offset Calibration

VOUT(B) = G(B) · VIN(B) + VOFFSET(B)

Figure 18. Scattered Signal Processing Method—Step 2: Direct Mode

VOUT(B) = G(B) · VIN(B) + VOFFSET(B)

Figure 19. Scattered Signal Processing Method—Step 3: Inversed Mode

Table 2. ADC Samples Taken During Steps 1 Through 3

4 Hardware, Software, Testing Requirements, and Test Results

4.1 Required Hardware and Software

12:GND 11:OEXC EXC-

4:VREF 3:VCC SIN+

Figure 20. TIDA-01527 Pinout