BUFFER.

V BUFFER_TEST
`resetall `resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
`view vlog `view vlog

//Define our own Inverter, // Testbench for Buffer Module

module inverter module buf_test;

(
Y, wire out ;
A reg in ;
);
`uselib view = vlog
// Declarations of I/O ,Power and
Ground Lines // Instantiate Buffer Module

output Y; buffer b1
input A; (
supply1 pwr; out,
supply0 gnd; in
);
// Instantiate pmos and nmos
switches `nouselib

pmos (Y,pwr,A); // Display

nmos (Y,gnd,A);
task display ;
endmodule begin
$display
// Define our own Buffer (
"time=%0d" , $time , " ns"
module buffer , " Input=" , in
( , " Output=", out
out, );
in end
); endtask

// Declarations of I/O Lines // Apply Stimulus

output out; initial

input in; begin
in = 1'b0 ; #10 ; display ;
// Wire Declaration in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
wire a; in = 1'bz ; #10 ; display ;
end
// Instantiate Inverter module
endmodule
inverter i1 (a,in);
inverter i2 (out,a); `noview

endmodule

`noview

TG.V TG_TEST.V
`resetall `resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
`view vlog `view vlog
// Testbench for Inverter Module
//Define our own Transmission module trangate_test;
Gate, wire out ;
reg in ;
module trangate reg cntrl1,cntrl2;
(
out , `uselib view = vlog
in ,
cntrl1, // Instantiate trangate Module
cntrl2 trangate t1
); ( out, in, cntrl1,cntrl2 ) ;

// Declarations of I/O and Control `nouselib

Lines
// Display
output out;
input in; task display ;
input cntrl1,cntrl2; begin
$display
// Instantiate pmos and nmos (
switches "time=%0d" , $time , " ns"
, " Input=" , in
pmos (out,in,cntrl1); , " Output=", out
nmos (out,in,cntrl2); , " Control1=",cntrl1
, " Control2=",cntrl2
endmodule );
end
`noview endtask

// Apply Stimulus

initial
begin
in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2
= 1'b1 ; #10 ; display ;
in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2
= 1'b0 ; #10 ; display ;
in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2
= 1'b1 ; #10 ; display ;
in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2
= 1'b0 ; #10 ; display ;
end

endmodule

`noview

INVERTER_TEST.V
`resetall
INVERTER.V `timescale 1 ns / 1 ns
`resetall `view vlog
`timescale 1 ns / 1 ns
`view vlog // Testbench for Inverter Module
 module inv_test;
//Define our own Inverter, wire out ;
reg in ;
module inverter
( `uselib view = vlog
out ,
in // Instantiate inverter Module
);
inverter i1
// Declarations of I/O ,Power and (
Ground Lines out,
in
output out; );
input in;
supply1 pwr; `nouselib
supply0 gnd;
// Display
// Instantiate pmos and nmos
switches task display ;
begin
pmos (out,pwr,in); $display
nmos (out,gnd,in); (
"time=%0d" , $time , " ns"
endmodule , " Input=" , in
, " Output=", out
`noview );
end
endtask

// Apply Stimulus

initial
begin
in = 1'b0 ; #10 ; display ;
in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
in = 1'bz ; #10 ; display ;
end

endmodule

`noview
D_FF.V T_FF.V
module d_ff(q,clk,n_rst,din); module t_ff(q,qbar,clk,tin,rst);
output q; output q,qbar;
input clk,din,n_rst; input clk,tin,rst;
reg q; reg tq;
always @(posedge clk or
always @(posedge clk or negedge negedge rst)
n_rst) begin
begin if(!rst)
if(!n_rst) tq <= 1'b0;
q <= 1'b0; else
else begin
q <= din; if (tin)
end tq <= ~tq;
endmodule end
module d_ff_test; end
assign q = tq;
reg clk, din, n_rst; assign qbar = ~q;
wire q, d1, clk1; endmodule
d_ff df1 (q, clk, n_rst, din);
module t_ff_test;
assign d1=din; reg clk,tin,rst;
assign clk1=clk; wire q,qbar;
initial t_ff t1(q,qbar,clk,tin,rst);
clk = 1'b0; initial
clk = 1'b0;
always always
 #10 clk = ~clk; #10 clk = ~clk;
initial
initial begin
begin rst = 1'b0; tin = 1'b0;
din = 1'b0; #30 rst = 1'b1;
n_rst = 1'b1; #10 tin = 1'b1;
#20 n_rst = 1'b0; #205 tin = 1'b0;
#10 din = 1'b1; #300 tin = 1'b1;
#20 n_rst = 1'b1; #175 tin = 1'b0;
#18 din = 1'b0; #280 rst = 1'b0;
#1 din = 1'b1; #20 rst = 1'b1;
#20 din = 1'b0; #280 tin = 1'b1;
#10 ; #10 ;
end end
initial
always #2000 $finish;
#5 $display ($time," clk=%b din= endmodule
%b q=%b", clk, din, q);
initial
#100 $finish;
specify
$setup(d1, posedge
clk1, 2);
$hold(posedge clk1,
d1, 2);
$width(negedge d1, 2);
endspecify
endmodule

JK_FF.V #50 rst = 1'b0;

module jk_ff(q,qbar,clk,rst,j,k); #10 ;
end
input clk,rst,j,k;
output q,qbar; always
reg q,tq; #5 $display($time,"
clk=%b j=%b k=%b ",clk,j,k);
always @(posedge clk or negedge
rst) initial
begin #300 $finish;
 if (!rst) specify
begin $setup(j1, posedge
q <= 1'b0; clk1, 2);
tq <= 1'b0; $setup(k1, posedge
end clk1, 2);
else $hold(posedge clk1, j1,
begin 2);
if (j == 1'b1 && k == $hold(posedge clk1,
1'b0) k1, 2);
q <= j; endspecify
else if (j == 1'b0 && k == endmodule
1'b1)
q <= 1'b0;
else if (j == 1'b1 && k
== 1'b1)
begin
tq <= ~tq;
q <= tq;
end
end
end
assign q_bar = ~q;
endmodule

module jk_ff_test;
reg clk,rst,j,k;
wire q,qbar;

wire clk1,j1,k1;

jk_ff inst(q,qbar,clk,rst,j,k);

assign clk1=clk;
assign j1=j;
assign k1=k;

initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
j = 1'b0; k = 1'b0; rst =
1'b0;
 #30 rst = 1'b1;
#60 j = 1'b0; k = 1'b1;
#29 j = 1'b1; k = 1'b0;
#1 j = 1'b0; k = 1'b1;
#20 j = 1'b1; k = 1'b1;
#40 j = 1'b1; k = 1'b0;

#5 j = 1'b0; #20 j = 1'b1;

MS_FF.V initial
module ms_jkff(q,q_bar,clk,j,k); #200 $finish;
output q,q_bar; specify
input clk,j,k; $setup(j2, posedge clk2,
reg tq,q,q_bar; 2);
$setup(k2, posedge clk2,
always @(clk) 2);
begin $hold(posedge clk2, j2,
if (!clk) 2);
begin $hold(posedge clk2, k2,
if (j==1'b0 && 2);
k==1'b1) endspecify
tq <= 1'b0;
else if (j==1'b1 && endmodule
k==1'b0)
tq <= 1'b1;
else if (j==1'b1 &&
k==1'b1)
tq <= ~tq;
end
if (clk)
begin
q <= tq;
q_bar <= ~tq;
end
end
endmodule

module tb_ms_jkff;
reg clk,j,k;
wire q,q_bar;
 wire clk2,j2,k2;

ms_jkff inst(q,q_bar,clk,j,k);

assign clk2=clk;
assign j2=j;
assign k2=k;

initial
clk = 1'b0;

always #10
clk = ~clk;

initial
begin
j = 1'b0; k = 1'b0;
#60 j = 1'b0; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#20 j = 1'b1; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#5 j = 1'b0; #20 j = 1'b1;
#10 ;
end
always
#5 $display($time," clk=%b j=
%b k=%b
",clk,j,k);

SR_FF.V initial
module SR_ff(q,qbar,s,r,clk); #500 $finish;
output q,qbar; specify
input clk,s,r; $setup(s1, posedge
reg tq; clk1, 2);
$setup(r1, posedge
always @(posedge clk or tq) clk1, 2);
begin $hold(posedge clk1, s1,
if (s == 1'b0 && r == 1'b0) 2);
tq <= tq; $hold(posedge clk1, r1,
else if (s == 1'b0 && r == 2);
1'b1) endspecify
tq <= 1'b0; endmodule
 else if (s == 1'b1 && r ==
1'b0)
tq <= 1'b1;
else if (s == 1'b1 && r ==
1'b1)
tq <= 1'bx;
end
assign q = tq;
assign qbar = ~tq;
endmodule

module SR_ff_test;
reg clk,s,r;
wire q,qbar;

wire s1,r1,clk1;

SR_ff sr1(q,qbar,s,r,clk);

assign s1=s;
assign r1=r;
assign clk1=clk;

initial
clk = 1'b0;

always
#10 clk = ~clk;
initial
begin
s = 1'b0; r = 1'b0;
#30 s = 1'b1;
#29 s = 1'b0;
#1 r = 1'b1;
#30 s = 1'b1;
#30 r = 1'b0;
#20 s = 1'b0;
#19 s = 1'b1;
#200 s = 1'b1; r = 1'b1;
#50 s = 1'b0; r = 1'b0;
#50 s = 1'b1; r = 1'b0;
#10 ;
end
always
 #5 $display($time,"
clk=%b s=%b r=%b ",clk,s,r);

AND.V AND_TEST.V
`resetall `resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
`view vlog `view vlog

//Define our own And Gate, // Testbench for And Module

module andgate module and_test;

(
out , wire out ;
in1 , reg in1,in2 ;
in2
); `uselib view = vlog

// Declarations of I/O ,Power and // Instantiate And Gate Module

Ground Lines
andgate a1
output out; (
input in1,in2; out,
supply1 pwr; in1,
supply0 gnd; in2
);
// Declaration of Wires
`nouselib
wire contact;
wire nout; // Display

// Instantiate pmos and nmos task display ;

switches to form Nand gate begin
$display
pmos (nout,pwr,in1); (
pmos (nout,pwr,in2); "time=%0d" , $time , " ns"
nmos (nout,contact,in1); , " Input1=" , in1
nmos (contact,gnd,in2); , " Input2=" , in2
, " Output=" , out
// Instantiate pmos and nmos );
switches to form Inv end
endtask
pmos (out,pwr,nout);
nmos (out,gnd,nout); // Apply Stimulus

endmodule initial
begin
`noview in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview

NAND.V NAND_TEST.V
`resetall
`resetall `timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns `view vlog
`view vlog
// Testbench for Nand Gate
//Define our own Nand Gate, Module

module nandgate module nand_test;

(
out , wire out ;
in1 , reg in1,in2 ;
in2
); `uselib view = vlog

// Declarations of I/O ,Power and // Instantiate Nand Gate Module

Ground Lines
nandgate n1
output out; (
input in1,in2; out,
supply1 pwr; in1,
supply0 gnd; in2
);
// Declaration of Wire
`nouselib
wire contact;
// Display
// Instantiate pmos and nmos
switches task display ;
begin
pmos (out,pwr,in1); $display
pmos (out,pwr,in2); (
nmos (out,contact,in1); "time=%0d" , $time , " ns"
nmos (contact,gnd,in2); , " Input1=" , in1
, " Input2=" , in2
endmodule , " Output=" , out
);
`noview end
endtask

// Apply Stimulus

initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview
 NOR_TEST.V
NOR.V `resetall
`resetall `timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns `view vlog
`view vlog
// Testbench for Nor Gate Module
//Define our own Nor Gate,
module nor_test;
module norgate
( wire out ;
out , reg in1,in2 ;
in1 ,
in2 `uselib view = vlog
);
// Instantiate Nor Gate Module
// Declarations of I/O ,Power and
Ground Lines norgate n1
(
output out; out,
input in1,in2; in1,
supply1 pwr; in2
supply0 gnd; );

// Declaration of Wire `nouselib

wire contact; // Display

// Instantiate pmos and nmos task display ;

switches begin
$display
pmos (contact,pwr,in1); (
pmos (out,contact,in2); "time=%0d" , $time , " ns"
nmos (out,gnd,in1); , " Input1=" , in1
nmos (out,gnd,in2); , " Input2=" , in2
, " Output=" , out
endmodule );
end
`noview endtask

// Apply Stimulus
 initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview

OR.V OR_TEST.V
`resetall
`resetall `timescale 1 ns / 1 ns
`timescale 1 ns / 1 ns `view vlog
`view vlog
// Testbench for Nor Gate Module
//Define our own Or Gate,
module or_test;
module orgate
( wire out ;
out , reg in1,in2 ;
in1 ,
in2 `uselib view = vlog
);
// Instantiate Orgate Module
// Declarations of I/O ,Power and
Ground Lines orgate n1
(
output out; out,
input in1,in2; in1,
supply1 pwr; in2
supply0 gnd; );

// Declaration of Wires `nouselib

wire contact; // Display

wire nout;
task display ;
// Instantiate pmos and nmos begin
switches for Nor gate $display
(
pmos (contact,pwr,in1); "time=%0d" , $time , " ns"
pmos (nout,contact,in2); , " Input1=" , in1
nmos (nout,gnd,in1); , " Input2=" , in2
nmos (nout,gnd,in2); , " Output=" , out
);
// Instantiate pmos and nmos end
switches for Not gate endtask

pmos (out,pwr,nout); // Apply Stimulus

nmos (out,gnd,nout);
initial
endmodule begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
`noview display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview
XNOR.V XNOR_test.v
`resetall `resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
`view vlog `view vlog

//Define our own XNOR Gate, // Testbench for Xnor Module

module xnorgate module xnor_test;

(
out , wire out ;
in1 , reg in1,in2 ;
in2
); `uselib view = vlog

// Declarations of I/O ports // Instantiate Xnor gate Module

output out; xnorgate x1

input in1,in2; (
wire in2bar; out,
in1,
assign in2bar = ~in2; in2
);
// Instantiate pmos and nmos
switches : `nouselib

pmos (out,in2bar,in1); // Display

nmos (out,in2,in1);
pmos (out,in1,in2bar); task display ;
nmos (out,in1,in2); begin
$display
endmodule (
"time=%0d" , $time , " ns"
`noview , " Input1=" , in1
, " Input2=" , in2
, " Output=" , out
);
end
endtask

// Apply Stimulus

initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
 display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview

XOR.V XOR_TEST.V
`resetall `resetall
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
`view vlog `view vlog

//Define our own XOR Gate, // Testbench for Xor Module

module xorgate module xor_test;

(
out , wire out ;
in1 , reg in1,in2 ;
in2
); `uselib view = vlog

// Declarations of I/O ports // Instantiate Xorgate Module

output out; xorgate x1

input in1,in2; (
wire in2bar; out,
in1,
assign in2bar = ~in2; in2
);
// Instantiate pmos and nmos
switches : `nouselib

pmos (out,in2,in1); // Display

nmos (out,in2bar,in1);
pmos (out,in1,in2); task display ;
nmos (out,in1,in2bar); begin
$display
endmodule (
"time=%0d" , $time , " ns"
`noview , " Input1=" , in1
, " Input2=" , in2
, " Output=" , out
);
end
endtask

// Apply Stimulus

initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ;
display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ;
display ;
end

endmodule

`noview

ADDER.V ADDER4_T.V
module adder4 module adder4_t ;
( carryin,x,y,sum,carryout);
reg [3:0] x,y;
input carryin; reg carryin;
input [3:0] x,y; wire [3:0] sum;
output [3:0] sum; wire carryout;
output carryout;
adder4 a1
fulladd stage0 ( carryin,x,y,sum,carryout);
(carryin,x[0],y[0],sum[0],c1);
fulladd stage1 initial
(c1,x[1],y[1],sum[1],c2); begin
fulladd stage2 $monitor($time,"SUM=
(c2,x[2],y[2],sum[2],c3); %d",sum);
fulladd stage3 x = 4'b0000; y= 4'b0000;carryin =
(c3,x[3],y[3],sum[3],carryout); 1'b0;
#20 x =4'b1111; y = 4'b1010;
endmodule #40 x =4'b1011; y =4'b0110;
#40 x =4'b1111; y=4'b1111;
FULLADD.V
module fulladd (cin,x,y,s,cout); #50 $finish;
end
input cin,x,y;
output s,cout; endmodule

assign s = x^y^cin;
assign cout =( x & y) | (x & cin) |
( y & cin);

endmodule

mycounter.v mycounter_t.v
module counter_behav module mycounter_t ;
( count,reset,clk); wire [3:0] count;
input wire reset, clk; reg reset,clk;
output reg [3:0] count;
initial
always @(posedge clk) clk = 1'b0;
if (reset) always
count <= 4'b0000; #5 clk = ~clk;
else counter_behav m1 ( count,reset,clk);
count <= count + 4'b0001; initial
begin
endmodule reset = 1'b0 ;
 #15 reset =1'b1;
#30 reset =1'b0;
#300 $finish;
end
initial
$monitor ($time, "Output count = %d
",count );
endmodule

SERIAL_ADDER.V SHIFT_REGISTER.V
module serial_adder ( A,B, reset, module shiftrne ( R,L,E,w,clock,q);
clock, sum);
input [7:0] A,B; parameter n=8;
input reset,clock; input [n-1:0] R;
output [7:0] sum; input L,E,w,clock;
reg [3:0] count; output [n-1:0] q;
reg s,y,Y; reg [n-1:0] q;
wire [7:0] qa,qb,sum; integer k;
wire run;
parameter G=0,H=1; always @(posedge clock)
if (L)
shiftrne shift_A q <= R;
(A,reset,1'b1,1'b0,clock,qa); else if (E)
shiftrne shift_B begin
(B,reset,1'b1,1'b0,clock,qb); for (k=n-1;k>0;k=k-1)
shiftrne shift_sum q[k-1] <= q[k];
(8'b0,reset,run,s,clock,sum); q[n-1] <= w;
end
//adder fsm endmodule
//output and next state
combinational circuit SERIAL_ADDER_t.V
always @(qa or qb or y) module serial_adder_t ;
case (y) reg [7:0] A,B;
G: begin reg reset,clock;
s = qa[0]^qb[0]; wire [7:0] sum ;
if (qa[0] & qb[0])
 Y = H; initial
else clock = 1'b0;
Y = G;
end always
#5 clock =~clock;
H: begin
s = qa[0] ~^qb[0]; serial_adder s1
if (~qa[0] & ~qb[0]) (A,B,reset,clock,sum);
Y =G;
else initial
Y = H; begin
end reset = 1'b0;A = 8'b10101010; B =
8'b11111111;
default : Y = G; #20 reset = 1'b1;
#20 reset = 1'b0;
endcase #150 reset = 1'b1; A =
8'b11110000 ; B = 8'b11110011;
//sequential block #20 reset = 1'b0;
always @(posedge clock)
if (reset) #200 $finish;
y <= G; end
else
y <= Y; initial
$monitor ($time, " SUM = %d ",
//control the shifting process sum);
always @(posedge clock)
if (reset) Endmodule
count = 8;
else if (run) count = count - 1;
assign run=|count;

endmodule

RIPPLE_COUNTER.V RIPPLE_COUNTER_t
`view rtl `noview
module ripple_counter (clock, module ripple_counter_t ;
toggle, reset, count); reg clock,toggle,reset;
input clock, toggle, reset; wire [3:0] count ;
output [3:0] count; ripple_counter r1
 reg [3:0] count; (clock,toggle,reset,count);
wire c0, c1, c2;
assign c0 = count[0], c1 = count[1], initial
c2 = count[2]; clock = 1'b0;

always @ (posedge reset or posedge always

clock) #5 clock = ~clock;
if (reset == 1'b1) count[0] <= initial
1'b0; begin
else if (toggle == 1'b1) count[0] <= reset = 1'b0;toggle = 1'b0;
~count[0]; #10 reset = 1'b1; toggle = 1'b1;
#10 reset = 1'b0;
always @ (posedge reset or #190 reset = 1'b1;
negedge c0) #20 reset = 1'b0;
if (reset == 1'b1) count[1] <= #100 reset = 1'b1;
1'b0; #40 reset = 1'b0;
else if (toggle == 1'b1) count[1] <= #250 $finish;
~count[1];
end
always @ (posedge reset or
negedge c1)
if (reset == 1'b1) count[2] <=
1'b0;
else if (toggle == 1'b1) count[2] <=
~count[2];

always @ (posedge reset or

negedge c2)
if (reset == 1'b1) count[3] <=
1'b0;
else if (toggle == 1'b1) count[3] <=
~count[3];
endmodule

SAR.V SAR_T.V
module shiftrne module sar_t;
( R,L,E,w,clock,q);
reg [7:0] r;
parameter n=8; reg l;
input [n-1:0] R; reg e;
input L,E,w,clock; reg w;
output [n-1:0] q; reg clk;
reg [n-1:0] q; wire [7:0] q;
integer k; shiftrne
sf(.R(r),.L(l),.E(e),.w(w),.clock(clk),
always @(posedge clock) .q(q));
if (L) initial
q <= R; begin
else if (E) clk = 1'b0;
begin l = 1'b1;
for (k=n-1;k>0;k=k-1) w = 1'b0;
q[k-1] <= q[k]; e = 1'b0;
q[n-1] <= w; #5 r = 8'b1111_0000;
end #10 l = 1'b0;
e = 1'b1;
endmodule w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b1;
#10 w = 1'b1;
#10 w = 1'b1;
#10 w = 1'b1;
#10 $finish;
end
always #5 clk = ~clk;
endmodule