List of Figures
List of Figures
List of Figures
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Figure No. Name of the Figure Page No
7.9 Workspace Sim Tab Displays Design Hierarchy 64
7.10 Object Plane Displays Design Objects 65
7.11 Using the Popup Menu to Add Signals to Wave Window 66
7.12 Waves Drawn in Wave Window 66
7.13 Setting Breakpoint in Source Window 67
7.14 Restart Dialog 68
7.15 Blue Arrow Indicates Where Simulation Stopped. 69
7.16 Values Shown in Objects Window 69
7.17 Parameter Name and Value in Source Examine Window 69
7.18 The Main Window 70
7.19 Window/Pane Control Icons 71
8.1 Simulation result of pattern one matched 72
8.2 Simulation result of pattern two matched 73
8.3 Simulation result of pattern not matched 74
8.4 Design summary report of previous algorithm 75
8.5 Design summary report of proposed AC_algorithm 75
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LIST OF TABLES
Table No. Name of the Table Page No
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LIST OF ACRONYMS
AC Aho-Corasick
ACK Acknowledgement
ALG Algorithm
CAD Computer Aided Design
CLK Clock
CPLD Complex Programmable Logic Device
DDR Double Data Rate
EDA Electronic Design Automation
FPGA Field Programmable Gate Array
FSM Finite State Machine
HDL Hardware Description Language
MUX Multiplexer
NIDS Network Intrusion Detection System
PHY Periphery
RTL Resistor Transistor Logic
SIDS Signature Based Intrusion Detection System
SIPO Serial In Parallel Out
TLM Transaction Level Modeling
VHSIC Very High Speed Integrated Circuits
VLSI Very Large Scale Integration
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