Power Consumption in CMOS

Power Consumption in CMOS
Gagandeep Singh,
Lecturer, ECED
Thapar University
Components of Power
Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit
Static
Leakage Ptotal = Pdyn + Psta+ Psc
Power of a Transition: Ptran
VDD
Ron
ic(t)
vi (t) vo(t)
R = large CL
Ground
Charging of a Capacitor
R
t=0
i(t) v(t)
V C
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt

i(t) = C dv(t)/dt = [V v(t)] /R
dv(t) V v(t)
=
dt RC
dv(t) dt
=
V v(t) RC
-t
ln [V v(t)] = + k
RC
Initial condition, t = 0, v(t) = 0 k = ln V
-t
v(t) = V [1 exp()]
RC
-t
v(t) = V [1 exp( )]
RC
dv(t) V -t
i(t) = C = exp( )
dt R RC
Total Energy Per Charging Transition from
Power Supply
V2 -t
Etrans = V i(t) dt = exp( ) dt
0 0 R RC
= CV2
Energy Dissipated per Transition in
Resistance
2 V2 -2t
R i (t) dt = R
2
exp( ) dt
0 R 0 RC
1
= CV2
2
Also called the energy stored in Capacitor
Energy Stored in Charged Capacitor
-t V -t
v(t) i(t) dt = V [1-exp( )] exp( ) dt
0 0 RC R RC
1
= CV2
2
Transition Power
Gate output rising transition
Energy dissipated in pMOS transistor = CV 2/2
Energy stored in capacitor = CV 2/2
Gate output falling transition
Energy dissipated in nMOS transistor = CV 2/2
Energy dissipated per transition = CV 2/2
Power dissipation:
Ptrans = Etrans fck = fck CV2/2
= activity factor
Short Circuit Power of a Transition: Psc
VDD
isc(t)
vi (t) vo(t)
CL
Ground
Short Circuit Current, isc(t)
VDD
VDD - VTp n-transistor
Vi (t)
Vo(t) cuts-off
Volt
VTn
p-transistor 0
starts Iscmaxf
conducting isc(t)
Isc
Time (ns)
0 tB tE 1
Peak Short Circuit Current
Increases with the size (or gain, ) of
transistors
Decreases with load capacitance, CL
Largest when CL = 0
Short-Circuit Energy
Increases with rise and fall times of input
Decreases for larger output load capacitance
Decreases and eventually becomes zero when
VDD is scaled down but the threshold voltages
are not scaled down
Psc, Rise Time and Capacitance
VDD
VDD
Ron
ic(t)+isc(t)
vi (t) vo(t)
vo(t)
CL tr
tf R = large vo(t)
Ground
R
isc, Rise Time and Capacitance
-t
VDD[1- exp()]
vo(t) R(t) C
Isc(t) = =
R(t) R(t)
iscmax, Rise Time and Capacitance
Psc, Rise Times, Capacitance
For given input rise and fall times short circuit
power decreases as output capacitance
increases.
Short circuit power increases with increase of
input rise and fall times.
Leakage Power
VDD
Ground IG
Gate
R
Source Drain
n+ Isub n+
IPT
IGIDL ID
Bulk Si (p)
nMOS Transistor
Sources of Leakages
Subthreshold Current ISub
DIBL (lowers Vt)
Punchthrough IPT
Thin Oxide Gate Tunneling IG
GIDL IGIDL
PN Junction Current ID
Leakage Current Components
Subthreshold conduction, Isub
Reverse bias pn junction conduction, ID
Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
Drain source punchthrough, IPT due to short
channel and high drain-source voltage
Gate tunneling, IG through thin oxide; may
become significant with scaling
Subthreshold Conduction
Subthreshold leakage is the most important
contributor to static power in CMOS.
Note that it is primarily a function of VT

Higher VT, exponentially less current!
Cont
Drain-Induced Barrier Lowering
Since the channel must be depleted of charge
before inversion
takes place, any help on depletion process will
reduce VT
Large Vds => large depletion layer around
drain
Part of channel surface already depleted
Lowered barrier => VT reduced => increased
leakage current
Cont
Fig (a) has lesser VD than Fig (b)
So in which case Vt will be higher ?
(a) (b)
Cont
For long-channel device, the depletion layer
width is small
around junctions so VT does not change
noticeably
For short-channel devices, as we increase VDS,
the depletion
layer will continue to increase and help to reduce
the VT
VT will continue to decrease as depletion layer
thickness grows
Punch Through
If source and drain depletion regions merge - -
Punch-through occurs!
Gate-Induced Drain Leakage (GIDL)
Drain-to-substrate leakage due to tunneling
current in very high field depletion region in
gate-drain overlap region.
Caused by thinner oxides, lightly-doped drains
and high VDD.
Cont.
Gate Tunneling
tox has been scaling with each technology
generation.
We have reached the point where tox is so small
the direct tunneling occurs (tox < 2nm)
Gate leakage = f(tox, VG)
NMOS leakage is 3-10X PMOS leakage (electrons
vs. holes)
Below 20 A, the leakage increases by 10X for
every 2A in gate thickness reduction
Cont
Increased Subthreshold Leakage
Scaled device
Ic
Log (Drain current)
Isub
0 VTH VTH Gate voltage

Low Power Techniques
Scaling (Decreases static/dynamic power but
increase in leakage currents ).
Power Gating (Clocked Power Supply).
Multi Vt designs (low Vt for time critical data paths,
high Vt for other data paths).
Adiabatic Technique.
Few more ..

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Power Consumption in CMOS

Charge on capacitor, q(t) = C v(t)

Current, i(t) = dq(t)/dt = C dv(t)/dt

Note that it is primarily a function of VT

0 VTH VTH Gate voltage

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