EEE458 VLSI II Laboratory Laboratory Module 3: Schematic Driven Layout Design With Virtuoso Layout Suite XL (VXL) Editor

Department of Electrical & Electronic Engineering
Bangladesh University of Engineering & Technology

EEE458 VLSI II Laboratory
Laboratory Module 3:
Schematic Driven Layout design with Virtuoso Layout Suite XL(VXL) Editor
Objectives:
This module will demonstrate schematic-driven layout on the example of a 2-input NAND
gate.
Lab 3-1 Creating Schematic Driven Layout using Virtuoso XL (VXL)

1. Open the schematic of the NAND2 cell you have generated in Lab1 using virtuoso
schematic editior.
2. Next, you need to invoke Layout XL from the schematic editor. Execute Launch Layout
XL A schematic window dialog will pop up and ask you to define connectivity reference.
3. Now go back to the Virtuoso Layout Editor to create layout view for this schematic. At the
left most side of the bottom of the layout editor you will see Generate from source. Click
this icon. The following pop-up window will appear:
The dialog box shows that all I/O pins are in Metal1 layer(Metal1 dg).
Just as an exercise, if you were to use Metal2 instead for pins Ain, Bin, and Out, you would
have selected Ain, Bin, and Out (hold Ctrl for multiple selection), choose Metal2 drawing
layer, and click the Update button. Click OK.
ABM H. Rashid, Dept. of EEE, BUET Page 1 8/03/2017

4. The initial pin and transistor placement in layout will look like this:
Bounding Box
Pin
Transistors

As seen above 2 PMOS and 2 NMOS transistors are created along with 5 pins namely Ain,
Bin, Out, Vdd and Gnd as defined in the schematic. Now change the display option as hown
in in lab2 with Minor spacing 0.005, Major spacing 0.05, X snap spacing 0.005 and Y snap
spacing 0.005. Also set Display Levels start 0 and Stop 32. Now you will able to see all the
layers in the transistors.
5. The transistors and pins are shown inside a bounding box, which is an estimate of the
optimum size of the final layout. Automatic router will use the bounding box to constrain
all routing to occur within the box. The bounding box may need to be re-sized to
accommodate all components. An important concept to keep in mind during resizing is that
standard cells typically have fixed height (so that power/ground rails line up correctly for
routing purposes).
6. VXL and gpdk045 allow us to create stacked transistors with shared source/drain areas.
Zoom in to two transistors on the bottom (to zoom in, type z and draw a box around the
transistors). Click on the transistor on the right and type m to move the object. As you
start dragging the object to the left, fly-lines indicating connectivity will appear as shown
below.
7. When the source/drain areas are overlapped, left-click to fix the position. You should see a
transistor stack with shared source/drain areas like this (depending on how far you move,
you may need to move left/right a bit):

8. This is a nice NMOS stack for the NAND gate. As you can see, the source/drain contacts
have disappeared thanks to VXL.
9. Lets do the same exercise for the PMOS transistors. Zoom in to two transistors on the
bottom (to zoom in, type z and draw a box around the transistors). Click on the transistor
on the right and type m to move the object. As you start dragging the object to the left,
fly-lines indicating connectivity will appear. Drag the transistor to the right:
10. The PMOS transistors do have shared drain contacts because they work in parallel.
Connectivity information is extracted from schematic by VXL. The pull-up network looks
like this:
11. In gpdk045 the standard cell height is 1.71m, with the power rails extending by 0.15m
over the top/bottom edges. Bring all the components within the boundary. Select the PMOS

transistors and move them a bit to the right or left (so that flylines appear) and make sure
Poly lines wont cross during routing.
12. Use create wire option to connect the poly lines of signal Ain of NMOS and PMOS to be
connected. Similarly connect Bin signal of NMOS and PMOS. Finally use wire option to
connect the Ain and Bin signal of poly lines to metal wires and connect it to the pins at the
boundary of the layout. Use create via optionto connect the metal and poly layers.
13. Similarly wire up the Out and Vdd and Gnd signal of your layout with the corresponding
pin. Your layout would be something like below:
Lab 3-2 Design Verification: Design Rule Check.

Now, we need to verify our design against layout design rules (DRC) such that no design rule have
been violated.
Execute Launch Plugin PVS
Perform the design rule check of the layout and make it DRC clean using PVS in the following
way:
In the Layout window click PVS and select Run DRC. A DRC run submission form appears as
shown below:

Click Run Data on the left side of the form. Set Run Directory.
Now click Rules file and select pvtech.lib as Technology mapping file and Gpdk045_pvs as
technology file and default as Rule Set. In input field confirm that library mylib and cell nand2
and view layout is selected. Additionally Start DRC DE give tick
Now submit the job.
You will soon find the console with message Waiting for Error and after some time output of the
DRC check will appear.
Correct the error and re-run the DRC until all the errors are corrected.
Lab 3-3 Design Verification: Layout vs. Schematic (LVS) Check.
Perform the Layout Vs Schematic check and make sure that the schematic and the layout match
each other.
1) Execute PVS Run LVS. The LVS run window appear as shown below:
Now fill up the form as follows:
2) In Run Data select
Run Directory nand2_run1

Run PVS Singe CPU
Run PVS on Local Host
3) In Rules select
Technology mapping file pvtech.lib

Technology gpdk045_pvs
Rule set Default
4) In input select
Library mylib,
Cell nand2,
View layout
5) In output select
Run ERC Check

Output Format ASCI
Start LVS DE
Create Quantus QRC Input Data
QRC Data Dir svdb
6) In LVS Options select
POWER Vdd and click to Global or Ports

GROUN Gnd and click to Global or Ports
.
Now submit the LVS comparison. After a few minutes you will get the following message if
your operation ended smoothly.
Lab 3-4 Parasitic Extraction.
Now perform Parasitic extraction from the layout and run SPECTR SPICE with the
parasitic included in the netlist.
For this purpose you need to execute QRC Setup Quantus QRC

Report
Follow standard template of EEE 458 lab report and include the following also:
1. Explain the good layout practices that were adapted in the schematic driven layout.

EEE458 VLSI II Laboratory Laboratory Module 3: Schematic Driven Layout Design With Virtuoso Layout Suite XL (VXL) Editor

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Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

Lab 3-1 Creating Schematic Driven Layout using Virtuoso XL (VXL)

ABM H. Rashid, Dept. of EEE, BUET Page 1 8/03/2017

ABM H. Rashid, Dept. of EEE, BUET Page 2 8/03/2017

ABM H. Rashid, Dept. of EEE, BUET Page 3 8/03/2017

ABM H. Rashid, Dept. of EEE, BUET Page 4 8/03/2017

Lab 3-2 Design Verification: Design Rule Check.

Execute Launch Plugin PVS

ABM H. Rashid, Dept. of EEE, BUET Page 5 8/03/2017

Now submit the job.

Lab 3-3 Design Verification: Layout vs. Schematic (LVS) Check.

Now fill up the form as follows:

2) In Run Data select

Run Directory nand2_run1

ABM H. Rashid, Dept. of EEE, BUET Page 6 8/03/2017

Technology mapping file pvtech.lib

Run ERC Check

6) In LVS Options select

POWER Vdd and click to Global or Ports

Lab 3-4 Parasitic Extraction.

ABM H. Rashid, Dept. of EEE, BUET Page 7 8/03/2017

ABM H. Rashid, Dept. of EEE, BUET Page 8 8/03/2017

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