3.

3 Microcontroller:

Fig: 3.2: Microcontrollers

3.3.1 Introduction to Microcontrollers:

Circumstances that we find ourselves in today in the field of microcontrollers had

their beginnings in the development of technology of integrated circuits. This development
has made it possible to store hundreds of thousands of transistors into one chip. That was a
prerequisite for production of microprocessors, and the first computers were made by adding
external peripherals such as memory, input-output lines, timers and other. Further increasing
of the volume of the package resulted in creation of integrated circuits. These integrated
circuits contained both processor and peripherals. That is how the first chip containing a
microcomputer, or what would later be known as a microcontroller came about.

Microprocessors and microcontrollers are widely used in embedded systems products.

Microcontroller is a programmable device. A microcontroller has a CPU in addition to a
fixed amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed
amount of on-chip ROM, RAM and number of I/O ports in microcontrollers makes them
ideal for many applications in which cost and space are critical.

3.3.2 Description of AT 89S52 microcontroller:

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with

8K bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density non-volatile memory technology and is compatible with the industry-
standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to
be reprogrammed in-system or by a conventional non-volatile memory programmer. By
combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,
the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-
effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-
vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock
circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode stops
the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to
continue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next interrupt or hardware reset.

3.3.3 Features of AT 89S52 architecture:

 8K Bytes of In-System Programmable (ISP) Flash Memory

--Endurance: 1000 Write/Erase Cycles

 4.0V to 5.5V Operating Range

 Fully Static Operation: 0 Hz to 33 MHz

 Three-level Program Memory Lock

 256 x 8-bit Internal RAM

 32 Programmable I/O Lines

 Three 16-bit Timer/Counters

 Eight Interrupt Sources

 Full Duplex UART Serial Channel

 Low-power Idle and Power-down Modes

 Interrupt Recovery from Power-down Mode

 Watchdog Timer

 Dual Data Pointer

  Power-off Flag

Now we may be wondering about the non-mentioning of memory space meant

for the program storage, the most important part of any embedded controller.
Originally this AT 89S52 architecture was introduced with on-chip, ‘one time
programmable’ version of Program Memory of size 4K X 8. Intel delivered all
these microcontrollers (AT 89S52) with user’s program fused inside the device. The
memory portion was mapped at the lower end of the Program Memory area. But,
after getting devices, customers couldn’t change anything in their program code,
which was already made available inside during device fabrication.

3.3.4 Pin Configuration:

Figure 3.3: Pin diagram of AT 89S52 microcontroller

Vcc: Pin 40 provides supply voltage to the chip. The voltage source is +5v.
Gnd: Pin 20 is the ground.

Ports 0, 1, 2 and 3:

As shown in pin diagram, the four ports P0, P1, P2, and P3 each with 8 pins, make the
8-bit ports. All the ports upon Reset are configured as input, since P0-P3 have FFH on them.

Port 0:

Port 0 occupies a total of 8 pins (pins 32-33). It can be used for input or output. Port0
is also designated as AD0-AD7, allowing it to be used for both address and data. When
connecting an AT 89S52 to an external memory, port 0 provides both address and data. The
AT 89S52 multiplexes address and data through port 0 to save pins. ALE=0, it provides data
D0-D7, but when ALE=1, it has address A0-A7. Therefore, ALE is used for demultiplexing
address address and data with the help of a 74LS373 latch. In the AT 89S52-based systems
where there is no external memory connection, the pins of P0 must be connected externally to
a 10k –ohm pull-up resistor. With external pull-up resistors connected to P0, it can be used as
a simple I/O port, just like P1 and P2. In contrast to Port 0, ports p1, p2, and p3 do not need
any pull-up resistors since they already have pull-up resistors internally. Upon reset, ports
p1, p2, and p3 are configured as input ports.

Port 0 can also be configured to be the multiplexed low order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0
also receives the code bytes during Flash programming and outputs the code bytes during
program verification. External pull-ups are required during program verification.

Port 1:

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled
high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pullups. In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the
following table. Port 1 also receives the low-order address bytes during Flash programming
and verification.
 Table 3.1: Port1 pins of microcontroller

Port 2:

Port 2 occupies a total 8 pins (pins 21-28). It can be used as input or output. However, in
8031-based systems, port2 is also designated as A8-A15, indicating its dual function. Since
an AT 89S52/31 is capable of accessing 64K bytes of external memory, it needs a path for the
16 bits of the address. While P0 provides the lower 8 bits via A0-A7, it is the job of p2 is
used for the upper 8 bits of the 16-bit address, and it cannot be used for I/O. Just like P1, port
2 does not need any pull-up resistors since it already has pull-up resistors internally. Upon
reset, port2 is configured as an input port.

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled
high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program memory and during
accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2
Special Function Register. Port 2 also receives the high-order address bits and some control
signals during Flash programming and verification.

Port 3:
 Port 3 occupies a total of 8 pins (pins 10-17). It can be used as input or output. P3
does not need any pull-up resistors, just as P1 and P2 did not. Although Port 3 is configured
as an input port upon reset, this is not the way it is most commonly used. Port 3 has the
additional function of providing some extremely important signals such as interrupts. The
below table provides these alternate functions of P3. This is information applies to both AT
89S52 and 8031 chips.

Table 3.2: Port3 pins of microcontroller

Alternate Functions of Port 3:

Port 3 also receives some control signals for Flash programming and verification.

RST:

Reset input. A high on this pin for two machine cycles while the oscillator is running resets
the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The
DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default
state of bit DISRTO, the RESET HIGH out feature is enabled.

Address Latch Enable (ALE) is an output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse input

during Flash programming. In normal operation, ALE is emitted at a constant rate

of 1/6 the oscillator frequency and may be used for external timing or clocking purposes.
Note, however, that one ALE pulse is skipped during each access to external data memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external
execution mode.

Program Store Enable is the read strobe to external Program Memory. When the
device is executing out of external Program Memory, this port is activated twice each
machine cycle (except that two PSEN activations are skipped during accesses to external
Data Memory). PSEN is not activated when the device is executing out of internal Program
Memory.

When EA is held high the CPU executes out of internal Program Memory (unless the
Program Counter exceeds 0FFFH in the AT 89S52). Holding EA low forces the CPU to
execute out of external memory regardless of the Program Counter value. In the 80C31, EA
must be externally wired low. In the EPROM devices, this pin also receives the programming
supply voltage (VPP) during EPROM programming.

XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2:

Output from the inverting oscillator amplifier.

The AT 89S52’s I/O port structure is extremely versatile and flexible. The
device has 32 I/O pins configured as four eight bit parallel ports (P0, P1, P2 and P3).
Each pin can be used as an input or as an output under the software control. These
I/O pins can be accessed directly by memory instructions during program execution
to get required flexibility.
 These port lines can be operated in different modes and all the pins can be
made to do many different tasks apart from their regular I/O function executions.
Instructions, which access external memory, use port P0 as a multiplexed
address/data bus. At the beginning of an external memory cycle, low order 8 bits of
the address bus are output on P0. The same pins transfer data byte at the later stage
of the instruction execution.

Also, any instruction that accesses external Program Memory will output the
higher order byte on P2 during read cycle. Remaining ports, P1 and P3 are available
for standard I/O functions. But all the 8 lines of P3 support special functions: Two
external interrupt lines, two counter inputs, serial port’s two data lines and two
timing control strobe lines are designed to use P3 port lines. When you don’t use
these special functions, you can use corresponding port lines as a standard I/O. Even
within a single port, I/O operations may be combined in many ways. Different pins can be
configured as input or outputs independent of each other or the same pin can be used
as an input or as output at different times. You can comfortably combine I/O
operations and special operations for Port 3 lines.

3.3.5 Memory organisation:

MCS-51 devices have a separate address space for Program and Data Memory. Up to
64K bytes each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external
memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H
through 1FFFH are directed to internal memory and fetches to addresses 2000H through
FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. This means that the upper 128 bytes
have the same addresses as the SFR space but are physically separate from SFR space. When
an instruction accesses an internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions which use direct addressing access of the SFR space. For example, the
following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example,
the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte
at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.

3.3.6 Basic registers:

In the CPU, registers are used to store information temporarily. That information
could be a byte of data to be processed, or an address pointing to the data to be fetched. The
vast majority of AT 89S52 registers are 8–bit registers. In the AT 89S52 there is only one
data type: 8bits. The 8 bits of a register are shall be in the diagram from the MSB (most
significant bit) D7 to the LSB (least significant bit) D0. With an 8-bit data type, any data
larger than 8bits must be broken into 8-bit chunks before it is processed.

The most widely used registers of the AT 89S52 are A(accumulator), B, R0, R1, R2,
R3, R4, R5, R6, R7, DPTR(data pointer), and PC(program counter). All of the above
registers are 8-bits, except DPTR and the program counter.

The Accumulator:

If you've worked with any other assembly language you will be familiar with the
concept of an accumulator register.

The Accumulator, as its name suggests, is used as a general register to accumulate the
results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most
versatile register the AT 89S52 has due to the sheer number of instructions that make use of
the accumulator. More than half of the AT 89S52's 255 instructions manipulate or use the
Accumulator in some way. For example, if you want to add the number 10 and 20, the
resulting 30 will be stored in the Accumulator. Once you have a value in the Accumulator
you may continue processing the value or you may store it in another register or in memory.
The "R" Registers:

The "R" registers are sets of eight registers that are named R0, R1, through R7. These
registers are used as auxiliary registers in many operations. To continue with the above
example, perhaps you are adding 10 and 20. The original number 10 may be stored in the
Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition
you would execute the command:

ADD A, R4

After executing this instruction the Accumulator will contain the value 30. You may
think of the "R" registers as very important auxiliary, or "helper", registers. The Accumulator
alone would not be very useful if it were not for these "R" registers.

The "R" registers are also used to store values temporarily. For example, let’s say you
want to add the values in R1 and R2 together and then subtract the values of R3 and R4. One
way to do this would be:

MOV A, R3 ; Move the value of R3 to accumulator

ADD A, R4 ; add the value of R4

MOV R5, A ; Store the result in R5

MOV A, R1 ; Move the value of R1 to Acc

ADD A, R2 ; add the value of R2 with A

SUBB A, R5 ; Subtract the R5 (which has R3+R4)

As you can see, we used R5 to temporarily hold the sum of R3 and R4. Of course, this
isn't the most efficient way to calculate (R1+R2) - (R3 +R4) but it does illustrate the use of
the "R" registers as a way to store values temporarily.

As mentioned earlier, there are four sets of "R" registers-register bank 0, 1, 2, and 3.
When the 8052 is first powered up, register bank 0 (addresses 00h through 07h) is used by
default. In this case, for example, R4 is the same as Internal RAM address 04h. However,
your program may instruct the 8052 to use one of the alternate register banks; i.e., register
banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address 04h. For
example, if your program instructs the 8052 to use register bank 1, register R4 will now be
synonymous with Internal RAM address 0Ch. If you select register bank 2, R4 is
synonymous with 14h, and if you select register bank 3 it is synonymous with address 1Ch.

The concept of register banks adds a great level of flexibility to the 8052, especially
when dealing with interrupts (we'll talk about interrupts later). However, always remember
that the register banks really reside in the first 32 bytes of Internal RAM.

The B Register:

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-
bit (1-byte) value. The "B" register is only used implicitly by two AT 89S52 instructions:
MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by
another number, you may store the other number in "B" and make use of these two
instructions.

Aside from the MUL and DIV instructions, the "B" register are often used as yet
another temporary storage register much like a ninth "R" register.

The Program Counter:

The Program Counter (PC) is a 2-byte address that tells the AT 89S52 where the next
instruction to execute is found in memory. When the AT 89S52 is initialized PC always starts
at 0000h and is incremented each time an instruction is executed. It is important to note that
PC isn't always incremented by one. Since some instructions are 2 or 3 bytes in length the PC
will be incremented by 2 or 3 in these cases.

The Program Counter is special in that there is no way to directly modify its value.
That is to say, you can't do something like PC=2430h. On the other hand, if you execute
LJMP 2430h you've effectively accomplished the same thing.

It is also interesting to note that while you may change the value of PC (by executing
a jump instruction, etc.) there is no way to read the value of PC. That is to say, there is no
way to ask the 8052 "What address are you about to execute?" As it turns out, this is not
completely true: There is one trick that may be used to determine the current value of PC.
This trick will be covered in a later chapter.

The Data Pointer:

 The Data Pointer (DPTR) in the AT 89S52 is only user-accessible 16-bit (2-byte)
register. The Accumulator, "R" registers, and "B" register are all 1-byte values. The PC just
described is a 16-bit value but isn't directly user-accessible as a working register.

DPTR, as the name suggests, is used to point to data. It is used by a number of

commands that allow the AT 89S52 to access external memory. When the AT 89S52
accesses external memory it accesses the memory at the address indicated by DPTR.

While DPTR is most often used to point to data in external memory or code memory,
many developers take advantage of the fact that it's the only true 16-bit register available. It is
often used to store 2-byte values that have nothing to do with memory locations.

The Stack Pointer:

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte)
value. The Stack Pointer is used to indicate where the next value to be removed from the
stack should be taken from.

When you push a value onto the stack, the AT 89S52 first increments the value of SP
and then stores the value at the resulting memory location. When you pop a value off the
stack, the AT 89S52 returns the value from the memory location indicated by SP and then
decrements the value of SP.

This order of operation is important. When the AT 89S52 is initialized SP will be

initialized to 07h. If you immediately push a value onto the stack, the value will be stored in
Internal RAM address 08h. This makes sense taking into account what was mentioned two
paragraphs above: First the AT 89S52 will increment the value of SP (from 07h to 08h) and
then will store the pushed value at that memory address (08h).

Register Instructions:

The register banks, containing registers R0 through R7, can be accessed by certain
instructions which carry a 3-bit register specification within the opcode of the instruction.
Instructions that access the registers this way are code efficient, since this mode eliminates an
address byte. When the instruction is executed, one of the eight registers in the selected bank
is accessed. One of four banks is selected at execution time by the two bank select bits in the
PSW.
Register-Specific Instructions:

Some instructions are specific to a certain register. For example, some instructions
always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to
point to it. The opcode itself does that. Instructions that refer to the Accumulator as A
assemble as accumulator specific opcodes.

Immediate Constants:

The value of a constant can follow the opcode in Program Memory. For example,

MOV A, #100

loads the Accumulator with the decimal number 100. The same number could be specified in
hex digits as 64H.

3.3.7 Central processing unit:

The CPU is the brain of the microcontrollers reading user’s programs and
executing the expected task as per instructions stored there in. Its primary elements
are an 8 bit Arithmetic Logic Unit (ALU ) , Accumulator (Acc ) , few more 8 bit
registers , B register, Stack Pointer (SP ) , Program Status Word (PSW) and 16 bit
registers, Program Counter (PC) and Data Pointer Register (DPTR).

The ALU (Acc) performs arithmetic and logic functions on 8 bit input
variables. Arithmetic operations include basic addition, subtraction, and multiplication
and division. Logical operations are AND, OR, Exclusive OR as well as rotate, clear,
complement and etc. Apart from all the above, ALU is responsible in conditional
branching decisions, and provides a temporary place in data transfer operations
within the device.

B-register is mainly used in multiply and divides operations. During

execution, B register either keeps one of the two inputs or then retains a portion of
the result. For other instructions, it can be used as another general purpose register.

Program Status Word (PSW) keeps the current status of the ALU in different
bits. Stack Pointer (SP) is an 8 bit register. This pointer keeps track of memory space
where the important register information is stored when the program flow gets into
executing a subroutine. The stack portion may be placed in any where in the on-
chip RAM. But normally SP is initialized to 07H after a device reset and grows up
from the location 08H. The Stack Pointer is automatically incremented or
decremented for all PUSH or POP instructions and for all subroutine calls and
returns.

Program Counter (PC) is the 16 bit register giving address of next instruction
to be executed during program execution and it always points to the Program
Memory space. Data Pointer (DPTR) is another 16 bit addressing register that can be
used to fetch any 8 bit data from the data memory space. When it is not being used
for this purpose, it can be used as two eight bit registers.

3.3.8 Timers/counters:

Watchdog Timer(One-time Enabled with Reset-out):

The WDT is intended as a recovery method in situations where the CPU may be
subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the
WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location
0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator
is running. The WDT timeout period is dependent on the external clock frequency. There is
no way to disable the WDT except through reset (either hardware reset or WDT overflow
reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT:

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST
register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter
overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. This means the
user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sections of code that will periodically be
executed within the time required to prevent a WDT reset.

Timer 0 and 1:
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in
the AT89C51 and AT89C52.

Timer 2:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three
operating modes: capture, auto-reload (up or down counting), and baud rate generator. The
Modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2.
In the Timer function, the TL2 register is incremented every machine cycle. Since a machine
cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

3.3.9 Serial ports:

Each AT 89S52 microcomputer contains a high speed full duplex (means you
can simultaneously use the same port for both transmitting and receiving purposes)
serial port which is software configurable in 4 basic modes: 8 bit UART; 9 bit
UART; inter processor Communications link or as shift register I/O expander.

For the standard serial communication facility, AT 89S52 can be programmed

for UART operations and can be connected with regular personal computers, teletype
writers, modem at data rates between 122 bauds and 31 kilo bauds. Getting this
facility is made very simple using simple routines with option to elect even or odd
parity. You can also establish a kind of Inter processor communication facility among
many microcomputers in a distributed environment with automatic recognition of
address/data. Apart from all above, you can also get super fast I/O lines using low
cost simple TTL or CMOS shift registers.

3.3.10 Interrupts:

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these
interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at
once. Note that Table 5 shows that bit position IE.6 is unimplemented.In the AT89S52, bit
position IE.5 is also unimplemented. User software should not write 1s to these bit positions,
since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical
OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared
in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the
timer overflows.

Table 3.3: Interrupt enable(IE) register

 Table 3.4: Interrupt Enable(IE) register Functions.

3.3.11 Oscillator Characteristics:

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock source,
XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
Figure3.4 (a): Oscillator connections. Figure 3.4(b): External clock drive
configuration.

3.3.12 Idle Mode:

In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain
active. The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be terminated by
any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a
hardware reset, the device normally resumes program execution from where it left off, up to
two machine cycles before the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by
a reset, the instruction following the one that invokes idle mode should not write to a port pin
or to external memory.

3.3.13 Power-down Mode:

In the Power-down mode, the oscillator is stopped, and the instruction that invokes
Power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the Power-down mode is terminated. Exit from Power-
down mode can be initiated either by a hardware reset or by an enabled external interrupt.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
 Table 3.5 Status of external pins in idle and power down mode

3.3.14 Criteria in choosing a microcontroller:

1. The first and foremost criterion in choosing a microcontroller is that it must meet task at
hands efficiently and cost effectively. In analyzing the needs of a microcontroller based
project we must first see whether it is an 8-bit, 16-bit or 32-bit microcontroller and how
best it can handle the computing needs of the task most effectively. The other
considerations in this category are:

(a) Speed: The highest speed that the microcontroller supports

(b) Packaging: Is it 40-pin DIP or QPF or some other packaging format? This is
important in terms of space, assembling and prototyping the End product.

(c) Power Consumption: This is especially critical for battery-powered Products.

(d) The amount of RAM and ROM on chip

(e) The number of I/O pins and timers on the chip.

(f) Cost per unit: This is important in terms of final product in which a
microcontroller is used.

2. The second criteria in choosing a microcontroller are how easy it is to develop products
around it. Key considerations include the availability of an assembler, debugger, a code
efficient ‘C’ language compiler, emulator, technical support and both in house and
outside expertise. In many cases third party vendor support for chip is required.

3. The third criteria in choosing a microcontroller is it readily available in needed quantities

both now and in future. For some designers this is even more important than first two
criteria’s. Currently, of leading 8–bit microcontrollers, the AT 89S52 family has the
largest number of diversified (multiple source) suppliers. By suppliers meant a producer
besides the originator of microcontroller in the case of the AT 89S52, which was
originated by Intel, several companies are also currently producing the AT 89S52. Viz:
INTEL, PHILIPS, These companies include PHILIPS, SIEMENS, and DALLAS-
SEMICONDUCTOR. It should be noted that Motorola, Zilog and Microchip
Technologies have all dedicated massive resource as to ensure wide and timely
availability of their product since their product is stable, mature and single sourced. In
recent years they also have begun to sell the ASIC library cell of the microcontroller.