Design and Implementation of a Multi Level Three-Phase Inverter with … 593

JPE 9-4-9

Design and Implementation of a Multi Level Three-Phase Inverter with

Less Switches and Low Output Voltage Distortion

Mahrous E. Ahmed† and Saad Mekhilef *

†
Faculty of Engineering South Valley University, Aswan, Egypt
*
Dept. of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia

ABSTRACT

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage
source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the
full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a
significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the
proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output
waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge
power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit
switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been
performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental
results have been provided.

Keywords: Two-level inverter, Multi level inverter, Total harmonic distortion, Three level output waveform inverter

1. Introduction inverters is far from a sinusoid. The output voltage

waveform total harmonic distortion (THD) ratio is
The high standards applied today to electrical energy approximately 31% [1]. In addition, in the case of high
increases the requirement of clean sinusoidal waveforms, power, the use of the conventional inverters very rare due
with minimum harmonics content. Although this can be to the fact that the power switches have to withstand the
achieved with the use of conventional inverters with six full network voltage.
step modulation control this approach is seldom applied in There are some proposed solutions in [2] – [6], where
practice. The output voltage of conventional two-level these topologies are formed from two cells of the classical
two-level inverter topology. The outputs of these cells can
Manuscript received January 22, 2009; revised May 22, 2009 be added together using injection transformers [2] - [4] or by
†
Corresponding Author: mahrous@svu.edu.eg
Tel: +2097-4661589, Fax: +2097-4661406, South Valley Univ. directly connecting the output of one cell in series with
Faculty of Engineering South Valley University, Egypt another [5] – [6]. As a result, the harmonic content of the
*
Dept. of Electrical Engineering, Univ. of Malaya, Malaysia output voltage is significantly reduced.
594 Journal of Power Electronics, Vol. 9, No. 4, July 2009

Multilevel inverters (MLIs) can be used to solve these the auxiliary circuit is formed from two switching
problems. They are built using a number of cells; each cell elements and two diodes, while in [19] the auxiliary
consisting of switches and capacitor voltage sources. The circuit contains one switching element and a full bridge of
control of the power switches allows the capacitor voltage diodes. In [20] a switched capacitor circuit is used which
sources to be added to obtain the desired output voltage is formed from two diodes, two capacitors and a switching
with reduced voltage stress on each individual switch. element. As a result, a five-level waveform is obtained at
Also, the resolution of the staircase waveform of the the inverter output which results in significant suppression
output voltage increases with the number of voltage steps of the load harmonic currents when compared with the
of capacitor voltage sources available in the multilevel classical three-level full bridge inverter.
inverter. Three different main topologies have been Many three-phase loads require a supply of variable
reported for multilevel inverters: 1) diode-clamped or voltage at a variable frequency, including fast and high
neutral-clamped [7]–[9], where the dc-bus voltage is split efficiency control by electronic means [21]. The power
into (n+1) levels by n capacitors, where the middle point is requirements for these applications range from fractions of
called the neutral point and a number of diodes clamp the kilowatts to several megawatts. It is preferred in general to
stress voltage on the power switches; 2) capacitor-clamped take the power from a dc source and convert it to
or flying capacitors [10]–[12], where additional capacitors are three-phase ac using power electronic dc-to-ac converters.
used to clamp the switches’ voltage stress; 3) cascaded The input dc voltage, mostly of constant magnitude, is
multi-cell with separate dc sources [3], [13], [14], where each obtained from a public utility through rectification, or from
phase leg consists of n similar cells connected in a series a storage battery in the case of an electric vehicle drive.
with each cell formed from a switched capacitor and four Based on the VIENNA Rectifier II [16], this paper
power switches. All these solutions are relatively simple proposes a three-phase inverter topology consisting of
for getting a three-level staircase waveform, but become three bi-directional switches inserted between the source
extremely complicated for getting a higher multilevel and the full-bridge power switches of the classical
staircase waveform. three-phase inverter, where the dc source is taken from the
A well-known example for the three-phase diode ac utility through rectification. Section 2 describes and
clamed MLI is the neutral point clamped inverter [15] explains the proposed inverter general block diagram, the
which is widely used in industrial applications. It uses four inverter configuration, its operating principles and the
switching elements and two clamping diodes in each leg. control pulses needed for operating the inverter switches.
It has three-level voltage waveforms. Zero, positive and Section 3 subsequently presents an analysis of the total
negative supply dc voltage levels that result in harmonics distortion minimization control method and the
considerable suppression of the harmonic currents when inverter output waveform total harmonic distortion THD
compared with conventional full-bridge two-level minimization analysis. To serve as a reference for the
inverters. Another well-know 3-level example is the inverter’s validity, section 4 gives Matlab simulated
VIENNA Rectifier [16]. It consists of three bidirectional results and laboratory measurements. These results are
switches, a three-phase full bridge diode rectifier, and a used for verifying the performance of the proposed
high switching transformer in its structure to get a 3-level three-level inverter prototype whose analysis is presented
boost type rectifier system. This can be called a in Section 2. Section 5 summarizes the proposed inverter
unidirectional type. A similar topology can be found in concepts presented in the paper.
[17] with a higher number of switches.
The principle of improving the quality of the waveform 2. The Proposed Inverter Topology
of the classical inverter by inserting an auxiliary circuit
between the source and the power switches of the The block diagram of the proposed three-phase
full-bridge inverter has been reported in the literature for three-level voltage source inverter system consists of two
single phase inverter only in [18], [19], and [20]. In [18], isolated and regulated dc sources, three-level inverter,
 Design and Implementation of a Multi Level Three-Phase Inverter with … 595

microcontrollers, a data acquisition card PCL-818L, and a Q1 Q3 Q5

personal computer as shown in fig. 1. This system acts as a ia
S1
a link between the output of the linear generator and the Vdc
ib
load, where the linear generator output voltage magnitude 2 S2 b
N
Vdc
is a single phase distorted waveform with its frequency ic
2 S3
c
varying from 25 to 50 Hz. Due to that, it is not suitable for
many applications, which use a 50 Hz ac. The inverter Q2 Q4 Q6

output voltage can be controlled by controlling the dc n

inverter bus link voltages, where two dc-dc boost Figure 2: The proposed ninethree-level
switches inverter.
Fig. 2. The proposed nine switch
converter circuits with a 10 kHz switching frequency have three-level inverter
been used. The measured voltages of the inverter dc t1/2 t1/2
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
capacitor link (two analogue signals) from the sensors are
Q1
received first by microcontroller1 and microcontroller2 200V
S1 S1
which convert them to 8 bits digital signals for each 2
Q2
analogue signal (16 bits total). These 16 digital bits are 1
Q3
received by the PC through the PCL-818L card.
S2 S2
The digital data is processed in real time to calculate the 100V
Q4
duty cycle of each dc-dc converter using a PID controller.
Q5 Q5
The sampling frequency is chosen to be 2 kHz which is S3 S3

fast enough to perform these calculations. These duty Q6

0V
cycles are subsequently sent back to the hardware through 0s
0ms /2
5ms 
10ms 15ms
3/2 20ms2
the PCL-818L card in a digital form. Microcontroller1 and V(G1A,G1B)+195
Figure 3: V(G2A,0)+145 V(G3A,G3B)+120
Switching timing diagram.V(G4A,0)+70 V(G5A,G5B)+45 V(G6A,0)
V(G7A,G7B)+170 Fig.
V(G8A,G8B)+95
3. V(G9A,G9B)+25 timing diagram.
Switching
Microcontroller2 receive this digital data from the Time
PCL-818L card and converts it to a duty cycle required by
each switch in the dc-dc converter. Microcontroller3 is Fig. 2 shows the proposed inverter which consists of
used to generate the inverter nine controlling pulses. In two isolated H-bridge circuit units, capacitor banks
order to avoid a short circuit during the transition between respectively, conventional two-level inverters
switches of each leg, a proper time delay has been
through as a main inverter at 50 Hz switching
considered.
frequency; and an additional circuit which compromises of

Nine switches
bi-directional (middle) switches through , at 100
2 units of H- 2 units of boost
DC-DC converter inverter Hz switching frequency, which allows energy to flow in
bridge rectifier
+ both directions.
 Vdc/2

-
AC  +
 Vdc/2 3. The Operational Principals
-
Low frequency
Transformer
Nine gating Fig. 3 shows the proposed controlling pulses of the
Isolation & signals for
Duty
amplifier switches switches, where the operations can be divided to 12
cycles Microcontroller3
switching states. The switch on/off states are shown in
Microcontroller1 Table 1 and the operational modes are illustrated in fig.
Isolation &
Driver Microcontroller2
4(i), (ii), (iii), (iv), (v), (vi), (vii), (viii), (ix), (x), (xi), and
(xii). The operational modes can be explained as follows:
Figure 1: Block diagram of the proposed inverter and the feedback control circuit. Mode i: For switching duration time ( ), only
Fig. 1. Block diagram of the proposed inverter and the
switches , , are in the on-state and all the
feedback control circuit.
596 Journal of Power Electronics, Vol. 9, No. 4, July 2009

Table 1. Switching states of switches in each step duration.

Step Condu
Durati ction
on period

0 1 0 1 1 0 0 0 0

0 0 0 1 1 0 1 0 0

1 0 0 1 1 0 0 0 0

1 0 0 1 0 0 0 0 1

1 0 0 1 0 1 0 0 0

1 0 0 0 0 1 0 1 0

1 0 1 0 0 1 0 0 0

0 0 1 0 0 1 1 0 0

0 1 1 0 0 1 0 0 0

0 1 1 0 0 0 0 0 1

0 1 1 0 1 0 0 0 0

0 1 0 0 1 0 0 1 0

other switches are in the off-state; i.e; , In this case both load nodes 'a' and 'c' are connected to the
and , which means that both load nodes 'a' and top point of the dc bus, while load node 'b' is connected to the
'b' are connected to the neutral point of the dc bus, while neutral point of the dc bus as shown in fig. 4(iii).
load node 'c' is connected to the top point of the dc bus as Mode iv: For switching duration time ( ), only
shown in fig. 4(i). switches , , are in the on-state and the other
Mode ii: For switching duration time ( ), only switches are in the off-state,
switches , , are in the on-state and the other
. This
switches are in the
means that load node 'a' is connected to the top point of
off-state, . the dc bus, load 'b' is connected to the neutral point of the
This means that load node 'a' is connected to the middle dc bus, and load node 'c' is connected to the middle point
point of the dc bus, load 'b' is connected to the neutral of the dc bus as shown in fig. 4(iv).
point of the dc bus, and load node 'c' is connected to the Mode v: For switching duration time ( ), only
top point of the dc bus as shown in fig. 4(ii). switches , , are in the on-state and the other
Mode iii: For switching duration time ( ), switches are in the off-state, .
only switches , , are in the on-state and the During this switching period, both load nodes 'b' and 'c' are
other switches are in the off-state, connected to the neutral point of the dc bus, and the load node 'a'
. is connected to the top point of the dc bus as shown in fig. 4(v).
 Design and Implementation of a Multi Level Three-Phase Inverter with … 597

Q1 Q3 Q5
Q1 Q3 Q5
S1 a ia
S1 a ia
Vdc Vdc
2 b ib
S2 2 b ib
N S2
Vdc N
Vdc 3
ic
2 S3 c 2 c
ic
S3
Q2 Q4 Q6
Q2 Q4 Q6
n n
Mode i; van  0; vbn  0, vcn Vdc Mode ii; van  V
dc V
; vbn  0, vcn  Vdc
Mode i; van  0; vbn  0, vcn Vdc Mode ii; van  2 dc
; vbn  0, vcn Vdc
2
Q1 Q3 Q5 Q1 Q3 Q5

S1 a ia S1 a ia
Vdc Vdc
ib 2 b ib
2 S2
b S2
N N
Vdc Vdc
ic
2 S3 c ic 2 S3 c

Q2 Q4 Q6 Q2 Q4 Q6

n n

V
Mode iii; van Vdc; vbn  0, vcn Vdc Mode iv; van  Vdc ; vbn  0, vcn  dc V
Mode iii; van Vdc ; vbn  0, vcn Vdc Mode iv; van  Vdc ; vbn  02, vcn  dc
2
Q1 Q3 Q5 Q1 Q3 Q5

S1 a ia S1 a ia
Vdc Vdc
ib ib
2 S2 b 2 S2 b
N N
Vdc Vdc
ic ic
2 S3 c 2 S3 c

Q2 Q4 Q6 Q2 Q4 Q6
n n

Mode v; van Vdc ; vbn  0, vcn  0 V

Mode vi; vvan  VdcV; vbn; v dc, vVcndc 0, v  0
Mode v; van Vdc ; vbn  0, vcn  0 Mode vi; an dc bn 2 cn
2
Q1 Q3 Q5 Q1 Q3 Q5

S1 a ia S1 a ia
Vdc Vdc
ib ib
2 b 2 S2 b
S2 N
N
Vdc Vdc
ic ic
c 2 S3 c
2 S3

Q2 Q4 Q6 Q2 Q4 Q6

n n

V
van V 0cn  0 an ; vbn Vdc
, vVcndc,0 vcn  0
V Vdc dc
Mode
Mode vii;vii;van dc; ;vbn
Vdc vbn dcV cn ,v
, vdc Mode viii; vvan
Modeviii; ; vbn
22
Q1 Q3 Q5 Q1 Q3 Q5

a ia S1 a ia
S1
Vdc Vdc
ib ib
2 S2 b 2 S2
b
N N
Vdc Vdc
ic
2 S3 c ic 2 S3 c

Q2 Q4 Q6 Q2 Q4 Q6

n n

ix; vvan 0;0v;bnvVdc , vcn  Vdc Vdc

0;  bn, vcnVdc , vcn 
bn Vdc , 0vcn  0 Modex;x;vanvan vbn0; V
Modeix;
Mode Mode vdc
an 2 2
Fig. 4. Operational states of switches according to the switches on-off conditions. (Continued)
598 Journal of Power Electronics, Vol. 9, No. 4, July 2009

Q1 Q3 Q5 Q1 Q3 Q5

a ia a ia
S1 S1
Vdc Vdc
ib ib
2 b 2 S2 b
S2 N
N Vdc
Vdc
ic ic
2 c 2 S3 c
S3

Q2 Q4 Q6 Q2 Q4 Q6
n n

xi; vvan VV Mode xii; van  0; vbn  Vdc , vcnVdc

an dcdc ;bnvbndc Vcn
Modexi;
Mode ; v  V , v , Vvdc  V Mode xii; van  0; v2 bn  Vdc, vcn  Vdc
dc cn dc
2

Fig. 4. Operational states of switches according to the switches on-off conditions.

Mode vi: For switching duration time ( ), only load node 'b' is connected to the top point of the dc bus as
switches , , are in the on-state and the other shown in fig. 4(ix).
switches are in the off-state, Mode x: For switching duration time ( ), only
switches , , are in the on-state and the other
. This means that load switches are in the off-state
node 'a' is connected to the top point of the dc bus, load
node 'b' is connected to the middle point of the dc bus, and
load node 'c' is connected to the neutral point of the dc bus During this switching period, load node 'a' is connected to
as shown in fig. 4(vi). the pole of the dc bus, load node 'b' is connected to top
Mode vii: For switching duration time ( ), point of the dc bus, and load node 'c' is connected to the
middle point of the dc bus as shown in fig. 4(x).
only switches , , are in the on-state and the
other switches are in the off-state, Mode xi: For switching duration time (2 ),
only switches , , are in the on-state and the
other switches are in the off-state
During this duration period, both load nodes 'a' and 'b' are . In this
connected to the top point of the dc bus, and the load node 'c' switching period both the load nodes of 'b' and 'c' are
is connected to the neutral point of the dc bus as shown in fig. connected to the top point of the dc bus, while load node
4(vii). 'a' is connected to the neutral point of the dc bus as shown
Mode viii: For switching duration time ( ), in fig. 4(xi).
only switches , , are in the on-state and the Mode xii: For switching duration time ( ),
other switches are in the off-state only switches , , are in the on-state and the
other switches are in the off-state
The load node 'a' is
connected to the top point of the dc bus, load node 'b' is In this case load
connected to the middle point of the dc bus, and load node node 'a' is connected to the pole of the dc bus, load node
'c' is connected to the neutral point of the dc bus as shown 'b' is connected to the middle point of the dc bus, and load
in fig. 4(vii). node 'c' is connected to the top point of the dc bus as
Mode ix For switching duration time (2 ), only shown in fig. 4(xii).
switches , , are in the on-state and the other In all of the above mentioned modes of operation
switches are in the off-state . conditions, while turning on and off the switches; the
In this case of switching duration both of the load nodes 'a' direction of load currents depends on
and 'c' are connected to the neutral point of the dc bus, and voltages .
 Design and Implementation of a Multi Level Three-Phase Inverter with … 599

The efficiency of the whole converter circuit is high

which is attributed to the inverter switches operating at
(4)
low switching frequencies, (where the total switching
times are much less than the period). This will result in
The line-to-line load voltage can be obtained
the switching losses of the inverter circuit to be negligible
[22]
using the following equation:
. In addition to the boost topology used with a single
switch, it has high efficiency [1]. (5)

4. Analysis of the Optimized Waveform From equations (4) and (5), the phase voltage of node 'a'
and the line-to-line voltage can be calculated
By applying the switching patterns given in fig. 3, the and drawn as shown in fig. 6. The load phase voltage
node 'a' referred to point 'n' can be defined as follows:
has 7 steps ( )
- For voltage level , turn on the upper switch and the line-to-line voltage has 5 steps
.
( ). The line-to-line voltage
- For voltage level , turn on the middle switch waveform as shown in fig. 6 (b) is known as a stepped
. waveform. A Fourier analysis of this waveform gives the
- For voltage level , turn on the lower switch magnitudes of the harmonics as a function of and
. as shown in equation (6).

The switches’ conduction angles can be calculated from

fig. 5 as follows:
- For upper switches , , and
, n=1,3,5,…… (6)
(1)
The voltage rating of the upper or lower switch is
- For lower switches , , and because it conducts during the total bus voltage while the

voltage rating of the middle switch is because it

(2) conducts during half of the dc bus voltage. The current voltage
ratings of these different switches are shown in table 2.
- For bi-directional switches , , and
The ideal is to get a clean sinusoidal output voltage, i.e.,
(3) the content of the harmonics orders greater than one (n=3,
5, 7 …) should be zero. The THD of the output voltage
Therefore from equations (1), (2), and (3),
.
is defined as where is
Fig. 5 illustrates the load phase voltages calculated from (6). Fig. 7 shows a computer simulation of

referred to the neutral point of the the THD as a function of the parameters and ,
dc bus. If neutral point 'n' of the dc bus is not connected to where the minimum THD (THD < 16%) is obtained for
the neutral point of the load 'N', the phase voltages of the and .
load are related to the neutral point of the dc bus 'n' as By comparing the proposed inverter which consists of 9
given in [23] by the following equation: power switches and 12 main power diodes with the
600 Journal of Power Electronics, Vol. 9, No. 4, July 2009

three-level NPC inverter which consists of 12 main power 40

22

48
18

20

44

46
32

34

36

40
switches and 6 main power diodes[24]–[25] under

28

42
35

18
16

38
30
2 [degree]

24
fundamental frequency modulation, it can be concluded

22
30

26
24
that they produce the same output voltage waveform

16
25

26

20
20

18
22

44
28
performance. Also table 3 gives a comparison between the

32

34
36

40
28
20

42
18

38
30
proposed inverter and the well-known 3-level inverters:

24
32

24
15

22
20

30

26
34
26 22

diode-clamped, flying capacitor, and cascaded inverters. 10 28

38
It can be concluded that the disadvantage of the 36
24

32
5

36
34

40
32

28
40 26
30

44 46
proposed inverter is that the voltage ratings of the switches

42
34

30
28

38
0
0 5 10 15 20 25 30 35 40

have not been reduced. Also, they have different ratings 1[degree]

Figure 7. THD of the output voltage as a function of 1 and 2.

which are similar to the voltage ratings of the
Fig. 7. THD of the output voltage as a function of 1 and 2.
diode-clamped inverter switches [10]. Some switches have
Table 2. Current and voltage ratings for inverter switches.
ratings of while others have voltage ratings of .
In this proposed topology, the RMS Current ratings Max Current ratings

switches have the same The upper

%(Iswitch/ILoad)RMS 72.5 %(Iswitch/ILoad)max= 100
switch
voltage and current switch ratings ( and load current) The lower
%(Iswitch/ILoad)RMS 72.5 %(Iswitch/ILoad)max= 100
and are greater than middle switches switch
The
( /2 and 27.2% of the load current). middle %(Iswitch/ILoad)RMS 27.2 %(Iswitch/ILoad)max  50
switch

Vdc 4/3-1 RMS voltage ratings max voltage ratings

Vdc / 2
4/3-1-2
0
1 2 1 The upper
%(Vswitch RMS /Vdc)  66 %(Vswitchmax/Vdc)= 100
Vdc
switch
Vdc / 2 The lower
0 %(Vswitch RMS /Vdc)  66 %(Vswitchmax/Vdc)= 100
switch
Vdc The
Vdc / 2
0
middle %(Vswitch RMS /Vdc)  43 %(Vswitch max/Vdc) = 50
0  2
2/3-1
2 4/3+1
switch
RMS  root mean square
max  maximum
Figure 5: MATLAB SIMULINK simulated waveforms of the load node

Fig. 5. MATLAB SIMULINK simulated waveforms of the

voltages van , vbn , and vcn

load node voltages and .

Table 3. Comparison of the proposed 3L inverter with the
well-known 3-level inverters.
2Vdc / 3
Vdc / 21
Vdc / 3

00 Converter Proposed Diode- Flying- Cascaded

Vdc / 3 type inverter clamp capacitors inverters
Vdc / 2-1
2Vdc / 3
(a) Main
3
2
switching 9 12 12 12
Vdc2
1
Vdc / 2 devices
1 00 Vdc / 2
Main 18 12 12 12
-1

Vdc-2
diodes
-3
0  2 3/2 4
Clamp- 0 6 0 0
(b)
2 2 ing diodes
Figure 6: MATLAB SIMULINK simulated waveforms of:
DC bus 2 2 2 3
Fig. 6. MATLAB SIMULINK simulated
(a) the load phase voltage waveform v waveforms of: aN

(b) the line-to-line voltage waveform v

Balanc-
(a) the load phase voltage waveform ab
and (b) the ing 0 0 3 0
line-to-line voltage waveform . capacitors
 Design and Implementation of a Multi Level Three-Phase Inverter with … 601

5. Results and Discussions phase voltage with seven steps and the line-to-line
voltage with five steps which were obtained in the
The proposed topology has been simulated using simulation results. Fig. 12 shows the phase voltage
MATLAB/SIMULINK® to verify the performance of the
and the line current .
proposed configuration. The dynamic response due to a
sudden change in the reference voltage is presented and a 120

110
Proportional Integral and Derivative (PID) controller has

Vdc/2 [V]
100

been implemented in order to maintain balanced voltages 90

Vdc / 2

in the dc bus capacitor. A balanced three-phase star 80

70
connected RL load with 30 resistance, and 50mH 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

inductor per phase was used. 120

110
Fig. 8 shows the inverter dc bus voltages of the upper

Vdc/2 [V]
100

and the lower capacitor banks respectively with controllers, 90

Vdc / 2

where a step change in the reference voltage from 80V to 80

70
110V is shown. Because the voltage of each capacitor is 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time [Sec]
regulated to 80 V or 110 V, the total dc-link voltage is
maintained at 160 V and 220 respectively. Fig. 9 shows Figure 8: simulation
Fig. 8. Simulation resultsof
results of the
theupper and lower
upper andregulated
lowercapacitor
regulated
banks voltages.
the inverter output waveforms of the phase voltage , capacitor banks voltages.

line-to-line voltage , and the line current . The 150

phase voltage exhibits seven levels 100

vaN [V]

50

-50

-100

( ), and the -150

0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

150

line-to-line voltage shows five levels 300

100

200
50
vab [V]

100
0

0
-50

-100
-100

( ). It is clearly -200
-150

-300
0.06
0.06 0.08

0.08
0.1

0.1
0.12

0.12 0.14
0.14 0.16

0.16
0.18

0.18
0.2

0.2

shown that , , and follow the step change in 2

ia [A]

dc capacitor voltage at 100ms. 0

-1

To validate the proposed inverter, an experimental -2

-3
0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

prototype of the proposed inverter has been built, Time [sec]

Fig. 9. Figure
Inverter9: Inverter
outputoutput
(from (from
toptoptotobottom)
bottom) phase
vaN, phasevoltage vaN,
voltage
experimentally tested, and compared with the simulated line to line voltage vab , and line (phase) current ia respectively
results. A balanced three-phase star connected load with line to line voltage vab, and line (phase) current ia
respectively.
30 resistance, and 50mH inductor per phase was used.
The inverter circuit was built using insulated gate bipolar
transistors (IGBTs) as switches, and each bi-directional
switch consisting of one IGBT and 4 elements of fast
Vdc / 2
diode rectifiers. The inverter switching frequencies are 50

Hz for the conventional two-level inverter and 100 Hz for
bi-directional switches. The control circuit switching
frequency is 10 kHz which consists of 2 units of dc-dc
boost converters. Vdc / 2

Fig. 10 shows a step change in the dc link capacitor  1) Ch 1: 50 Volt 50 ms

2) Ch 2: 50 Volt 50 ms
voltage, where a step change has been applied from 80V
to 110 V in each capacitor bank, thus maintaining 160V Figure 10: The inverter dc bus voltages (50V/div, 50ms/div).
and 220V on the dc bus, respectively. Fig. 11 shows the Fig. 10. The inverter dc bus voltages (50V/div, 50ms/div).
602 Journal of Power Electronics, Vol. 9, No. 4, July 2009

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