IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.

1, JANUARY 2007 149

A Novel Four-Level Voltage Source

Inverter—Influence of Switching Strategies
on the Distribution of Power Losses
George S. Perantzakis, Member, IEEE, Fotis H. Xepapas, and Stefanos N. Manias, Fellow, IEEE

Abstract—In this paper, a novel four-level inverter will be

presented and analyzed. The proposed inverter topology, which
is composed of a conventional two-level and a three-level neu-
tral-point clamped (NPC) inverter, is suitable for high-voltage
and high-power applications. The proposed inverter, when it
is compared with the conventional four-level NPC pulsewidth
modulation inverter, exhibits the following advantages: a) ability
of changing the power losses distribution profile among the de-
vices by selecting a suitable switching strategy; b) reduction of
total inverter power semiconductor device losses; c) ability of
bidirectional operation for all power semiconductor switches; and
d) easy implementation using existing power semiconductor mod-
ules. The effect of conduction and switching losses profiles of the
proposed inverter for different switching strategies is examined
under different loads, power factors, and modulation indices. The
dc-link capacitors voltages are effectively balanced via a proposed Fig. 1. Proposed three-phase four-level inverter.
self-voltage balancing topology, without the need of isolated dc
voltage sources or additional voltage stabilizing circuits. Finally,
the theoretical results are confirmed by simulation and experi-
mental results.
Index Terms—DC-Link capacitor voltage balance, multilevel
voltage source inverter (VSI), semiconductor device power losses,
sinusoidal pulsewidth modulation (SPWM).

I. INTRODUCTION
HE transformerless multilevel inverter topologies have
T gained a great attention during the last two decades owing
to their significant advantages in high-voltage and high-power Fig. 2. Different dc-link arrangements for inverter. (a) The reference point 0
is taken from the common point of the dc sources. (b) The reference point 0 is
applications. The multilevel inverters, when are compared taken from the common connection of capacitors C and C .
with the conventional two-level inverters, exhibit higher output
voltage with the same device ratings, lower harmonic con-
MOS-controller transistors (MCTs), gate turn-off thyristors
tent, and and lower electromagnetic interference (EMI)
(GTOs), e.t.c.] in all positions, thus giving the ability of bidi-
levels [1]–[3]. Also, they draw input current with very low
rectional operation for all power semiconductor switches [4].
distortion content and they can operate with a lower switching
Here, an investigation of influence of switching strategies on
frequency. However, additional power semiconductor devices
the distribution of power losses in the semiconductor devices
are necessary for their implementation. The proposed four-level
of the four-level inverter is accomplished under different loads,
pulsewidth modulation (PWM) inverter (Fig. 1), which can
power factors, and modulation indices. Selecting the suitable
be used in high voltage dc (HVDC) transmission systems, ac
switching strategy a well-distributed losses dissipation among
drives, and renewable energy conversion systems, is a combi-
the devices can be obtained. This ability of having alternative
nation of a conventional two-level inverter and a three-level
switching strategies is an inherent advantage of the proposed
neutral-point clamped (NPC) inverter.
inverter. In addition, for high output power applications with
As it can be seen from Fig. 1, the proposed four-level inverter
high power factors and high modulation indices, the proposed
uses active switches [insulated gate bipolar transistors (IGBTs),
topology exhibits lower total power semiconductor losses than
Manuscript received June 27, 2005; revised February 1, 2006. Recommended the conventional four-level NPC inverter under the same load
for publication by Associate Editor J. Rodriguez. and dc input voltage. The dc-link capacitors voltages are kept
The authors are with the Laboratory of Electrical Machines, Department of
Electrical and Computer Engineering, National Technical University of Athens,
nearly constant under real and reactive power applications
Athens 15773, Greece (e-mail: manias@central.ntua.gr). through the use of a self-voltage balancing topology, as it is
Digital Object Identifier 10.1109/TPEL.2006.886627 described in Section V.
0885-8993/$20.00 © 2006 IEEE
150 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 3. (a), (b) Inverter output phase voltage and its harmonic spectrum respectively for the dc-link arrangement of Fig. 2(a). (c), (d) Inverter output phase voltage
and its harmonic spectrum respectively for the dc-link arrangement of Fig. 2(b).

II. OPERATION presented in Fig. 3. Fig. 3(a) and (b) correspond to dc-link
arrangement of Fig. 2(a), whereas Fig. 3(c) and (d) correspond
Each phase leg of the proposed inverter is composed of eight to dc-link arrangement of Fig. 2(b). The line-to-line voltage
active switches (IGBTs), thus ensuring bidirectional operation. and its harmonic spectrum for dc-link arrangement of Fig. 2(b)
The switches to are used for the implementation of a are given in Fig. 4. The software Simulink/Matlab is used for
conventional three-level NPC inverter, while the switches simulation. The simulation parameters for obtaining Figs. 3
and are used for the implementation of a conventional two- and 4 are: 900 V, 0.8, 39, 50 Hz,
level inverter, where , are the three phases. The dc inductive resistive 5 and 0.8.
input voltage is split into four bulk capacitors – and each Referring to Fig. 3, the following conclusions are extracted:
capacitor is charged to a voltage 4. 1) The magnitude of fundamental inverter phase voltage by
As the proposed inverter has an even number of voltage using the dc-link arrangement of Fig. 2(b) is 13.5% greater than
levels, two different dc-link arrangements are examined in the corresponding value obtained by the dc-link arrangement
order to obtain the inverter reference point 0, as shown in of Fig. 2(a), thus ensuring a better utilization of the dc-link
Fig. 2. The arrangement of Fig. 2(a), which provides an inverter voltage. 2) The inverter phase voltage harmonic spectrum by
output phase waveform of equally-spaced voltage levels, uses using the dc-link arrangement of Fig. 2(b) contains third and
two dc voltage sources 2, three capacitors of the same fifth order harmonics, whereas the line-to line voltage contains
capacitance and the reference point 0 is taken from the common only fifth order harmonic of small value. On the contrary, the
point of the dc sources. The arrangement of Fig. 2(b), which dc-link arrangement of Fig. 2(a) does not contain any low
provides an inverter output phase waveform of non-uniform order harmonics. 3) The harmonic content [total harmonic
voltage steps, uses one dc voltage source , four capacitors distortion (THD)] of the inverter phase voltage by using the
of the same capacitance and the reference point 0 is taken dc-link arrangement of Fig. 2(b) is about 12.7% lower than the
from the common connection of capacitors and . In corresponding value obtained by the dc-link arrangement of
order to decide upon the appropriate dc-link arrangement, the Fig. 2(a). Indeed, these values can be confirmed by referring
inverter output phase voltage and its harmonic spectrum for to Fig. 3(b) and (d). Considering that the advantages of higher
each dc-link arrangement are taken by simulation, which are output voltage and lower THD are more important than the
PERANTZAKIS et al.: NOVEL FOUR-LEVEL VOLTAGE SOURCE INVERTER 151

TABLE I

$
ALTERNATIVE SWITCH COMBINATIONS FOR PHASE LEG A. THE
SYMBOL: “ ” MEANS TRANSITION FROM ONE VOLTAGE
LEVEL TO ANOTHER AND VICE-VERSA

Fig. 5. SPWM implementation of the proposed four-level inverter. Carrier

waves bands and modulation wave for phase a.

Fig. 4. (a) Line-to-line voltage and three phase load currents for the dc-link The modulation method used in the proposed inverter is a car-
arrangement of Fig. 2(b). (b) Harmonic spectrum of line-to-line voltage. rier-based Sinusoidal PWM (SPWM) [5]–[8], which is shown in
Fig. 5. As it can be seen from Fig. 5, the SPWM phase output
disadvantage of appearing low order harmonics, the dc-link voltage results from the comparison of the modulating wave
arrangement of Fig. 2(b) is selected for the proposed inverter. with the three high frequency triangular carrier waves ,
Accordingly, the same dc-link arrangement of Fig. 2(b) for the , and which are contiguous in-phase disposition ar-
conventional four-level NPC inverter is adopted in order to be rangement. The same is valid for the output voltages for phases
comparable the semiconductor power losses between the two and . The three sine modulating waves for phases , , are
types of inverters. phase shifted to each other by 120 and are expressed by
In the proposed inverter (Fig. 1), there is a freedom of
selecting different switching pattern combinations, since active
switches and have been used instead of clamping
diodes. This fact allows different switching strategies for the (1)
proposed inverter to be adopted and consequently different (2)
losses distribution profiles among the semiconductor devices
to be achieved. Table I presents the possible alternative switch
(3)
combinations in order to obtain a particular voltage level. Note
that there exist two combinations for obtaining the voltage where
levels in the upper region 2 4 , four combi- modulation index 1;
nations for obtaining the voltage levels in the middle region frequency ratio 39;
4 4 , and another two combinations for obtaining modulating wave frequency 2
the voltage levels in the lower region 4 2 . From 50 Hz;
these combinations, eighteen different switching strategies are carrier wave frequency 1950 Hz;
obtained and presented in the Appendix.
modulating wave peak-to-peak amplitude;
In some switching strategies, the zero current switching (ZCS)
upper, medium, and lower carrier waves
technique has been used in order to reduce the switching losses.
peak-to-peak amplitudes.
Forexample, theswitch inthefirst switchingstrategyturns-on
during the voltage level 2 under zero current, although it Initially, the modulating wave is compared with the constant
takes part only in obtaining the next voltage level 4. Thus, voltages 1/3 p.u. and 1/3 p.u. (Fig. 5) in order to
reduced switching losses are caused by switch during the determine the voltage level that should be used. When the mod-
voltage transition from level 2 to level 4. As it can ulating wave is compared with the upper trianglular signal, tran-
be seen in the Appendix, the same technique is applied to other sitions between voltage levels ( 2) and ( 4) are ob-
switches for the switching strategies one to four. tained, while when it is compared with the middle and lower tri-
152 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 7. (a) Mean value of devices losses per phase of the proposed four-level
inverter. (b) Devices losses standard deviation per switching strategy.

Fig. 6. Inverter output phase voltage for zero modulation index. (a) For even same power factor. Consequently, the criterion for choosing
number of voltage levels. (b) For odd number of voltage levels.
the appropriate switching strategy is the degree to which the
devices power losses are dispersed around the central mean
value. Here, the standard deviation will be used as a measure of
angles transitions between ( 4), ( 4) and ( 4), dispersion, which is defined as [9]
( 2) are, respectively, obtained.
The proposed inverter, as it is valid for every inverter with even
number of voltage levels, can not output a zero voltage state. As
a result, the inverter output phase voltage for zero modulation (4)
index is a bipolar waveform taking two distinct values 4
and 4 as shown in Fig. 6(a). This bipolar voltage wave- where
form, although it has a zero magnitude of fundamental voltage, it
exhibits high RMS value and considerable harmonic energy con- th device power losses;
centrated at the switching frequency. For example, for: 900 mean value of inverter devices losses;
V, 0.0, 39, the RMS value of bipolar output phase number of inverter semiconductor devices.
voltage is about 225 V. This is a disadvantage of the proposed The standard deviation for each switching strategy has been
inverter, especially when it should output low or zero voltage to found and the results are presented in Fig. 7(b). As it can be
a load, since then its output voltage waveform can not be van- seen from Fig. 7(b), the ninth switching strategy has the lowest
ished. On the contrary, this problem does not exist in inverters standard deviation value and accordingly provides the most uni-
with odd number of voltage levels, since the output phase voltage form losses distribution profile among the inverter devices. For
waveform is reduced to a zero line for zero modulation index, example, for 0.8 and 0.8, the proposed inverter
as shown for example in Fig. 6(b) for a five-level inverter. has a standard deviation value of 8.1 W, while the corresponding
value of the conventional four-level NPC inverter is 18 W, which
is more than twice higher. Therefore, from here on, the ninth
III. POWER LOSSES DISTRIBUTION OF
switching strategy will be used for taking simulation and exper-
THE SWITCHING STRATEGIES
imental results.
As it can be seen from Fig. 7(a), the mean value of the For comparison reasons, the per phase devices losses profiles
semiconductor devices power losses of the proposed inverter of the proposed inverter and the conventional four-level NPC
is nearly constant for all the switching strategies under the inverter are presented in Fig. 8, under the same output power,
PERANTZAKIS et al.: NOVEL FOUR-LEVEL VOLTAGE SOURCE INVERTER 153

Fig. 9. Phase leg of the conventional four-level NPC inverter.

Fig. 8. Losses distribution profiles. (a) For proposed inverter with the ninth
switching strategy. (b) For conventional four-level NPC inverter.
TABLE II
SWITCHING STATES OF THE PROPOSED FOUR-LEVEL
dc-link voltage and modulation index and for different induc- INVERTER FOR THE NINTH SWITCHING STRATEGY
tive-resistive load power factors. As it is recognized, the pro-
posed inverter exhibits a better losses distribution profile than
the conventional four-level NPC inverter. The semiconductor
devices power losses used for deriving the diagrams of Figs. 7
and 8 are obtained by simulation based on parameters:
900 V, impedance of inductive-resistive load: 5.0 ,
0.8, 39, 50 Hz and power factors:
0.2, 0.5, 0.8, 1.0.
Furthermore, referring to Fig. 8(b), about 70% of the total TABLE III
SWITCHING STATES OF THE CONVENTIONAL FOUR-LEVEL NPC INVERTER
device losses of the conventional inverter are exclusively cre-
ated by the devices , , and
, while the remaining amount is created by the de-
vices , , and . This is due to
the fact that the switches 2 to 5 (Fig. 9) conduct during more
than one output voltage levels, while the switches 1 and 6 con-
duct only during the voltage levels 2 and 2, respec-
tively. On the contrary, in the proposed inverter Fig. 8(a) about
35% of total losses are created by the switches and
, while the remaining losses amount is nearly uni- In four-level inverters there are three voltage regions, which
formly distributed among the rest of the devices. are defined by the adjacent output voltage levels. That is, the
regions 1–3 are located between the voltage levels 2 and
4, 4 and 4, 4 and 2, respectively.
IV. INVERTER LOSSES
Using Fig. 10, the switch duty ratio for each region and voltage
In multilevel inverters, unlike two-level inverters, the losses level can be calculated and the results are summarized in
of each semiconductor device is different from one another and Table IV.
depends on the duty ratio of the device, the number of output The conduction and switching losses are initially calculated
voltage levels, the load power factor, and the depth of modula- analytically and then verified by simulation results. For power
tion index [10]–[13]. The switching states of the proposed and losses calculation, the static characteristics of the inverter semi-
conventional four-level NPC inverters are presented in Tables II conductor devices are considered and the current is assumed to
and III, respectively. The switching states of the conventional be sinusoidal, which is an accepted approximation when the fre-
four-level NPC inverter are referred to in Fig. 9. quency ratio is greater than 15 (here is 39) [10]. The
154 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

the angles that define the beginning and the

end of an interval with conduction losses;
the angles that define the beginning and the
end of an interval with switching losses;
the device blocking voltage;
the total dc-bus voltage;
the duty ratio of the SPWM output phase
voltage;
the maximum load current;
the threshold voltage and the dynamic
resistance of the device, respectively;
the inverter switching period and the
turn-on-and turn-off times of the device,
respectively;
2 ;
the load power factor angle.
The duty ratio of each conducting device depends on the
values of the load power factor, the modulation index and the
output voltage level. Fig. 11 shows an example of how to deter-
mine the conducting devices losses in relation to fundamental
Fig. 10. Switch duty ratio determination for each voltage level. output phase voltage and load current for 0.2 and
0.6. Similar diagrams are constructed for each load power factor
TABLE IV
and modulation index separately, in order to determine the con-
SWITCH DUTY RATIOS FOR EACH VOLTAGE LEVEL AND REGION ducting devices and their corresponding duty ratios.

V. DC-LINK CAPACITORS SELF VOLTAGE

BALANCING TOPOLOGY

The dc-link capacitors voltages balancing problem can be

successfully solved in multilevel inverters by using a gener-
alized multilevel inverter topology as described in [15], [16].
For the proposed inverter an efficient self-voltage balancing
topology is proposed, which can balance by itself the voltages
of the dc-link capacitors regardless of the load characteristics.
The proposed self-voltage balancing topology is composed of
eight clamping switches to and three auxiliary capac-
itors to and it is shown in Fig. 12. Referring to Fig. 12,
the switches to are the main power switches for phase
, while the clamping switches to are necessary to
connect the auxiliary capacitors – parallel to the dc-link
capacitors – during different switching states.
Where D is the duty ratio for region 1 and voltage level +V =2. When the output voltage level is 2, the clamping
switches , , , and should be on, connecting
average conduction and switching losses of a
the capacitors and , and , and in parallel
device are calculated using the following equations [10], [14]:
and voltage balance between the corresponding capacitors is
obtained, , , and . When the
(5) output voltage level is 4, the clamping switches ,
, , and should be on, connecting the capacitors
and , and , and in parallel and consequently
the voltage balance between the corresponding capacitors is
(6) ensured, , and . As a result,
when the output voltage level is changed from 2 to 4
where
and vice-versa, a voltage balance between the dc-link capac-
itors , , and is obtained because it holds ,
the fundamental load current (7) , and . Similarly, the dc-link capacitors
the fundamental voltages balance is maintained during the voltage transitions
output phase voltage (8) from 4 to 4, 4 to 2 and vice-versa. The
PERANTZAKIS et al.: NOVEL FOUR-LEVEL VOLTAGE SOURCE INVERTER 155

Fig. 11. Conducting devices for one fundamental period with m = 0.6 and cos' = 0.2.

Fig. 12. Phase a of the proposed inverter including the dc-link capacitors self-voltage balancing circuit.

switching states of the main and clamping switches (Fig. 12) switches turn on or turn off once in one period (Table V), the
for each output voltage level are presented in Table V. dc-link capacitors voltages can be balanced regardless of the
In the proposed self-voltage balancing circuit, the auxiliary load characteristics [16]. Thus, using the proposed self-voltage
capacitors are connected in parallel with different dc-link ca- balancing topology, the inverter is suitable for supplying power
pacitors during different switching states. Since the clamping under nearly constant dc-link capacitors voltages.
156 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 13. Output phase voltage v , load current and dc-link capacitors voltages +V =2, +V =4, 0V =4, 0V =2. (a), (b) and (c), (d) waveforms taken with
and without the voltage balancing topology respectively.

TABLE V recognized that without the balancing circuit the voltage levels
SWITCHING STATES OF MAIN AND CLAMPING SWITCHES 2 and 2 exhibit a constant ripple, while the voltage
FOR EACH OUTPUT VOLTAGE LEVEL
levels 4 and 4 exhibit not only a constant ripple but
also they converge to zero with time. On the contrary, as shown
in Fig. 13(a) and (b), with the balancing circuit all the voltage
levels are kept nearly constant. Thus, it is concluded that the
proposed self-voltage balancing circuit effectively balances the
voltages of the dc-link capacitors. The simulation parameters
for taking Fig. 13 are: 400 V, 0.8, 39,
50 Hz, 2 mF, 1 mF,
20 and 15 mH.

VI. SIMULATION, THEORETICAL AND EXPERIMENTAL RESULTS

A. Simulation and Theoretical Results of Devices Losses
The power semiconductor losses of the proposed inverter
have been calculated by considering constant inductive-resis-
tive load under different power factors (0.0, 0.2, 0.5, 0.8, and
1.0), while the modulation index is changed from 0.1 to 1.0.
The balancing effect of the proposed self-voltage balancing The working parameters are listed in Table VI.
circuit is confirmed by simulation results, which are presented The theoretical and simulation results of power losses for
in Fig. 13 for inductive-resistive load. Fig. 13(a) and (b) and semiconductor devices , , and
Fig. 13(c) and (d) have been extracted with and without the bal- (as a sample) of the proposed inverter are presented in Fig. 14
ancing circuit, respectively. Referring to Fig. 13(c) and (d), it is [4]. As it can be seen, the theoretical results are in good
PERANTZAKIS et al.: NOVEL FOUR-LEVEL VOLTAGE SOURCE INVERTER 157

TABLE VI
WORKING PARAMETERS FOR THEORETICAL AND SIMULATION RESULTS

Fig. 15. Comparison of total losses between the proposed and conventional
NPC inverter. The measurements were taken by varying the modulation index
and power factor under constant inductive-resistive load.

S
Fig. 14. Power losses of the devices ( + D S
), ( +D ), (S + D )
of the proposed inverter. (a) Simulation results. (b) Theoretical results.
The inductive-resistive load remains constant, while the modulation index
and the power factor are varied.

agreement with the simulation results and thus the losses

calculation method used for the proposed multilevel inverter
is verified. From the results it is concluded that: a) for power
factors from 0.0 to 0.8 and modulation index smaller than 0.6, Fig. 16. Total power losses for different inductive-resistive loads and power
factors with constant modulation index. (a) For the conventional four-level NPC
the devices losses increase with increasing the modulation inverter. (b) For the proposed four-level inverter.
index, while it is independent from the power factor value;
b) for modulation index greater than 0.6 the losses vary from
device to device and are dependent on the power factor value;
B. Simulation and Experimental Results of Output Waveforms
and c) for unity power factor and modulation index smaller
than 0.4, the power losses remain nearly constant and for The operation of the proposed inverter is confirmed by a
modulation index greater than 0.4, the power losses increase single phase laboratory prototype unit. The proposed inverter
as the modulation index increases. was implemented using IGBTs type HGTG10N120BND,
A comparison of the total devices losses between the pro- dc-bus voltage of 400 V, 0.8, 39, 50 Hz, in-
posed and the conventional four-level NPC inverter for constant ductive-resistive load with 160 and power factor 0.9.
inductive-resistive load and different power factors and modu- The simulation results of the proposed inverter are presented in
lation indices is presented in Fig. 15. As it can be seen from Figs. 3 and 4. Fig. 3(c) and (d) show the output phase voltage
Fig. 15, for 0.5 the proposed inverter exhibits up to 13% and its harmonic spectrum respectively, whereas the line-to-line
greater total losses than the conventional NPC inverter, while voltage and its harmonic spectrum are presented in Fig. 4(a) and
for 0.5 the proposed inverter exhibits up to 30% (for (b), respectively. As it was expected, the harmonics are centred
1.0 and 1.0) lower total losses than the conven- around the switching frequency, the triple harmonics have
tional NPC inverter. The same conclusions are resulted when a disappeared and there is only a fifth order harmonic of small
comparison of total devices losses of both inverter types is made value in the line-to-line spectrum. In the case of equally-spaced
for different loads and power factors (Fig. 16). So, under load voltage levels Fig. 2(a), the peak value of the line-to-line output
with high power factors and high modulation indices, the pro- voltage of the fundamental component is given by
posed inverter exhibits a better efficiency than the conventional
NPC four-level inverter. (9)
158 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

TABLE VII
SWITCHING STRATEGIES

Where x: a, b, c the three phases. The indices: “u,” “m,” and “l” means upper,
middle and lower carrier band, respectively.
Fig. 17. Experimental results of the proposed four-level inverter. (a) Output
phase voltage. (b) Load current.
two-level and a conventional three-level NPC inverter. The suit-
able switching strategy for the proposed inverter was selected,
which ensures the most uniform power losses distribution pro-
file among the inverter semiconductor devices, under different
loads, power factors, and modulation indices. It was found that
the proposed inverter had a better losses distribution profile
with respect to the conventional four-level NPC inverter. For
high output power with high power factors and modulation
indices, the proposed inverter exhibited up to 30% lower total
devices losses than the conventional NPC inverter. For low
output power with low power factors and modulation indices
the proposed inverter exhibited up to 13% greater total devices
losses than the conventional NPC inverter. Consequently, the
proposed topology is more efficient than the conventional
NPC inverter for supplying high output power and loads with
high power factors and modulation indices. However, the
proposed inverter has the disadvantage of using two additional
active switches per phase. Moreover, a self-voltage balancing
topology was proposed, which effectively balanced the dc-link
capacitors voltages. Finally, the theoretical results were in good
Fig. 18. Experimental results for IGBT S . (a) Blocking voltage. (b) Collector agreement with the simulation and experimental results.
current.

APPENDIX
As it is explained in Section II, the magnitude of the funda-
mental line-to-line voltage of the proposed inverter is 13.5% See Table VII.
higher than that given by (9). Indeed, this fact can be confirmed
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Elect. Eng., vol. 144, no. 5, pp. 235–239, Sep. 1994. engineering form Concordia University, Montreal,
[12] L. K. Mestha and P. D. Evans, “Analysis of on-state losses in PWM QC, Canada, in 1975, 1980, and 1984, respectively.
inverters,” Proc. Inst. Elect. Eng. B, vol. 136, no. 4, pp. 189–195, Jul. In 1975, he joined the Canadian Broadcasting Cor-
1989. poration (CBC) where he was responsible for the de-
[13] J. W. Kolar, H. Ertl, and F. C. Zach, “Influence of the modulation sign of radio and television automation systems. In
method on the conduction and switching losses of a PWM converter 1989, he joined the Electrical and Computer Engi-
system,” IEEE Trans. Ind. Appl., vol. 27, no. 6, pp. 1057–1063, Nov./ neering Department, National Technical University
Dec. 1991. of Athens (NTUA), Athens, Greece, and today he is
[14] A. M. Hava, R. J. Kerkman, and T. A. Lipo, “Simple analytical and a FullPprofessor teaching and conducting research in
graphical methods for carrier-based PWM-VSI drives,” IEEE Trans. the area of power electronics and motor drive systems. He is the author of more
Power Electron., vol. 14, no. 1, pp. 49–61, Jan. 1999. than 60 IEEE and IEE publications in Power Electronics and Motor Drive Sys-
[15] F. Z. Peng, “A generalized multilevel inverter topology with self tems.
voltage balancing,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. Dr. Manias is the Chapter Chairman and Founder of the IEEE Greece Section
611–618, Mar./Apr. 2001. IAS-PELS-IES, a member of the IEEE Motor Drives Committee, and a Regis-
[16] A. Chen and X. He, “A hybrid clamped multilevel inverter topology tered Professional Engineer in Canada and Europe.
with neutral point voltage balancing ability,” in Proc. PESC’04 Conf.,
Aachen, Germany, 2004, pp. 3952–3956.

George S. Perantzakis (M’05) was born in Volos,

Greece, in 1954. He received the diploma degree
in electrical engineering from Aristotle University
of Thessaloniki, Thessaloniki, Greece, in 1981 and
the M.Sc. degree in production and management
of energy from National Technical University of
Athens (NTUA), Athens, Greece, in 2002 where he
is currently pursuing the Ph.D. degree.
From 1982 to 1986, he was a Supervisor Engi-
neer with the Engineering Department, Greek car
assembly factory TEOKAP, where he was involved
with the design of automation systems for production lines. Since 1990, he has
been a Lecturer with the Department of Electrical Engineering, Technological
Education Institute of Lamia (TEI), Lamia, Greece. His research interests are
in the area of power electronics, motor drives, and control techniques.