Efficient Global Optimization of Analog Circuits Using Predictive Response Surface Models On Discretized Design Space

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/MDAT.2016.2580667, IEEE Design
and Test
Efficient Global Optimization of Analog Circuits using Predictive

Response Surface Models on Discretized Design Space
Jiho Lee1 and Jaeha Kim1
1
Department of Electrical Engineering and Computer Science, Seoul National University, South Korea
Abstract─ An efficient global optimization method is presented. Typically, simulation-based optimizers

have long execution time due to the large number of simulations required during the optimization process.
This paper tries to reduce the simulation number with two existing techniques: first, discretizing the
continuous design space with respect to the variability-induced correlation, making total number of design
candidate to be finite; second, performing simulation for only the best design candidates determined based
on response surface models (RSMs) on stochastic circuit performance. For more efficient searching,
extrapolative RSM and a heuristic for finding best candidate are also introduced. The RSM-based searching
is demonstrated to significantly enhance the scalability of discrete, gradient-based searching. Also, it shows
2x~3x reduction in the number of simulations for the optimization of a standard two-stage operational
amplifier, a voltage-controlled LC oscillator and a differential voltage-controlled ring oscillator compared
to the genetic algorithm.
I. Introduction
Analog circuit optimization tools aim to find the optimum set of design parameters that maximizes the
circuit’s performance while satisfying the constraints. Among the various approaches presented in literature
[1], [2], the simulation-based approaches present the least burden on the circuit designers since the tool
finds the optimum parameters by iteratively running the circuit simulations that the designers would have
to run themselves. However, the downside is long execution time, since typically hundreds to even
thousands of simulations may be required before finding the optimal design [3]-[5]. The situation gets even
worse for larger designs as the number of design parameters gets larger and each simulation run takes longer.
In order to reduce the number of simulations required, two key methods are necessary: a method that can
predict the outcome before running simulation and choose the next design candidate resulting in the better
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/MDAT.2016.2580667, IEEE Design
and Test
performance than the candidate solutions found in the prior iterations, and a method that can determine
when to stop the search. In fact, many problems found with the previous simulation-based optimization
algorithms can be traced down to lacking efficiency in one of these two aspects. That is, the algorithm may
waste time while simulating designs that are no better than the designs already found and keep searching
without knowing whether a better design will ever be found.
This paper presents an efficient global optimization tool for analog circuits addressing these two problems.
First, the predictive response surface models (RSMs) help pick the design candidate that is most likely to
improve the current circuit’s performance. Second, the design space discretization based on the correlations
between the neighboring design candidates due to the underlying variability in process, voltage, temperature
(PVT), and devices makes it easy to determine that the search process is complete.
Response surface models (RSMs) are commonly used to predict the outcomes of the simulation and bypass
unnecessary simulations during the optimization process [6]-[11]. That is, if the RSM predicts that a certain
design candidate is not likely to yield a better performance than the currently-known optimum (called
hitherto optimum), then one can discard that design before running the actual simulation, saving the
simulation cost. Therefore, it is important that the RSM makes an accurate prediction based on the
observations made during prior iterations. RSMs used for the purpose of circuit optimization include linear
and quadratic models [6], [7], convex models such as posynomial and signomial models [7], [8], and kernel
based models such as the radial basis interpolation (RBF) model [9] and Kriging model [10], [11]. To use
RSM’s predictions in choosing the next design candidate to simulate, it is often necessary to know how
reliable the prediction is. For instance, the prediction on the design close to the previously-simulated designs
is likely to be more accurate than the one on the design far away from them assuming that the simulation
response is smooth and continuous across the design space. This reliability information along with the
prediction can help the optimizer determine the probability of a given design candidate satisfying the
constraints and yielding the better performance than the hitherto optimum. This work adopts the stochastic
Kriging model [12] to describe the probabilistic distribution of the circuit performance of each design
candidate due to variability and combines it with the radial basis function (RBF) interpolation model [13]
in order to add an extrapolation capability for better performance prediction.
It is noteworthy that by performing this RSM-based circuit optimization on a discretized design space, one
can realize a powerful variability-aware, global optimization tool for analog circuits. In other words, one
can find the globally optimal design yielding the best performance in the presence of PVT variation and
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device mismatch with a small number of simulation runs. It has been demonstrated in [14] that the
variabilities present in ICs introduce strong correlations between the similar designs. That is, the
performance characteristics can change only smoothly over the design parameter space and the sampling
theorem implies that one can fully explore the continuous design space by probing only a finite number of
discrete samples. Its significance lies in the fact that the number of design candidates to be considered is
now finite, enabling a global search. For instance, even a brute-force method of evaluating all the design
candidates can find the global optimum in finite time. The later sections of this paper will describe how this
property helps an RSM-based optimizer choose the design candidate that is most likely to yield the
improved performance and determine when the search process is complete. The RSM-based approach also
complements the weakness of the discrete optimization approaches: dimensionality scaling. Despite various
efforts made in [15], the local optimization method used with a discretized design space had a serious
scalability issue that the number of design candidates to evaluate increases exponentially with the number
of design parameters. The global optimization method based on the RSM predictions can greatly improve
this scaling to a sub-linear dependence as discussed in Section III.
The rest of this paper is organized as follows. Section II describes the overall flow of the proposed
variability-aware global circuit optimization algorithm, with an emphasis on the adopted RSMs and the
criteria of choosing the next design candidate to simulate and terminating the search based on its predictions.
Then, Section III will discuss the experimental results of the presented algorithm on the examples of a two-
stage operational amplifier, demonstrating the effectiveness of performing an RSM-guided global search
on a discretized design space. Finally, Section IV concludes this paper.
II. Variability-Aware, Global Optimization Algorithm using Response Surface Models and
Discretized Design Space
Fig. 1 illustrates the overall flow of the proposed variability-aware global optimization algorithm. The basic
flow is similar to the one described in [16], except that the presented algorithm actively utilizes a discretized
design space and performs variability-aware optimization with a modified stochastic Kriging model for
improved extrapolation capability. First, the design space is discretized into a finite set of design candidate
points based on the variability of the PVT condition and device characteristics. Among them, the first set
of pilot design points are randomly selected and simulated to construct the initial RSM. The RSM estimates
the mean and standard deviation of the performance distribution of each design candidate point due to
variability, along with the measures that indicate how reliable each prediction is. Based on this information,
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the algorithm calculates the expected improvement (EI) and expected feasibility (EF) for each design
candidate, indicating how much the design candidate can improve the hitherto optimum and how likely it
is to satisfy the constraints, respectively. Among the unevaluated design candidates meeting the minimum
EF, the algorithm selects the one with the highest EI and evaluates the distributions of its performance
metrics via Monte-Carlo circuit simulation. If the new design candidate evaluated indeed achieves the better
performance than the hitherto optimum, the hitherto optimum is updated. Also, the RSM is updated to
reflect the new simulation results obtained. The algorithm terminates when the highest EI among the
remaining candidates is below a certain threshold, as it implies that the chance of discovering a better design
than the hitherto optimum is sufficiently low. Note that each iteration involves finding the design candidate
with the highest EI, which is by itself a challenging global optimization problem. The fact that the design
candidates are chosen to be on an isotropic, discretized grid called Polka-dot [15] greatly simplifies this
task as discussed in Section II.D. The following sub-sections explain each of these steps in more detail.
A. Design Space Discretization and Initial Pilot Sampling
As mentioned earlier, the presented algorithm starts by discretizing the design space and finds the optimum
design from the resulting finite set of design candidates. A multi-dimensional design space of an analog
circuit is discretized into a set of points on an isotropic grid called Polka-dot, which has some favorable
properties compared to a classical Cartesian grid such as uniform distances between the nearest neighbors
on the grid and the uniform angle of 60 spanned by the two adjacent vectors originating from a given point.
Also, the number of nearest neighbors scales mildly as N(N+1) with the dimension N, instead of aN.
The resolution of the grid, i.e., the spacing between the two neighboring points is determined by the
variability of the circuit being considered. This is based on the observation [14] that the variability in the
global PVT conditions as well as local device characteristics effectively smoothes out the circuit’s response
with respect to the design parameter changes, making the circuit’s performance characteristics change only
smoothly across the design space. In other words, in the presence of variability, two designs are hardly
distinguishable from each other unless their design parameters are sufficiently different. It implies that one
can fully explore a continuous design space by evaluating only a finite set of design points leveraging this
spatial correlation among the adjacent design points.
Fig. 2 illustrates this smoothness or equivalently the correlation induced by the variability of the circuit,
using the example of the phase noise characteristic of a voltage-controlled LC oscillator simulated as a
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function of the active transistor size and passive inductor size. Note that without variability, the phase noise
does not vary smoothly with these parameters. However, when the variability in the global PVT condition
and local device characteristics is introduced, the phase noise becomes a very smooth function of the same
parameters. In other words, it is very easy to predict the phase noise performance of a certain design point
via interpolation if the phase noises of its neighboring designs are known. Through some initial pilot
simulations, the presented algorithm determines the grid spacing so that the neighboring design candidates
have the correlation coefficient of at least 0.5. As the performance of the presented optimization algorithm
has a rather weak dependence on the grid spacing, the authors did not find it necessary to adopt a non-
uniform discretization scheme.
After discretizing the design space, a set of initial pilot design points are randomly selected from the grid
and evaluated via circuit-level simulation. To ensure a uniform distribution of these pilot points across the
design space, the Latin-hypercube sampling (LHS) [16] is used in this work. The simulation results obtained
from these initial pilot points serve as the basis for constructing the first RSMs, as explained next.
B. Response Surface Models (RSMs) for Predicting Circuit Performance Distribution
The RSM adopted in this work serves two purposes: first, estimating the statistical distribution of the
performance characteristic P(x) of a given design candidate x and second, indicating the reliability of this
estimate. Specifically, the RSM estimates the mean μ0(x) and standard deviation σ0(x) of the P(x)’s
statistical distribution and also computes mean-squared errors (MSEs) of these estimates, εμ(x) and εσ(x),
respectively. In other words, it is assumed that the true mean μ(x) and true standard deviation σ(x) of the
P(x)’s distribution take Gaussian distributions: μ(x) ~ N(μ0(x), εμ(x)) and σ(x) ~ N(σ0(x), εσ(x)).
The estimate on the mean μ0(x) is based on a stochastic Kriging model [12], augmented by a multi-quadric
radial basis function (RBF) model [13] for improved extrapolation capability as listed in EQ 1. EQ 1 has
two terms: the first term predicts the global trend and the second term predicts the local deviation from this
global trend, where  MQ denotes the multiquadric basis function and 𝛽 𝑇 (𝐱) denotes the correlation of the
design x with the previously-evaluated designs xi's . Y denotes sample means of circuit performances on
designs evaluated with simulation. The coefficients  i's and βT(x) are obtained by minimizing the mean-
squared error of a linear estimator with the unbiasedness constraint [16].
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K
 K

 0(x)     i MQ( x - xi )   T (x)  Y     i MQ( x - xi )   (EQ 1)
i 1  i 1 
The mean estimate model in EQ 1 adopts a multi-quadric RBF model for the global trend term instead of
the more commonly-used constant trend. By doing so, the RSM can provide the better predictions on the
design candidates that are outside the explored regions via extrapolation. Fig 3 compares the cases of using
a multi-quadric RBF model and using a constant model for the global trend term. For the regions far from
the evaluated points, the multi-quadric RBF model makes better predictions via extrapolation while the
constant model simply gives the overall average as the prediction.
The mean-squared error (MSE) of the estimator can indicate how reliable it is. This MSE becomes smaller
as the correlations between the design x and previously-evaluated designs xi’s get stronger, i.e., as x gets
close to xi’s. On the other hand, the MSE gets larger as the correlations get weaker, or equivalently, the
distances increase. This property makes the MSE a suitable measure for the reliability of the estimate:
 (x)  MSE[  0(x)] (EQ 2)
The estimate on the standard deviation or σ0(x) and its MSE εσ(x) are obtained using the simple Kriging
model [18]. Since extrapolation could yield a negative value for σ0(x) which is not valid, a constant trend
model is used unlike the case for mean estimation. Also, assuming that the noise in the sample standard
deviation is negligible, the regularization is not included in the RSM formulation for standard deviation.
C. Expected Improvement and Expected Feasibility Metrics
As previously noted, the proposed global optimization algorithm evaluates candidate designs based on two
measures: the expected improvement metric (EI) and expected feasibility metric (EF). Both of these
measures are calculated based on the RSMs described in the previous subsection.
First, EI predicts the improvement that the performance on a design x would make, compared to Popt which
is the mean value of the performance on hitherto optimum design. EQ 3 shows the definition for the case
when optimization objective needs to be maximized.
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EI(x) = E[max(P(x) - Popt , 0)] (EQ 3)
This EI metric may behave differently with the MSEs εμ(x) and εσ(x), depending on whether μ0(x) is higher
or lower than Popt. If μ0(x) is higher than 𝑃𝑜𝑝𝑡 , the larger MSEs make the EI value higher, motivating the
optimizer to select the design candidate in the less explored area first when the new design candidates are
likely to improve the hitherto optimum. On the other hand, if μ0(x) is lower than 𝑃𝑜𝑝𝑡 , the larger MSEs
make the EI value lower, motivating the optimizer to refine search near the hitherto optimum when no other
design candidates are likely to yield the better performance. This behavior will be discussed again in Section
III.
On the other hand, the EF metric predicts the probability of a design satisfying the constraints. For example,
EQ 4 calculates EF as the expected probability of P(x) being larger than a specified threshold, θconst:
EF(x)  E[prob(P(x)   const )] (EQ 4)
Similar to the case with EI, this EF metric behaves differently with the MSEs, depending on whether μ0(x)
is greater than θconst or not. If μ0(x) is greater than θconst, the EF metric decreases with the increasing MSEs,
guiding the optimizer to select the design that meets the constraints more conservatively. On the other hand,
if μ0(x) is lower than θconst, the EF metric increases with the increasing MSEs, making the optimizer to
search more aggressively when no feasible designs are found.
D. Candidate Design Selection and Termination Criteria
At each iteration step, the optimizer selects the best design candidate that is most likely to improve the
hitherto optimum or the design candidate that explores the remaining part of the design space to terminate
the search, based on the EI and EF metrics described in the previous subsection. That is, among the design
candidates that meet the minimum EF value, the one with the largest EI value is selected for simulation.
The new simulation results obtained from the selected candidate may then update the hitherto optimum or
the RSM, resulting in the better estimates on the EI and EF values for the remaining candidates. The search
process continues until the largest EI of the remaining candidates is below a certain threshold, implying
that the chance of finding a better design than the hitherto optimum is low enough.
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Although the EI and EF metrics for a given design candidate x can be computed easily using the described
RSMs, namely, using the mean and standard deviation estimates μ0(x) and σ0(x) and their MSEs εμ(x) and
εσ(x), finding the design candidate with the largest EI is still a challenge as it is a global optimization
problem of a non-convex function. To address this, the previous works adopting the similar global search
algorithms guided by Kriging models used branch-and-bound heuristic [16] or stochastic searching [11].
However, the stochastic natures of these algorithms could not guarantee the deterministic convergence to
the global optimum.
This work employs a heuristic that performs a set of local searches each starting from the vicinity of the
previously-evaluated design points and selecting the best solution among them. This heuristic is based on
the postulation that the RBF and Kriging models have at most one local optimum in the region between
two adjacent data points. Fig 4(a) and (b) show the contour plots of an example of estimated mean function
and its MSE, illustrating the validity of this postulation. This postulation is further extended to EI(𝐱) and
EF(𝐱). Fig 4(c) shows the contour plot of the expected improvement, derived from Fig 4(a), (b), and the
standard deviation estimate (not shown in the figure).
Fig 4(c) demonstrates that the proposed heuristic actually finds the global optimum of EI(𝐱). There are four
local maxima on EI, located on the regions where estimation uncertainty is high or the local optima of the
mean estimate is located. With the local gradient searching starting from the neighboring points (empty
circle) of the data points (full circle), all of the four maxima can be found.
III. Experimental Results
The proposed algorithm reduces the number of evaluations required that increases super-quadratically with
the gradient-based search in [15] to the one that increases sub-linearly, as the dimension of the design space
increases. Fig 5 plots that the average number of function evaluations required in finding the optimum of
the log cosine hyperbolic test function in EQ 5 as the dimension N increases. The improved efficiency of
the proposed global search algorithm is due to the fact that the gradient-based local search algorithm has to
progress through the nearest neighbors of the hitherto optimum, while the proposed RSM-based global
search algorithm evaluates only the best candidate among entire searching space.
1
log cosh(𝑥) = ∑𝑁 𝒙𝒊
𝑖=1 log (2 (𝑒 + 𝑒
−𝒙𝒊 ))
(EQ 5)
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Fig. 7 also compares the number of circuit simulations required by the proposed algorithm with that by a
genetic algorithm [5] on examples of sizing a two-stage CMOS operational amplifier, a voltage-controlled
LC oscillator and a differential voltage-controlled ring oscillator in Fig. 6, with formulations of design
optimization listed in Table 1 – Table 3.
The op-amp (Fig. 6(a)) contains 10 independent design variables and measures 10 performance metrics as
listed in Table 1. The objective is to maximize the unity-gain bandwidth while satisfying constraints on the
other performance metrics. For the LC-VCO (Fig. 6(b)), 3 performance metrics are measured for 6
independent design variables, as listed in Table 2. A PMOS transistor of fixed size is used as the constant
current source for biasing. The optimization objective is to minimize the phase-noise at 1MHz offset from
center oscillation frequency, with respect to the constraints on the startup criterion and the tuning range.
The ring-VCO (Fig. 6(c)) has 3 independent design variables and 4 performance metrics are measured,
where the jitter in differential output is to be minimized with constraints on the tuning range and power
consumption as listed in Table 3. The yield target for constraint performances is set to 60% for experiments.
The number of simulations performed by the proposed algorithm is 2~3x less than that by the genetic
algorithm, for reaching the nearly equivalent solution. Fig. 7 shows the trade-offs between the simulation
cost and optimality of the solution for the proposed algorithm and genetic algorithm, where the assumed
algorithm parameters are listed in Table 4 for the three example circuits. The simulation cost and
optimization result are average values of repeated executions under each condition of algorithm parameters
Fig 8 and 9 show the actual designs simulated during the sample optimization process of both the algorithms
of the op-amp, projected on a few selected design variables for visualization. In Fig 9, it is observed that
the genetic algorithm runs a considerable amount of simulations on similar designs since it continues
searching until it observes convergence. In contrast, the proposed optimizer terminates when the maximum
EI of the unevaluated designs falls below a certain threshold, avoiding such a waste of repeatedly simulating
similar designs.
Fig. 10 illustrates how the proposed optimization algorithm works in practice, where each plot shows the
progression of the maximum EI value and the mean estimates of the unity-gain bandwidth, respectively.
The optimization process consists largely of three phases. In the first phase, a feasible region is identified
guided by the EF metric even when none of the initial pilot samples are feasible. In the second phase, the
optimizer continually improves the hitherto optimum by selecting the most promising candidate and
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exploring new spaces. In this phase, the hitherto optimum improves but the EI metric gradually decreases.
In the third phase, the EI metric is low for most remaining candidate and the optimizer selects designs that
can reduce the MSEs of the estimates. Finally, the optimization terminates when the maximum EI becomes
lower than the threshold.
IV. Conclusion
An efficient variability-aware global optimization method for analog circuits is presented. The use of RSM-
based global search and discretized design space significantly reduced the total number of simulations
required. Along with this, an extrapolative stochastic Kriging method and a novel heuristic method for
finding the global optimum of the RSM function are described. The proposed method can also be applied
to other optimization problems in engineering, where the objective performance has variability-induced
smoothness and saving the simulation cost is important.
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Discretize Design Space
Select and Evaluate Pilot Samples
Construct Response Surface
Find Candidate with Max. Enhancement

and Enough Feasibility are Expected
No
Evaluate
Max. Enhancement < S0 ?
New Candidate
Yes
Global Solution Found
Fig. 1. Overall flow of global optimization algorithm
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(a)
(b)
(c)
Fig. 2. The contour plots of an LC-VCO’s phase noise performances, which are functions of the
width of cross-coupled NMOS transistor and the radius of the spiral inductor. (a) The
surface roughness exists in TT-corner, being smoothed out in mean performance as (b) due
to performance variation. It justifies discretizing design space and using RSM as (c).
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Fig. 3. For bowl-shaped functions, using extrapolative trend function provides better
approximation than using flat trend.
Fig. 4. Contour plots of estimator of mean function (a), estimation uncertainty (b), expxected
improvement (c) on 2-D design space. All of the local maxima of expected improrment are
found by gradient-ascent searches starting from neighborhood points of data points.
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Fig. 5. Comparison between gradient-based searching and RSM-based searching on discretized

searching space.
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(a)
(b)
(c)
Fig. 6. The circuit schematics of optimization examples. (a) A two-stage operational amplifier (b)
an LC-tank voltage-controlled oscillator and (c) a 5-stage differential voltage-controlled
ring oscillator.
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(a)
(b)
(c)
Fig. 7. The trade-offs between optimized performance and the simulation numbers of the proposed
optimizer and genetic algorithm for optimization problems of (a) the op-amp, (b) the LC-
VCO and (c) the ring-VCO in Fig. 6.
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Fig. 8. The simulated design points during optimization process of op-amp with proposed
algorithm (projected on W1, W5 and W6). The circles indicate design points marked as
optimum during optimization process. Red dots represent initial probing designs.
Fig. 9. The simulated design points during optimization process of op-amp with GA (projected
on W1, W5). The similar design points are repeatedly simulated as GA converges to finish.
Red dots represent initial probing designs.
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(a)
(b)
Fig. 10. The profile of a sample optimization process for the op-amp. (a) Maximum expected
improvement, (b) objective performance (bandwidth).
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Table 1. The design space and performance requirements for optimization problem of the op-amp.
Design Searching Range
Performance metric Specification.
Variable (Min, Max) / Step
W1 [] (100, 700) / 150 Power [𝛍W] < 300
W3 [] (100, 700) / 150 IRN [nV/√𝑯𝒛 ] < 1.0
W5 [] (100, 700) / 150 DC gain [dB] > 30
W6 [] (300, 900) / 150 Phase Margin [º] > 40
W8 [] (10, 250) / 50 Gain Margin [dB] > 10
L1 [] (2, 10) / 2 CMRR [dB] > 30
L3 [] (2, 10) / 2 nPSRR [dB] > 30
L5 [] (2, 10) / 2 pPSRR [dB] > 30
L6 [] (2, 10) / 2 Slew rate [V/𝛍s] > 40
Cc[fF] (5, 50) / 5 Unity-Gain BW [GHz] Maximize
Table 2. The design space and performance requirements for optimization problem of the LC-
VCO.
Design Searching range
WP + WN [] (8, 16) / 2 FMIN [GHz] <5
WP / WN (30, 70) / 5 FMAX [GHz] >6
MCAP (80, 120) / 5 Startup criterion >2
R [um] (45 , 85) / 5 Phase noise @ 10MHz offset [dBc] Minimize
W [um] (7.5, 12.5) / 0.5
S [um] (2, 4) / 0.5
Table 3. The design space and performance requirements for optimization problem of the ring-
VCO
Design Searching range
WRN [] (20, 80) / 5 Power [mW] <1
WRP / WRN (1, 3) / 0.2 FMIN [GHz] < 0.5
WBIAS / WRN (2, 8) / 0.5 FMAX [GHz] > 1.5
Jitter [ps] Minimize
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Table 4. Experiment conditions for comparing proposed optimizer with GA. The algorithms
parameters are initial probe numbers (IP), termination threshold (TH) for proposed
algorithm and maximum generation number (MG), population number (POP) for GA.
Circuit Example Optimization Method Algorithm Parameters
Proposed one IP = 25, TH = {1e7, 5e7, 1e8, 5e8}
Op-amp
Genetic Algorithm MG = 10, POP = {10, 20, 30, 40, 50}
Proposed one IP = 20, TH= {20, 15, 10, 5, 4}
LC-VCO
Genetic Algorithm MG =10 , POP = {5, 10, 15, 20}
Proposed one IP = 20, TH = {20, 10, 5}
Ring VCO
Genetic Algorithm MG = 10, POP = {15, 20, 25}
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and Test
Biography
Jiho Lee is currently working toward a PhD in electrical engineering at Seoul National University, Seoul,
Korea. His research interests include design optimization of analog circuit and coverage-driven verification
of analog and mixed-signal models.
Jaeha Kim is currently an Assistant Professor at Seoul National University (SNU), Seoul, Korea and his
research interests include low-power mixed-signal circuit design and their verification methodologies. Prior
to joining SNU, Prof. Kim was with Stanford University as Acting Assistant Professor, with Rambus, Inc.
as Principal Engineer, and with Inter-university Semiconductor Research Center (ISRC) at SNU as Post-
doctoral Researcher. Dr. Kim is a recipient of the Takuo Sugano award for outstanding far-east paper at
2005 ISSCC and a Distinguished ACM Speaker in the area of design automation.

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This article has been accepted for publication in a future issue of this journal, but has not been

Efficient Global Optimization of Analog Circuits using Predictive

Jiho Lee1 and Jaeha Kim1

Abstract─ An efficient global optimization method is presented. Typically, simulation-based optimizers

A. Design Space Discretization and Initial Pilot Sampling

B. Response Surface Models (RSMs) for Predicting Circuit Performance Distribution

 (x)  MSE[  0(x)] (EQ 2)

C. Expected Improvement and Expected Feasibility Metrics

EI(x) = E[max(P(x) - Popt , 0)] (EQ 3)

EF(x)  E[prob(P(x)   const )] (EQ 4)

D. Candidate Design Selection and Termination Criteria

III. Experimental Results

Discretize Design Space

Select and Evaluate Pilot Samples

Construct Response Surface

Find Candidate with Max. Enhancement

Fig. 1. Overall flow of global optimization algorithm

Fig. 5. Comparison between gradient-based searching and RSM-based searching on discretized

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