Multigate Device: Industry Need
Multigate Device: Industry Need
Multigate Device: Industry Need
In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing
more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced
current in the "on" state, also known as drive current. These advantages translate to lower power
consumption and enhanced device performance. Nonplanar devices are also more compact than
conventional planar transistors, enabling higher transistor density which translates to smaller
overall microelectronics.
[edit] Flexfet
[edit] FinFETs
The term FinFET was coined by University of California, Berkeley researchers (Profs.
Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate
transistor built on an SOI substrate,[5] based on the earlier DELTA (single-gate) transistor design.
[6]
The distinguishing characteristic of the FinFET is that the conducting channel is wrapped
around a thin silicon "fin", which forms the body of the device. The dimensions of the fin
determine the effective channel length of the device.
In current usage the term FinFET has a less precise definition. Among microprocessor
manufacturers, AMD, IBM, and Motorola describe their double-gate development efforts as
FinFET development whereas Intel avoids using the term to describe their closely related tri-gate
[1] architecture. In the technical literature, FinFET is used somewhat generically to describe any
fin-based, multigate transistor architecture regardless of number of gates.
A 25-nm transistor operating on just 0.7 Volt was demonstrated in December 2002 by Taiwan
Semiconductor Manufacturing Company. The "Omega FinFET" design, named after the
similarity between the Greek letter "Omega" and the shape in which the gate wraps around the
source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and
0.88 ps for the P-type.
Schematic view (L) and SEM view (R) of Intel tri-gate transistors
Tri-gate or 3-D are terms used by Intel Corporation to describe their nonplanar transistor
architecture planned for use in future microprocessor technologies. These transistors employ a
single gate stacked on top of two vertical gates allowing for essentially three times the surface
area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume
far less power than current transistors.
In the technical literature, the term tri-gate is sometimes used generically to denote any
multigate FET with three effective gates or channels.
Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds
the channel region on all sides. Depending on design, gate-all-around FETs can have two or four
effective gates. Gate-all-around FETs have been successfully built around silicon nanowire.[7]