VLSI Interview Questions and Answers

VLSI Interview Questions and Answers
Q1). Explain how logical gates are controlled by Boolean logic?

Ans: In Boolean algebra, the true state is denoted by the number one, referred as logic one or
logic high. While, the false state is represented by the number zero, called logic zero or logic
low. And in the digital electronic, the logic high is denoted by the presence of a voltage
potential.
Q2).Mention what are the different gates where Boolean logic are applicable?
Ans:
 NOT Gate:It has one out input and one output. For example, if the value of A= 0 then
the Value of B=1 and vice versa
 AND Gate:It has one output due to the combination of two output. For example, if the
value of A and B= 1 then value of Q should be 1
 OR Gate:Either of the value will show the same output. For example, if the value of A is
1 or B is 0 then value of Q is 1
Q3).Explain how binary number can give a signal or convert into a digital signal?
Ans: Binary number consists of either 0 or 1, in simple words number 1 represents the ON state
and number 0 represents OFF state. These binary numbers can combine billion of machines into
one machines or circuit and operate those machines by performing arithmetic calculations and
sorting operations.
Q5). Explain what is a sequential circuit?

Ans: A sequential circuit is a circuit which is created by logic gates such that the required logic
at the output depends not only on the current input logic conditions, but also on the sequences
past inputs and outputs.
Q6).Explain how Verilog is different to normal programming language?

Ans: Verilog can be different to normal programming language in following aspects
 Simulation time concept

 Multiple threads
 Basic circuit concepts like primitive gates and network connections
Q7). Explain what is Verilog?

Ans: Verilog is an HDL (Hardware Description Language) for describing electronic circuits and
systems. In Verilog, circuit components are prepared inside a Module. It contains both
behavioral and structural statements. Structural statements signify circuit components like logic
gates, counters and micro-processors. Behavioral statements represent programming aspects like
loops, if-then statements and stimulus vectors.
Q8). In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

Q9). Mention what are the two types of procedural blocks in Verilog?
Ans: The two types of procedural blocks in Verilog are
 Initial:Initial blocks runs only once at time zero

 Always:This block loop to execute over and again and executes always, as the name
suggests
Q10). Explain why present VLSI circuits use MOSFETs instead of BJTs?
Ans: In comparison to BJT, MOSFETS can be made very compact as they occupy very small
silicon area on IC chip and also in term of manufacturing they are relatively simple. Moreover,
digital and memory ICs can be employed with circuits that use only MOSFETs, i.e., diodes,
resistors, etc.
Q11).Mention what are three regions of operation of MOSFET and how are they used?
Ans: MOSFET has three regions of operations
 Cut-off region
 Triode region
 Saturation region
The triode and cut-off region are used to function as a switch, while, saturation region is used to
operate as an amplifier.
Q12).Explain what is the depletion region?

Ans: When positive voltage is transmitted across Gate, it causes the free holes (positive charge)
to be pushed back or repelled from the region of the substrate under the Gate. When these holes
are pushed down the substrate, they leave behind a carrier depletion region.
Q13).Explain why is the number of gate inputs to CMOS gates usually limited to four?
Ans: Higher the number of stacks, slower the gate will be. In NOR and NAND gates the number
of gates present in the stack is usually alike as the number of inputs plus one. So input are
restricted to four.
Q16).Explain what is Slack?

Ans: Slack is referred as a time delay difference from the expected delay to the actual delay in a
particular path. Slack can be negative or positive.
Q18).What are the steps required to solve setup and Hold violations in VLSI?
Ans: There are few steps that has to be performed to solved the setup and hold violations in VLSI. The
steps are as follows:
– The optimization and restructuring of the logic between the flops are carried way. This way the logics
are combined and it helps in solving this problem.
– There is way to modify the flip-flops that offer lesser setup delay and provide faster services to setup a
device.
Modifying the launch-flop to have a better hold on the clock pin, which provides CK->Q that makes the
launch-flop to be fast and helps in fixing the setup violations.
– The network of the clock can be modified to reduce the delay or slowing down of the clock that
captures the action of the flip-flop.
– There can be added delay/buffer that allows less delay to the function that is used.
Q23).What are the different design constraints occur in the Synthesis phase?
Ans: The steps that are involved in which the design constraint occurs are:
1. first the creation of the clock with the frequency and the duty cycle gets created. This clock
helps in maintaining the flow and synchronizing various devices that are used.
2. Define the transition time according the requirement on the input ports.
3. The load values are specified for the output ports that are mapped with the input ports.
4. Setting of the delay values for both the input and output ports. The delay includes the input
and output delay.
5. Specify the case-settings to report the correct time that are matched with the specific paths.
6. The clock uncertainty values are setup and hold to show the violations that are occurring.
Q24).What are the different types of skews used in VLSI?

Ans: There are three types of skew that are used in VLSI. The skew are used in clock to reduce
the delay or to understand the process accordingly. The skew are as follows:
Local skew:
This contain the difference between the launching flip-flop and the destination flip-flop. This
defines a time path between the two.
Global skew:
Defines the difference between the earliest component reaching the flip flow and the the latest
arriving at the flip flow with the same clock domain. In this delays are not measured and the
clock is provided the same.
Useful skew:
Defines the delay in capturing a flip flop paths that helps in setting up the environment with
specific requirement for the launch and capture of the timing path. The hold requirement in this
case has to be met for the design purpose.
Q27).What is the difference between the mealy and moore state machine?
Ans:
– Moore model consists of the machine that have an entry action and the output depends only on
the state of the machine, whereas mealy model only uses Input Actions and the output depends
on the state and also on the previous inputs that are provided during the program.
– Moore models are used to design the hardware systems, whereas both hardware and software
systems can be designed using the mealy model.
– Mealy machine’s output depend on the state and input, whereas the output of the moore
machine depends only on the state as the program is written in the state only.
– Mealy machine is having the output by the combination of both input and the state and the
change the state of state variables also have some delay when the change in the signal takes
place, whereas in Moore machine doesn’t have glitches and its ouput is dependent only on states
not on the input signal level.
Q28).What is the difference between Synchronous and Asynchronous reset?

Ans:
– Synchronous reset is the logic that will synthesize to smaller flip-flops. In this the clock works
as a filter providing the small reset glitches but the glitches occur on the active clock edge,
whereas the asynchronous reset is also known as reset release or reset removal. The designer is
responsible of added the reset to the data paths.
– The synchronous reset is used for all the types of design that are used to filter the logic glitches
provided between the clocks. Whereas, the circuit can be reset with or without the clock present.
– Synchronous reset doesn’t allow the synthesis tool to be used easily and it distinguishes the
reset signal from other data signal. The release of the reset can occur only when the clock is
having its initial period. If the release happens near the clock edge then the flip-flops can be
metastable.
Q29).What are the different design techniques required to create a Layout for Digital
Circuits?
Ans: The different design techniques to create the Layout for digital circuits are as follows:
– Digital design consists of the standard cells and represent the height that is required for the
layout. The layout depends on the size of the transistor. It also consists of the specification for
Vdd and GND metal paths that has to be maintained uniformly.
– Use of metal in one direction only to apply the metal directly. The metal can be used and
displayed in any direction.
– Placing of the substrate that place where it shows all the empty spaces of the layout where
there is resistances.
– Use of fingered transistors allows the design to be more easy and it is easy to maintain a
symmetry as well.
Q30).Write a program to explain the comparator?

Ans: To make a comparator there is a requirement to use multiplexer that is having one input
and many outputs. This allows the choosing of the maximum numbers that are required to design
the comparator. The implementation of the 2 bit comparator can be done using the law of
tigotomy that states that A > B, A < B, A = B (Law of trigotomy). The comparator can be
implemented using:
combinational logic circuits or multiplexers that uses the HDL language to write the schematic at
RTL and gate level.
Behavioral model of comparator represented like:
module comp0 (y1,y2,y3,a,b);
input [1:0] a,b;
output y1,y2,y3;
wire y1,y2,y3;
assign y1= (a >b)? 1:0;
assign y2= (b >a)? 1:0;
assign y3= (a==b)? 1:0;
endmodule
Q36).What is the difference between CMOS and Bipolar technologies?

Ans:
– CMOS technology allows the power dissipation to be low and it gives more power output, whereas
bipolar takes lots of power to run the system and the ciricutary require lots of power to get activated.
– CMOS technology provides high input impedance that is low drive current that allow more current to
be flown in the cirucit and keep the circuit in a good position, whereas it provides high drive current
means more input impedance.
– CMOS technology provides scalable threshold voltage more in comparison to the Bipolar technology
that provides low threshold voltage.
– CMOS technology provides high noise margin, packing density whereas Bipolory technology allows to
have low noise margin so that to reduce the high volues and give low packing density of the
components.

VLSI Interview Questions and Answers

Uploaded by

Copyright:

Available Formats

VLSI Interview Questions and Answers

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VLSI Interview Questions and Answers

Uploaded by

Copyright:

Available Formats

VLSI Interview Questions and Answers

Q1). Explain how logical gates are controlled by Boolean logic?

Q5). Explain what is a sequential circuit?

Q6).Explain how Verilog is different to normal programming language?

 Simulation time concept

Q7). Explain what is Verilog?

Q8). In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

 Initial:Initial blocks runs only once at time zero

Q12).Explain what is the depletion region?

Q16).Explain what is Slack?

Q24).What are the different types of skews used in VLSI?

Q28).What is the difference between Synchronous and Asynchronous reset?

Q30).Write a program to explain the comparator?

Q36).What is the difference between CMOS and Bipolar technologies?

You might also like