International Journal of Engineering Research & Technology (IJERT)

ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

A New Topology for 31-Level Cascaded Multilevel Inverter

With Reduced Number of Switches

Ch.Sajan T.Praveen Kumar K.Srilatha

Associate professor, Associate professor, P.G. student,
Dept of EEE, Dept of EEE, Dept of EEE,
Jyothishmathi Institute Jyothishmathi Institute Jyothishmathi Institute
of technology & science, of technology & science, of technology & science,
Karimnagar, A.P., India Karimnagar, A.P., India Karimnagar, A.P., India

I. Introduction
Abstract Numerous industrial applications have begun
to require high power apparatus in recent years.
In this paper, a new topology is composed of Multilevel inverters have become more popular
Voltage sources that are connected in over the years in industrial propel applications and
series/parallel by the switching devices makes it high power applications with the promise of less
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easily extensible to higher number of output voltage disturbances, smaller common-mode voltage, the
levels associated with less number of switches, possibility to function at lower switching
capacitors, gate driver circuits, protection circuits frequencies, and good potential for further
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for switches and blocking voltage on switches. The developments than ordinary two-level inverters.
size, complexity and power consumption in the gate Though Conventional two-level inverters are
driving circuits is also reduced. Reduction of rating effective, but create harmonic distortions in the
of the switches is another advantage. The total output voltage, EMI and high dv/dt (compared to
harmonic distortion (THD) is reduced with more multilevel inverters). As a result the most
number of steps in output voltage without using attractive applications of multilevel inverters are in
pulse width modulation techniques. This topology is the medium to high voltage ranges. The concept of
proposed to get high 31 levels. Simulation results Multilevel Inverters does not depend on just two
are shown and compared with theoretical results. levels of voltage to create an AC signal. Instead
In the asymmetric topologies, the values of dc several voltage levels are added to each other to
voltage sources magnitudes are unequal or create a smoother stepped waveform with lower
changed dynamically. If the voltage sources are dv/dt and lower harmonic distortions. With more
changed during the converter operation, the voltage levels in the inverter, the waveform
voltage balancing should be done for active power becomes smoother, but with many levels the
transfer. In this paper voltage balancing technique design becomes more complicated, with more
is analyzed for cascaded multilevel inverter which components. A multilevel converter not only
shows how to operate the converter in order to achieves high power rating, but also enables the
maintain equal charge/discharge rates from the dc use of renewable energy sources such as
sources and Simulation results for active power photovoltaic, wind, and fuel cells can be easily
transfer & reactive power transfer are shown. interfaced to a multilevel converter system for a
high power application. Proposed topology has
fewer switches than that of in symmetric topology.

Several multilevel inverter topologies have

been developed like flying capacitor, neutral point
clamped, Cascaded H-bridge (CHB). Among these

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

topologies, the cascaded H bridge inverter has II. Proposed Topology

received much attention. The advantages of In this paper, the proposed multilevel inverter
cascaded multilevel inverters are: not only has the modularity feature of cascaded
 Requires less number of components per topologies but also consists of the ability of series
level and parallel connections of dc voltage sources.
 Modularized structure without clamping Series and parallel connections of the dc voltage
components sources increase the output voltage levels or given
 Possibility to implement soft-switching current to the multilevel inverter, respectively. In
the proposed topology, the magnitude of the dc
 Simple voltage balancing modulation. voltage sources differs from one unit to another.
And disadvantages are:
 Needs separate isolated DC sources for
real power transfer
 No common DC-bus
The proposed topology is of cascaded
multilevel inverter with asymmetrical
configuration, since it uses several levels of dc
voltage sources, which would be available from
batteries, ultra capacitors, or fuel cells. Because of
these several levels of dc sources may cause
voltage unbalances which leads to the increase of
harmonics and total harmonic distortion. Proposed Figure 1. Proposed basic unit.
topology shows how to operate this converter in
order to maintain equal charge/discharge rates When the switches S0 and Sc1 become ON,
from the dc sources. This is called voltage the voltage level at the output is zero. By turning
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balancing technique in the multilevel inverter. on the switches S1, Sb1, and Sc1, the two dc
With this technique the harmonic content is also voltage sources are paralleled and Vdc is produced
reduced. Since switching frequency is restricted by at the output. Similarly, when the switches S1 and
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switching losses in high power and high voltage Sa1 become ON, the two dc voltage sources could
applications, multilevel inverters have found wide be connected in series and 2Vdc is produced at the
acceptance as they can achieve a low harmonic output as shown in table 1.
component with low switching frequency.
Furthermore, low blocking voltage by switching Table 1. Switching sequence for Basic unit.
devices is the other advantage of this type of
converters as well as minimum harmonic
distortion and switching losses.
The blocked voltage by each switch in a
specific unit is same as the other switches used in
the same unit and is equal to the magnitude of the
dc voltage source used in the unit. Therefore, the
number of gate driving circuits is reduced and as a
result the size of multilevel inverter and its power
consumption are reduced. Another feature of the
proposed topology is that there is any kind of
necessity to bidirectional switches. In this paper, a
new procedure is recommended to find out the
magnitude of the dc voltage sources and produce
all output voltage levels. Finally, a method to find
out the optimal number of switches and dc voltage
sources so that have the maximum output voltage
levels with the minimum blocked voltage by
switches is presented.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

III. Principle of Operation In a conventional cascaded multilevel inverter,

the number of output phase voltage levels is
defined by, n= 2m+1, where m is the number of
dc voltage sources. Each H-bridge requires a dc
source and 4 switches. 12 switching devices are
needed for 7 levels, 16 switching devices are
needed for 9 levels, and 20 switching devices are
needed for 31 levels, which make an inverter
complicated.

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Figure 2. Proposed Topology for n-level
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The proposed topology of multilevel inverter

for n-level is shown in Figure 2. It consists of three
bridges that are two upper H-bridges and the lower
H-bridge with series/parallel circuit, which are
cascaded. The principle of operation of lower H-
bridge with series/parallel circuit is shown in table
2. By using this principle high numbers of steps
are obtained at output.

Table 2. Principle of operation of series/parallel

circuit Figure 3. For 31-level output.

But the proposed inverter outputs 12n +7

levels, where n is number of dc voltage sources in
series/parallel circuit. Total number of switching
devices required is 3n + 9, which makes the output
voltage of the inverter almost sinusoidal. Figure 3.
shows the proposed topology for 31 level output, it
consists of 2 voltage sources in the series/parallel
circuit.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

Table 3. Switching sequence for 31 level output. IV. Design and Analysis
Switches closed Vout The Matlab/Simulink model of the proposed
S2,S4,S6,S8,S10,S12 0 inverter for 31 level output is shown in Figure 4. It
consists of two upper H-bridges are cascaded with
S9,S12 0.5Vo lower H-bridge of series/parallel circuit.
S5,S8 Vo Simulation is performed for the proposed circuit
S5,S8,S9,S12 1.5 Vo with MATLAB/SIMULINK.
Sc1,S1,S4,S6,S7 2 Vo
Sc1,S1,S4,S10,S11 2.5 Vo
Sc1,S1,S4 3 Vo
Sc1,S1,S4,S9,S12 3.5 Vo
Sc1,S1,S4, S5,S8 4 Vo
Sc1,S1,S4,S5,S8,S9,S12 4.5 Vo
Sa1,S1,S4,S6,S7 5 Vo
Sa1,S1,S4,S10,S11 5.5 Vo
Sa1,S1,S4 6 Vo
Sa1,S1,S4,S9,S12 6.5 Vo
Sa1,S1,S4,S5,S8 7 Vo
Sa1,S1,S4,S5,S8,S9,S12 7.5 Vo
S10,S11 -0.5 Vo
S6,S7 - Vo
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S6,S7, S10,S11 -1.5 Vo
Sc1, S2,S3,S5,S8 -2Vo Figure 4. Mat lab/Simulink model for 31 level
output.
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Sc1, S2,S3, S9,S12 -2.5 Vo

Sc1, S2,S3 -3 Vo
Sc1, S2,S3, S10,S11 -3.5 Vo
Sc1, S2,S3, S6,S7 -4 Vo
Sc1,S2,S3,S6,S7,S10,S11 -4.5 Vo
Sa1,S2,S3,S5,S8 -5 Vo
Sa1,S2,S3, S9,S12 -5.5 Vo
Sa1,S2,S3 -6 Vo
Sa1,S2,S3, S10,S11 -6.5 Vo
Sa1,S2,S3, S6,S7 -7 Vo
Sa1,S2,S3, S6,S7,S10,S11 -7.5 Vo

Assuming the voltage ratio for 31 level Figure 5. Simulation result for 31 level output.
cascaded multilevel inverter voltage sources as
1:2:6, the inverter requires 15 switching devices 5V for first upper H-bridge, 10V for second
for 31 levels, which is shown in Figure 3. Two upper H-bridge, and two voltage sources of
voltage sources are required in series/parallel series/parallel circuit are 30V each maintaining the
circuit, levels are obtained by the Eq. (1) and the ratio of 1:2:6, then the amplitude of the inverter’s
switching sequence is shown in Table 3. output voltage waveform for 31 levels is 73.3V.
V𝑜𝑢𝑡=𝑣1+𝑣2+𝑣3 (1)

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

which uses lesser number of bridges. This scheme

therefore provides the capability to produce higher
voltages at higher speeds with low switching
frequency which has inherent low switching losses
and high converter efficiency. Although the
cascaded converter has an inherent self-balancing
characteristic, a slight voltage imbalance can occur
because of the circuit component losses.
Obviously, the primary attraction of the Cascaded
Multilevel converter topology is its modularity.
However, Cascaded topology requires an
excessive amount of DC voltage sources. The most
important factors causing the voltage imbalance
among these DC capacitors are the difference in
the power stage losses and the component
Figure 6. Experimental 31-level output voltage tolerances. The internal losses may be differently
and current. influenced by the switching and conduction
activity and the component tolerances. To achieve
Figure 5 and Figure 6 shows the 31 level steady-state, balanced voltages, these DC
output Voltage and current Waveforms without capacitors must have the same amount of real
PWM. It is clear that as the number of level power utilization in a given period of time. Due to
increases, distortion reduces. Switches required in sharing the same output current, the differences in
the proposed topology compared to other the capacitor currents are caused by the different
topologies are shown in figure 7. duty cycles, because a capacitor current is a
product of a duty cycle and an output current.
Therefore, the average switching functions or duty
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cycles in these H-bridge converters must be
identical.
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VI. Voltage-Balancing Technique

The Cascaded Multilevel Inverter with its use
of several voltage sources is suitable in Electric
Vehicles (EV) since battery cells is the power
source. The battery cells may not always be equal
and depending on the output demand the cells may
be discharged unequally. The above proposed
topology is composed of series basic units which
Figure 7. Comparison with other topologies are consisted of series and parallel connections of
dc voltage sources. The values of the dc voltage
From the above figure it is shown that less sources differ from one unit to another. Even
number of switches are required in the proposed though the same output voltages are generated, the
topology. Hence complexity is reduced for high currents flowing in the circuits have different
number of levels. paths. This means that different DC capacitors see
different current waveforms. Consequently, the
V. Voltage Balancing DC capacitors have different voltage profiles. It is
Asymmetric multilevel inverters have the same therefore important to investigate the voltage
topology as symmetric multilevel inverters. They source unbalance problem in the Cascaded
differ only in the rating of input dc voltages and Multilevel Inverters.
control strategies. For many applications it is The voltage unbalance problem can be solved
troublesome to use separate dc sources and too with the modulation by choosing a switch state
many dc sources will require many long cables and that corrects the unbalance. This can also be called
could lead to voltage imbalance among the dc prioritizing. By prioritizing in which order that
sources. To reduce the number of dc sources voltage sources are to be used the workload can be
required for the cascaded H-bridge multilevel divided between the sources so that they are held
inverter, Asymmetrical configuration is proposed balanced. The prioritizing order is dependent on

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

the current direction and if voltage amplitude is models connected to each module capacitor,
negative or positive. If, for example, a capacitor in recharging them over time so that they do not run
a full-bridge module for the Cascaded Multilevel out of stored energy.
Inverter (CMI) has a higher charge (and therefore
higher potential) that certain module can be given
the heaviest workload during a period where the
capacitor is going to be discharged (positive
voltage and current owing to the load), lowering
the voltage closer to the wanted value. The
strategy can also work the other way around, to
charge capacitors with lower potential by
connecting them to the load, with positive
potential forward, when current is owing from the
load, or vice versa. However, this strategy is most
effective when transferring active power. When
transferring only reactive power the sources does
not get unbalanced and this balancing strategy is
not necessary.

VII. Design Example

Voltage balancing technique is well explained with
this following example, in which the simulation
model shown for 5-level cascaded multilevel
inverter.
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Figure 9. Simulation results of 5level CMI.
a) Reactive power transfer capacitor voltages.
b) Active/mixed power transfer capacitor voltages.
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c) Reactive power transfer load voltage and

current. d) Active power transfer load voltage and
current.

VIII. Conclusion
Cascaded multilevel inverters in addition to
acceptable reliability and simple control, provide a
Figure 8. 5level Cascaded multilevel inverter better voltage waveform than the other types of
simulation model for voltage balancing. multilevel inverters. In this paper, a new cascaded
multilevel inverter topology was proposed which
The Cascaded Multilevel Inverter (CMI) with was connected to the dc voltage sources in series
its use of several voltage sources is suitable in and parallel. The suggested topology needs less
Electric Vehicles (EV) since battery cells is the number of switching devices with minimum
power source. The battery cells may not always be standing voltage. THD is also reduced without
equal and depending on the output demand the using modulation techniques. And the proposed
cells may be discharged unequally. It is therefore topology shows how to operate the Cascaded
important to investigate the voltage source multilevel inverter without any voltage unbalance
unbalance problem in the Cascaded multilevel problems. The simulation results are shown which
inverter. are accorded with the theoretical results. The
The 5 level CMI shown in above figure 8. is proposed inverter is used in high power
connected to an active/mixed power load and a applications like EV and HEV drives.
pure reactive power load can be seen. Each
capacitor where charged to 500V during the
beginning of the simulation with the charging
voltage source. The charging voltage source where
disconnected after the circuit reached steady-state
operation. It should be noted that there are battery

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 9, September - 2013

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