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Assignment Week4

The document provides solutions to 9 multiple choice questions about Verilog concepts. Question 1 asks about valid targets for procedural assignment statements and the answer is that a "wire" type variable cannot be assigned. Question 2 provides code to calculate the final value of variable "c", which is 75. Question 3 is similar but uses non-blocking assignments, with the final value of "c" being 65.

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saigdv1978
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258 views

Assignment Week4

The document provides solutions to 9 multiple choice questions about Verilog concepts. Question 1 asks about valid targets for procedural assignment statements and the answer is that a "wire" type variable cannot be assigned. Question 2 provides code to calculate the final value of variable "c", which is 75. Question 3 is similar but uses non-blocking assignments, with the final value of "c" being 65.

Uploaded by

saigdv1978
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Week 4: Assignment Solutions

1. Which of the following cannot be used as the target of a procedural


assignment statement?
a. A part select of a “reg” type variable.
b. An “integer” type variable.
c. An output signal of a module that is also declared as “reg”.
d. A “wire” type variable.
Correct answer is (d).
In a procedural assignment statement, only register type variables or part
select thereof can be used in the left hand side. A wire type variable
cannot be assigned a value within a procedural block.
2. For the following code segment, the final value of variable “c” will be
…………..
integer a, b, c;
initial
begin
a = 55; b = 10; c = 5;
a = b * c;
b = a – 25;
c = a + b;
end
Correct answer is 75.
In blocking assignments, statements are executed one after the other.
First assignment: a = 10 * 5 = 50
Second assignment: b = 50 – 25 = 25
Third assignment: c = 50 + 25 = 75
3. For the following code segment, the final value of variable “c” will be
…………..
integer a, b, c;
initial
begin
a = 55; b = 10; c = 5;
end
initial
begin
a <= #10 b * c;
b <= #10 a – 25;
c <= #10 a + b;
end
Correct answer is 65.
In non-blocking statements inside a procedural block, all right hand side
expressions are evaluated in parallel, and are assigned to the left hand side
variables all together.
First assignment: a = 10 * 5 = 50
Second assignment: b = 55 – 25 = 30
Third assignment: c = 55 + 10 = 65
4. What will the following code segment do?
always @(posedge clock)
begin
red = blue;
blue = red;
end
a. Exchange the values of the variables “red” and “blue”.
b. Both variables will get the value previously stored in “red”.
c. Both variables will get the value previously stored in “blue”.
d. None of the above.
Correct answer is (c).
Because the assignments are blocking, first, the value of “blue” will be
assigned to “red”, and then the new value of “red” will be assigned to
“blue”. Thus both the variables “red” and “blue” will get the previous value
stored in “blue”.
5. If the 8-bit variable “data” declared as “reg [7:0] data” is initialized to
8’b10100110, what will be its value after execution of the following code
segment?
always @(posedge clock)
begin
data = data << 1;
data[0] = data[7];
end
a. 8’b01001100
b. 8’b01001101
c. 8’b11001101
d. 8’b11001100
Correct answer is (a).
First data is left shifted by 1 position; its value will become 8’b01001100.
Then data[7], which is 0, is assigned to data[0], which is also 0. So there
will be no change, and the value will remain 8’b01001100.
6. What will the following code segment generate on synthesis, assuming
that the four variables y0, y1, y2 and y3 map into four latches / flip-flops?
always @(posedge clock)
begin
y3 = in;
y2 = y3;
y1 = y2;
y0 = y1;
end
a. A 4-bit shift register.
b. A 4-bit parallel-in parallel-out register.
c. Four D flip-flops all fed with the data “in”.
d. None of the above.
Correct answer is (c).
Since blocking assignment statements are executed one after another,
the value of “in” will be first assigned to “y3”, then to “y2”, then to “y1”,
and finally to “y0”. So the same input will feed all the four D flip-flops
in the synthesized circuit.
7. What will the following code segment generate on synthesis?
always @(posedge clock)
begin
y3 <= in;
y2 <= y3;
y1 <= y2;
y0 <= y1;
end
a. A 4-bit shift register.
b. A 4-bit parallel-in parallel-out register.
c. Four D flip-flops all fed with the data “in”.
d. None of the above.
Correct answer is (a).
Since we use non-blocking assignments, the values on the RHS are
assigned to the variables on the LHS in synchronism with the clock. This
will generate a 4-bit shift register.
8. Which of the following are true for “generate” blocks?
a. Multiple copies of code blocks are generated dynamically before
simulation or synthesis.
b. Can be used to instantiate multiple copies of some module.
c. Must be used along with a variable of type “genvar”.
d. None of the above.
Correct answersare (a), (b) and (c).
All of (a), (b) and (c) are true for “generate” blocks.
9. Which of the following are false for user defined primitives in Verilog?
a. Can be used to specify a combinational circuit with any number of
outputs.
b. Can be used to specify a finite state machine with one or two state
variables.
c. Don’t care or unspecified values are not allowed in the description.
d. None of the above.
Correct answer is (a), (b) and (c).
We can specify a combinational circuit with only one output.
We can specify a FSM with only one state variable.
We can use don’t care (denoted by “?”) to make the description more
compact.

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